TLV9001S

TLV9001_1810 TI1 | Alldatasheet

Document overview

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Technical content

= 1 + V V OUT IN R R F G 1 + sR C1 1( ( ( ( 2/c112 R C1 1 f =/c45 3 dB Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 TLV900xLow-Power,RRIO,1-MHzOperationalAmplifierforCost-SensitiveSystems

1 Features

1• Scalable CMOS Amplifier for Low-Cost

Applications

• Rail-to-Rail Input and Output
• Low Input Offset Voltage: ±0.4 mV
• Unity-Gain Bandwidth: 1 MHz
• Low Broadband Noise: 27 nV/√Hz
• Low Input Bias Current: 5 pA
• Low Quiescent Current: 60 µA/Ch
• Unity-Gain Stable
• Internal RFI and EMI Filter
• Operational at Supply Voltages as Low as 1.8 V
• Easier to Stabilize With Higher Capacitive Load Due to Resistive Open-Loop Output Impedance
• Extended Temperature Range: –40°C to +125°C

2 Applications

• Smoke Detectors
• Motion Detectors
• Wearable Devices
• Large and Small Appliances
• EPOS
• Barcode Scanners
• Sensor Signal Conditioning
• Power Modules
• Personal Electronics
• Active Filters
• HVAC: Heating, Ventilating, and Air Conditioning
• Motor Control: AC Induction
• Low-Side Current Sensing

3 Description

The TLV900x family includes single (TLV9001), dual (TLV9002), and quad-channel (TLV9004) low-voltage (1.8 V to 5.5 V) operational amplifiers (op amps) with rail-to-rail input and output swing capabilities. These op amps provide a cost-effective solution for space- constrained applications such as smoke detectors, wearable electronics, and small appliances where low-voltage operation and high capacitive-load drive are required. The capacitive-load drive of the TLV900x family is 500 pF, and the resistive open- loop output impedance makes stabilization easier with much higher capacitive loads. These op amps are designed specifically for low-voltage operation (1.8 V to 5.5 V) with performance specifications similar to the TLV600x devices. The robust design of the TLV900x family simplifies circuit design. The op amps feature unity-gain stability, an integrated RFI and EMI rejection filter, and no-phase reversal in overdrive conditions. The TLV900x devices include a shutdown mode (TLV9001S, TLV9002S and TLV9004S) that allow the amplifiers to switch off into standby mode with typical current consumption less than 1 µA. Micro-size packages, such as SOT-553 and WSON, are offered for all channel variants (single, dual, and quad), along with industry-standard packages such as SOIC, MSOP, SOT-23 and TSSOP packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV9001 SOT-23 (5) 1.60 mm × 2.90 mm SC70 (5) 1.25 mm × 2.00 mm SOT-553 (5) (2) 1.65 mm × 1.20 mm X2SON (5) 0.80 mm × 0.80 mm TLV9001S SOT-23 (6) 1.60 mm × 2.90 mm TLV9002 SOIC (8) 3.91 mm × 4.90 mm WSON (8) 2.00 mm × 2.00 mm VSSOP (8) 3.00 mm × 3.00 mm TSSOP (8) 3.00 mm × 4.40 mm TLV9002S VSSOP (10) 3.00 mm × 3.00 mm X2QFN (10) (2) 1.50 mm × 2.00 mm TLV9004 SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 4.40 mm × 5.00 mm WQFN (16) 3.00 mm × 3.00 mm WQFN (14) (2) 2.00 mm × 2.00 mm TLV9004S WQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Package is for preview only. Single-Pole, Low-Pass Filter

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Table of Contents

12.3 Receiving Notification of Documentation Updates 33

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (August 2018) to Revision G Page Changes from Revision E (July 2018) to Revision F Page Changes from Revision D (June 2018) to Revision E Page

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated Changes from Revision C (May 2018) to Revision D Page Changes from Revision B (March 2018) to Revision C Page Changes from Revision A (December 2017) to Revision B Page

• Added package preview notes to TLV9001 packages, TLV9004 packages, and TLV9002 8-pin VSSOP package in
• Added package preview notes to TLV9001, TLV9004 and TLV9002 VSSOP package pinout drawings in Pin
• Deleted package preview note from TLV9002 DSG (WSON) pinout drawing in Pin Configurations and Functions section. 7
• Deleted package preview note from TLV9002 RUG (X2QFN) pinout drawing in Pin Configurations and Functions section 8 Changes from Original (October 2017) to Revision A Page

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

5 Device Comparison Table

NO. OF CHANNEL S PACKAGE LEADS SC70 DRL SOIC D SOT-23 DBV SOT-553 DCK TSSOP PW VSSOP DGK WQFN RTE WSON DSG X2QFN RUC X2SON DPW TLV9002 2 — 8 — — 8 8 8 — TLV9004 4 — 14 — — 14 — 16 — 14 —

2IN±

4 IN+

2V± 3IN± 4 OUT 5 V+ Not to scale 1OUT 2V± 3IN+ 4 IN ± 5 V+ Not to scale TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

6 Pin Configuration and Functions

TLV9001 DBV and DRL Package, TLV9001 DCK Package 5-Pin SOT-23, SC-70 and SOT-553 Top View 5-Pin SC70, 5-Pin SOT-23 Top View 5-Pin X2SON Top View Pin Functions: TLV9001 PIN I/O DESCRIPTION NAME NO. SOT-23, SC-70(T), SOT-553 SC70, SOT-23(U) X2SON IN– 4 3 2 I Inverting input IN+ 3 1 4 I Noninverting input OUT 1 4 1 O Output V– 2 2 3 I or — Negative (low) supply or ground (for single-supply operation) V+ 5 5 5 I Positive (high) supply

2V± 5 SHDN 3IN+ 4 IN ± Not to scale TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated 6-Pin SOT-23 Top View Pin Functions: TLV9001S PIN I/O DESCRIPTION NAME NO. IN– 4 I Inverting input IN+ 3 I Noninverting input OUT 1 O Output SHDN 5 I Shutdown (low), enabled (high) V– 2 I or — Negative (low) supply or ground (for single-supply operation) V+ 6 I Positive (high) supply

2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Not to scale Thermal Pad 1OUT1 8 V+ 2IN1± 7 OUT2 3IN1+ 6 IN2 ± 4V± 5 IN2+ Not to scale TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated TLV9002 D, DGK, PW Packages 8-Pin SOIC, VSSOP, TSSOP Top View TLV9002 DSG Package (1) 8-Pin WSON With Exposed Thermal Pad Top View (1) Connect thermal pad to V– Pin Functions: TLV9002 PIN I/O DESCRIPTION NAME NO. IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 I or — Negative (low) supply or ground (for single-supply operation) V+ 8 I Positive (high) supply

1V± 2SHDN1 3SHDN2 4IN2+ 5IN2±

6 OUT2

8 OUT1

9 IN1 ±

10 IN1+

2IN1± 9 OUT2 3IN1+ 8 IN2 ± 4V± 7 IN2+ 5SHDN1 6 SHDN2 Not to scale TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated 10-Pin VSSOP Top View TLV9002S RUG Package (1) 10-Pin X2QFN Top View (1) Package is preview only Pin Functions: TLV9002S PIN I/O DESCRIPTION NAME NO. VSSOP X2QFN IN1– 2 9 I Inverting input, channel 1 IN1+ 3 10 I Noninverting input, channel 1 IN2– 8 5 I Inverting input, channel 2 IN2+ 7 4 I Noninverting input, channel 2 OUT1 1 8 O Output, channel 1 OUT2 9 6 O Output, channel 2 SHDN1 5 2 I Shutdown – low = disabled, high = enabled, channel 1 SHDN2 6 3 I Shutdown – low = disabled, high = enabled, channel 2 V– 4 1 I or — Negative (low) supply or ground (for single-supply operation) V+ 10 7 I Positive (high) supply

1IN1± 2IN1+ 3V+ 4IN2+ 5IN2± 6OUT2 7OUT3

8 IN3 ±

9 IN3+

10 V ±

11 IN4+

12 IN4 ±

13 OUT4

14 OUT1

16 IN1 ±5OUT2

15 OUT16NC

2V+ 11 V ±

14 OUT47NC

13 IN4 ±8OUT3

4IN2± 9 IN3 ± Not to scale Thermal Pad 1OUT1 14 OUT4 2IN1± 13 IN4 ± 3IN1+ 12 IN4+ 4V+ 11 V ± 5IN2+ 10 IN3+ 6IN2± 9 IN3 ± 7OUT2 8 OUT3 Not to scale TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated TLV9004 D, PW Packages 14-Pin SOIC, TSSOP Top View 14-Pin X2QFN Top View 16-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: TLV9004 PIN I/O DESCRIPTION NAME SOIC, TSSOP WQFN X2QFN IN1– 2 16 1 I Inverting input, channel 1 IN1+ 3 1 2 I Noninverting input, channel 1 IN2– 6 4 5 I Inverting input, channel 2 IN2+ 5 3 4 I Noninverting input, channel 2 IN3– 9 9 8 I Inverting input, channel 3 IN3+ 10 10 9 I Noninverting input, channel 3 IN4– 13 13 12 I Inverting input, channel 4 IN4+ 12 12 11 I Noninverting input, channel 4

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Pin Functions: TLV9004 (continued) PIN I/O DESCRIPTION NAME SOIC, TSSOP WQFN X2QFN NC — 6, 7 — — No internal connection OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation) V+ 4 2 3 I Positive (high) supply

15 OUT16SHDN12

2V+ 11 V ±

14 OUT47SHDN34

4IN2± 9 IN3 ± Not to scale Thermal Pad TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated 16-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: TLV9004S PIN I/O DESCRIPTION NAME NO. IN1+ 1 I Noninverting input IN1– 16 I Inverting input IN2+ 3 I Noninverting input IN2– 4 I Inverting input IN3+ 10 I Noninverting input IN3– 9 I Inverting input IN4+ 12 I Noninverting input IN4– 13 I Inverting input SHDN12 6 I Shutdown – low = enabled, high = disabled, channels 1 and 2 SHDN34 7 I Shutdown – low = enabled, high = disabled, channels 3 and 4 OUT1 15 O Output OUT2 5 O Output OUT3 8 O Output OUT4 14 O Output V– 11 I or — Negative (low) supply or ground (for single-supply operation) V+ 2 I Positive (high) supply

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage ([V+] – [V–]) 0 6 V Signal input pins Voltage(2) Common-mode (V–) – 0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 V Current(2) –10 10 mA Output short-circuit(3) Continuous Operating, TA –55 150 °C Junction, TJ 150 °C Storage, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 1.8 5.5 V TA Specified temperature –40 125 °C

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (2) This package option for TLV9001 is preview only.

7.4 Thermal Information: TLV9001

THERMAL METRIC (1) TLV9001 UNITDBV (SOT- 23) DCK (SC70) DPW (X2SON) DRL (SOT-553) (2)

5 PINS 5 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 232.9 239.6 470.0 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 148.5 211.9 TBD °C/W RθJB Junction-to-board thermal resistance 100.9 82.3 334.8 TBD °C/W ψJT Junction-to-top characterization parameter 77.2 54.5 29.8 TBD °C/W ψJB Junction-to-board characterization parameter 100.4 81.8 333.2 TBD °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics

7.5 Thermal Information: TLV9001S

THERMAL METRIC (1) TLV9001S UNITDBV (SOT-23)

6 PINS

RθJA Junction-to-ambient thermal resistance 232.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 °C/W RθJB Junction-to-board thermal resistance 100.9 °C/W ψJT Junction-to-top characterization parameter 77.2 °C/W ψJB Junction-to-board characterization parameter 100.4 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (2) This package option for TLV9002 is preview only.

7.6 Thermal Information: TLV9002

THERMAL METRIC(1) TLV9002 UNITD (SOIC) DGK (VSSOP) DGS (VSSOP) DSG (WSON) PW (TSSOP) RUG (X2QFN) (2)

8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS

RθJA Junction-to-ambient thermal RθJC(top) Junction-to-case (top) RθJB Junction-to-board thermal resistance 129.7 122.9 113 68.8 128.6 TBD °C/W ψJT Junction-to-top characterization parameter 26 21.2 15.8 14.7 27.2 TBD °C/W ψJB Junction-to-board (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (2) This package option for TLV9002S is preview only.

7.7 Thermal Information: TLV9002S

THERMAL METRIC (1) TLV9002S UNITDGS (VSSOP) RUG (X2QFN) (2)

10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 169.5 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.1 TBD °C/W RθJB Junction-to-board thermal resistance 113 TBD °C/W ψJT Junction-to-top characterization parameter 15.8 TBD °C/W ψJB Junction-to-board characterization parameter 111.6 TBD °C/W

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (2) This package option for TLV9004 is preview only .

7.8 Thermal Information: TLV9004

THERMAL METRIC(1) TLV9004 UNITD (SOIC) PW (TSSOP) RTE (WQFN) RUC (WQFN) (2)

14 PINS 14 PINS 16 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 102.1 148.3 66.4 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.8 68.1 69.3 TBD °C/W RθJB Junction-to-board thermal resistance 58.5 92.7 41.7 TBD °C/W ψJT Junction-to-top characterization parameter 20.5 16.9 5.7 TBD °C/W ψJB Junction-to-board characterization parameter 58.1 91.8 41.5 TBD °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics

7.9 Thermal Information: TLV9004S

THERMAL METRIC (1) TLV9004S UNITRTE (WQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 66.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.3 °C/W RθJB Junction-to-board thermal resistance 41.7 °C/W ψJT Junction-to-top characterization parameter 5.7 °C/W ψJB Junction-to-board characterization parameter 41.5 °C/W

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

7.10 Electrical Characteristics

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage Vs = 5 V ±0.4 ±1.6 mV Vs = 5 V, TA = –40°C to 125°C ±2 mV dVOS/dT VOS vs temperature TA = –40°C to 125°C ±0.6 μV/°C PSRR Power-supply rejection ratio VS = 1.8 to 5.5 V, VCM = (V–) 80 105 dB INPUT VOLTAGE RANGE VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.1 (V+) + 0.1 V CMRR Common-mode rejection ratio TA = –40°C to 125°C 86 dB TA = –40°C to 125°C 95 TA = –40°C to 125°C 63 77 TA = –40°C to 125°C 68 INPUT BIAS CURRENT IB Input bias current Vs = 5 V ±5 pA IOS Input offset current ±2 pA NOISE En Input voltage noise (peak-to- peak) ƒ = 0.1 Hz to 10 Hz, VS = 5 V 4.7 μVPP en Input voltage noise density ƒ = 1 kHz, VS = 5 V 30 nV/√Hz ƒ = 10 kHz, VS = 5 V 27 nV/√Hz in Input current noise density ƒ = 1 kHz, VS = 5 V 23 fA/√Hz INPUT CAPACITANCE CID Differential 1.5 pF CIC Common-mode 5 pF OPEN-LOOP GAIN AOL Open-loop voltage gain RL = 10 kΩ 104 117 dB RL = 10 kΩ 100 RL = 2 kΩ 130 FREQUENCY RESPONSE GBW Gain-bandwidth product VS = 5 V 1 MHz φm Phase margin VS = 5.5 V, G = 1 78 degrees SR Slew rate VS = 5 V 2 V/µs tS Settling time To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 2.5 μs To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 3 tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.85 μs THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1 f = 1 kHz, 80 kHz measurement BW 0.004% OUTPUT VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 10 20 mV VS = 5.5 V, RL = 2 kΩ 35 55 ISC Short-circuit current Vs = 5.5 V ±40 mA ZO Open-loop output impedance Vs = 5 V, f = 1 MHz 1200 Ω

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Electrical Characteristics (continued) For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) Specified by design and characterization; not production tested. (2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level. (3) Full shutdown refers to the dual TLV9002S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9004S having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter. POWER SUPPLY VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V IQ Quiescent current per amplifier TLV9002, TLV9002S TLV9004, TLV9004S IO = 0 mA, VS = 5.5 V 60 75 µATLV9001, TLV9001S IO = 0 mA, VS = 5.5 V 60 77 IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C 85 SHUTDOWN(1) IQSD Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS– 0.5 1.5 µA ZSHDN Output impedance during shutdown VS = 1.8 V to 5.5 V, amplifier disabled 10 || 2 GΩ || pF High level voltage shutdown threshold (amplifier enabled) VS = 1.8 V to 5.5 V (V–) + 0.9 (V–) + 1.1 V Low level voltage shutdown threshold (amplifier disabled) VS = 1.8 V to 5.5 V (V–) + 0.2 V (V–) +

0.7 V V

Amplifier enable time (full shutdown)(2)(3) VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 70 µs Amplifier enable time (partial shutdown)(2)(3) VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 50 tOFF Amplifier disable time(2) VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL connected to V– 4 µs SHDN pin input bias current (per pin) VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) - 0.8 V 40 nA VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V- + 0.8 V 150

7.11 Typical Characteristics

Figure 1. Offset Voltage Distribution Histogram Figure 2. Offset Voltage Drift Distribution Histogram Figure 3. Input Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Figure 5. Offset Voltage vs Supply Voltage Figure 6. IB and IOS vs Temperature

V (Ground) /c45 VBIAS2 VBIAS1 Class AB Control Circuitry VO TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TLV900x is a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TLV900x family to be used in virtually any single- supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low- supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Operating Voltage

The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown in the typical characteristics section.

8.3.2 Rail-to-Rail Input

The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region.

8.3.3 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails.

8.3.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV900x family is approximately 850 ns.

8.3.5 Shutdown

The TLV9001S, TLV9002S and TLV9004S devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low. The TLV9001S, TLV9002S and TLV9004S SHDN pins include internal pullup resistors that pull the voltage to V+ (enabling the amplifiers) when the SHDN pins are not connected to a signal. The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit.

TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated Feature Description (continued) The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 10 μs for full shutdown of all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV9002S and TLV9004S to operate as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the TLV9001S, TLV9002S or TLV9004S without a load, the resulting turnoff time significantly increases.

8.4 Device Functional Modes

The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

rails, and allows the TLV900x devices to be used in any single-supply application.

9.2 Typical Application

9.2.1 TLV900x Low-Side, Current Sensing Application

Figure 37 shows the TLV900x configured in a low-side current sensing application. Figure 37. TLV900x in a Low-Side, Current-Sensing Application

9.2.1.1 Design Requirements

• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV

9.2.1.2 Detailed Design Procedure

sizes the resistors RF and RG, to set the gain of the TLV900x to 49 V/V.

9.2.1.3 Application Curve

Figure 38. Low-Side, Current-Sense Transfer Function

9.2.2 Single-Supply Photodiode Amplifier

an example of a single-supply photodiode amplifier circuit using the TLV9002. Figure 39. Single-Supply Photodiode Amplifier Circuit

2 R C

IN PD CM DC C C C 47 pF 5 pF 1 pF 53 pF F F 3dB 1 1 C 10.3 pF 10 pF2 R f 2 309 k 50 kHz |uSu u uSu :u OUT REF F IN V V 3.2 V 0.1 V kVR 310 309 kI 10 A A | : P REFV 0.1 V 0.0303V 3.3 V 1 2 REF 1 2 R R V V R R OUT IN F REFV I R V u TLV9001,TLV9001S,TLV9002,TLV9002S,TLV9004,TLV9004S www.ti.com SBOS833G – OCTOBER 2017– REVISED SEPTEMBER 2018 Product Folder Links: TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated Typical Application (continued)

9.2.2.1 Design Requirements

The design requirements for this design are:

• Supply Voltage: 3.3 V
• Input: 0 µA to 10 µA
• Output: 0.1 V to 3.2 V
• Bandwidth: 50 kHz

9.2.2.2 Detailed Design Procedure

The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF) is defined in Equation 5. (5) Where: (6) Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio calculated in Equation 7. (7) The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω. The required feedback resistance can be calculated based on the input current and desired output voltage. (8) Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using Equation 9. (9) The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the capacitance on the INx– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance, (CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10 shows. (10) The minimum op amp bandwidth is calculated in Equation 11. (11) The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this application configuration.

9.2.2.3 Application Curves

measured performance of the photodiode amplifier circuit is shown in Figure 41. Figure 40. Photodiode Amplifier Circuit AC Gain Results Figure 41. Photodiode Amplifier Circuit DC Results

10 Power Supply Recommendations

variance with regard to operating voltage or temperature. Supply voltages larger than 6 V may permanently damage the device; see the table.

10.1 Input and ESD Protection

protection primarily consists of current-steering diodes connected between the input and power-supply pins. 10 mA. Figure 42 shows how a series input resistor can be added to the driven input to limit the input current. noise-sensitive applications. Figure 42. Input Current Protection

11 Layout

11.1 Layout Guidelines

• Noise can propagate into analog circuitry through the power connections of the board and propagate to the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a low-impedance path to ground. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Figure 44. Keeping RF and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

Figure 43. Schematic Representation for Figure 44 Figure 44. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers

12.2 Related Links

resources, tools and software, and quick access to order now. Table 1. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

www.ti.com 4-Oct-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV9001IDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 PTLV9001IDCKR ACTIVE SC70 DCK 5 3000 TBD Call TI Call TI -40 to 125 PTLV9001IDPWR ACTIVE X2SON DPW 5 3000 TBD Call TI Call TI -40 to 125 PTLV9001SIDBVR ACTIVE SOT-23 DBV 6 3000 TBD Call TI Call TI -40 to 125 PTLV9002SIDGSR ACTIVE VSSOP DGS 10 2500 TBD Call TI Call TI -40 to 125 PTLV9004IDR ACTIVE SOIC D 14 2500 TBD Call TI Call TI -40 to 125 PTLV9004IPWR ACTIVE TSSOP PW 14 2000 TBD Call TI Call TI -40 to 125 PTLV9004IRTER ACTIVE WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 PTLV9004SIRTER ACTIVE WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 TLV9001IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1OGF TLV9001IDCKR PREVIEW SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 1BZ TLV9001IDPWR PREVIEW X2SON DPW 5 3000 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DF TLV9001SIDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1OJF TLV9001UIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 1ODF TLV9002IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TL9002 TLV9002IDSGR ACTIVE WSON DSG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1GMH

www.ti.com 4-Oct-2018 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV9002IDSGT ACTIVE WSON DSG 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1GMH TLV9002IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 9002 TLV9002SIDGSR PREVIEW VSSOP DGS 10 2500 TBD Call TI Call TI -40 to 125 TLV9004IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T9004 TLV9004SIRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T9004S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 4-Oct-2018 Addendum-Page 3 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2018 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV9001IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV9001IDPWR X2SON DPW 5 3000 205.0 200.0 33.0 TLV9001SIDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 TLV9001UIDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TLV9002IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 TLV9002IDGKT VSSOP DGK 8 250 366.0 364.0 50.0 TLV9002IDR SOIC D 8 2500 336.6 336.6 41.3 TLV9002IDSGR WSON DSG 8 3000 210.0 185.0 35.0 TLV9002IDSGT WSON DSG 8 250 210.0 185.0 35.0 TLV9002IPWR TSSOP PW 8 2000 366.0 364.0 50.0 TLV9004IDR SOIC D 14 2500 336.6 336.6 41.3 TLV9004IPWR TSSOP PW 14 2000 366.0 364.0 50.0 TLV9004IRTER WQFN RTE 16 3000 367.0 367.0 35.0 TLV9004SIRTER WQFN RTE 16 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2018 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C SEE OPTIONAL TERMINAL 8X 0.3 0.2 1.6 0.1 1.5 0.9 0.1 6X 0.5 8X 0.4 0.2 0.05 0.00

0.8 MAX

A 2.1 1.9 B 2.1 1.9 0.3 0.2 0.4 0.2 (0.2) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/B 09/2017 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500 OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.25) (1.6) (1.9) 6X (0.5) (0.9) ( 0.2) VIA TYP (0.55) 8X (0.5) (R0.05) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/B 09/2017 SYMM 4 5 LAND PATTERN EXAMPLE SCALE:20X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.25) 8X (0.5) (0.9) (0.7) (1.9) (0.45) 6X (0.5) WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/B 09/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM METAL SYMM

www.ti.com PACKAGE OUTLINE C 4X 0.27 0.17 3X 0.32 0.23

0.4 MAX

0.05 0.002X 0.48 0.27 0.17 0.25 0.1 B 0.85 0.75 A 0.85 0.75 (0.1) (0.06) 4X (0.05) (0.25) 2X (0.26) X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 PIN 1 INDEX AREA SEATING PLANE NOTE 3 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary. NOTE 3 SCALE 12.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

(0.21) TYP EXPOSED METAL CLEARANCE (0.48) (0.78) 4X (0.42) 4X (0.22) ( 0.25) 4X (0.26) 4X (0.06) ( 0.1) VIA (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 SYMM SYMM LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:60X SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK TYP NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com EXAMPLE STENCIL DESIGN (0.48) (0.78) 4X (0.42) 4X (0.22) 4X (0.26) 4X (0.06) ( 0.24) (0.21) TYP (R0.05) TYP X2SON - 0.4 mm max heightDPW0005A PLASTIC SMALL OUTLINE - NO LEAD 4223102/B 09/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD 92% PRINTED SOLDER COVERAGE BY AREA SCALE:100X SYMM SYMM EDGE SOLDER MASK

www.ti.com PACKAGE OUTLINE C TYP0.22 0.08 0.25 3.0 2.6 2X 0.95 1.9

1.45 MAX

TYP0.15 0.00 5X 0.5 0.3 TYP0.6 0.3 TYP8 1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/C 04/2017 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C TYP0.22 0.08 0.25 3.0 2.6 2X 0.95 1.9 TYP0.15 0.00 5X 0.5 0.3 TYP0.6 0.3 TYP8 1.9 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/C 04/2017 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MAX

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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