TLV803EA29DBZR

TLV803E_V02 TI1 | Alldatasheet

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Technical content

FPGA, ASIC, DSP VDD RESET LDO IN OUT *Rpull-up GND *Pull-up resistor not required for TLV809E Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 TLV8xxE,LowPower250-nAIQSupplyVoltageSupervisors

1 Features

1• Ensured RESET output for VDD = 0.7 V to 6 V

• Fixed time delay: 40 µs, 10 ms, 50 ms, 100 ms, 200 ms, 400 ms
• Supply current (IDD): 250 nA (typical) – 1 µA (maximum for VDD = 3.3 V)
• Output topology: – TLV809E: push-pull, active low – TLV803E: open-drain, active low – TLV810E: push-pull, active high
• Under voltage detection: – High accuracy: ±0.5% (typical) – Nominal voltage monitor: 3 V, 3.3 V, 5 V 2.93 V, 3.08 V, 4.38 V, 4.63 V
• Package: – SOT23-3 (DBZ) (with pin 1 = GND) – SOT23-3 (DBZ) (with pin 1 = RESET) – SC-70 (DCK)
• Temperature range: –40°C to +125°C
• Pin-to-pin compatible with MAX803/809/810, APX803/809/810

2 Applications

• Applications using DSPs, microcontrollers, or microprocessors
• Electricity meters
• Portable, battery-powered equipment
• Set-top boxes and TVs
• Building automation
• Notebook/desktop computers, servers

3 Description

The TLV803E, TLV809E, and TLV810E are enhanced alternatives to the TLV803, TLV853, TLV809, LM809, TPS3809 and TLV810. TLV803E, TLV809E and TLV810E offer lower supply current for battery-powered applications, higher accuracy, wider temperature range, and lower power-on-reset (VPOR) for increased system reliability. The TLV80xE and TLV81xE family are low IQ (250 nA typical, 1 µA max), voltage supervisory circuits (reset IC) that monitor VDD voltage level. These devices initiate a reset signal whenever supply voltage VDD drops below the factory programmed falling threshold voltage, VIT–. The reset output remains low for a fixed reset time delay tD after the VDD voltage rises above the rising voltage threshold (VIT+) which is equivalent to the falling threshold voltage (VIT-) plus hysteresis (VHYS). These devices have integrated glitch immunity to ignore fast transients on the VDD pin. The low current consumption and high accuracy (±0.5% typical) makes these voltage supervisors ideal for use in low- power and portable applications. The TLV80xE and TLV81xE devices are specified to have the defined output logic state for supply voltages down to VPOR = 0.7 V. The TLV80xE and TLV81xE devices are available in industry standard 3-pin SOT23 (DBZ) package and 3-pin, SC70 (DCK) package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV803E, TLV809E, TLV810E(2) SOT-23 (3) 2.90 mm × 1.30 mm SC-70 (3) 2.00 mm × 1.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package Typical Application

TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Table of Contents

12.4 Receiving Notification of Documentation Updates 22

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (November 2019) to Revision D Page Changes from Revision B (July 2019) to Revision C Page

5 Device Comparison

Figure 1. Device Naming Nomenclature

TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

6 Pin Configuration and Functions

NAME DCK, DBZ DBZ (Reverse Pinout) GND 1 2 — Ground RESET 2 1 O Active low output reset signal: This pin is driven low logic when VDD voltage falls below the negative voltage threshold (VIT–). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rise above VIT+. RESET 2 1 O Active High output reset signal (TLV810E only): This pin is driven high logic when VDD voltage falls below the negative voltage threshold (VIT–). RESET remains high (asserted) for the delay time period (tD) after VDD voltage rise above VIT+. VDD 3 3 I Input supply voltage. TLV80xE and TLV81xE monitors VDD voltage.

TLV803E, TLV809E, TLV810E www.ti.com SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation FeedbackCopyright © 2018–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions (above the Recommended Operating Conditions) for extended periods may affect device reliability. (2) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller. (3) As a result of the low dissipated power in this device, the junction temperature is assumed to be equal to the ambient temperature.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted(1) MIN MAX UNIT Voltage VDD pin –0.3 6.5 V RESET (TLV809E), RESET(TLV810E) –0.3 VDD + 0.3 (2) V RESET (TLV803E) –0.3 6.5 V Current Output sink and source current -20 20 mA Temperature(3) Operating ambient, TA –40 125 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS- 001(1) ± 2000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ± 500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Input supply voltage 1.7 6 V VRESET, VRESET RESET pin and RESET pin voltage 0 6 V IRESET, IRESET RESET pin and RESET pin current 0 ±5 mA TJ Junction temperature (free air temperature) –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) TLV8XXE UNITDCK (SC70-3) DBZ (SOT23-3)

3 PINS 3 PINS

RθJA Junction-to-ambient thermal resistance 300.5 254.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 178.2 150.5 °C/W RθJB Junction-to-board thermal resistance 166.5 140.1 °C/W ψJT Junction-to-top characterization parameter 70 48.1 °C/W ψJB Junction-to-board characterization parameter 165.2 139.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated (1) VIT+ = VIT- + VHYS (2) Minimum VDD voltage for a controlled output state. Below VPOR, the output cannot be determined. (3) Product Preview

7.5 Electrical Characteristics

over operating range (TA = -40°C to 125°C), 1.7 V < VDD < 6 V, RUP = 10 kΩ to 6 V, 10 pF load at RESET pin, unless otherwise noted. Typical values are at 25°C, VDD = 3.3V and VIT- = 2.93 V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON PARAMETERS VDD Input supply voltage 1.7 6 V VIT- Input threshold voltage accuracy TA= -40 °C to125 °C -2 0.5 2 % VHYS Hysteresis voltage Hysteresis from VIT- 0.9 1.2 1.5 % IDD Supply current into VDD pin VDD=3.3 V; VDD>VIT+ (1) 0.25 1 µA VDD=6 V 0.4 1.2 µA TLV809E (Push-Pull Active-Low) VPOR Power on reset voltage (2) VOL<= 300mV, IOUT (Sink) = 15 µA 700 mV VOL Low level output voltage VDD =1.7V, VDD < VIT-, IOUT (Sink) = 500 µA 300 mV VDD= 3.3V, VDD < VIT-, IOUT (Sink) = 2 mA 300 mV VOH High level output voltage VDD = 6V, VDD > VIT+, IOUT (source) = 4 mA 0.8VDD V VDD= 3.3V, VDD > VIT+, IOUT (source) = 2 mA 0.8VDD V TLV803E (Open-Drain Active-Low) VPOR Power on reset voltage (2) VOL <= 300 mV, IOUT (Sink) = 15 uA 700 mV VOL Low level output voltage VDD = 1.7 V, VDD < VIT-, IOUT = 500 µA 300 mV VDD = 3.3 V, VDD < VIT-, IOUT = 2 mA 300 mV Ilkg(OD) Open drain output leakage current VDD = VPULLUP = 6 V, VDD > VIT+ 100 350 nA TLV810E (Push-Pull Active-High) (3) VOH High level output voltage VDD= 3.3V, VDD < VIT-, IOUT (source) = 2 mA 0.8VDD V VDD = 1.7V, VDD < VIT-, IOUT (source) = 500 uA 0.8VDD V VPOR Power on Reset Voltage VOH >= 720 mV, IOUT (Source) = 15 uA 900 mV VOL Low level output voltage VDD = 6V, VDD > VIT+, IOUT (Sink) = 2 mA 300 mV VDD= 3.3V, VDD > VIT+, IOUT (Sink) = 500 µA 300 mV

TLV803E, TLV809E, TLV810E www.ti.com SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation FeedbackCopyright © 2018–2020, Texas Instruments Incorporated (1) Overdrive = [(VDD/ VIT-) - 1] × 100%. Refer to Section 8.3.3 on VDD glitch immunity. (2) Refer to device nomenclature table in Section 12.1.1. VDD: (VIT--10%) to (VIT+ + 10%) (3) Product Preview (4) Specified by design

7.6 Timing Requirements

over operating range (TA = -40°C to 125°C), 1.7 V < VDD < 6 V, Open-Drain-only: RUP = 10 kΩ to 6 V (Open Drain only), 10 pF load at RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25°C, VDD = 3.3V and VIT- = 2.93. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tGI Glitch immunity 5% Overdrive(1) 10 µs tPD_HL Propagation delay from VDD falling below VIT- to RESET VDD = (VIT+ + 30%) to (VIT- - 10%) 30 50 µs tD Release time or reset timeout period Reset time delay variant A (2) 130 200 270 ms Reset time delay variant B (2) (3); RUP=100 kΩ, CL = 100 pF (4) 45 90 µs Reset time delay variant B (2) (3) 40 80 µs Reset time delay variant C (2) (3) 6.5 10 13.5 ms

7.7 Timing Diagram

Figure 2. TLV803E, TLV809E Timing Diagram Figure 3. TLV810E Timing Diagram

7.8 Typical Characteristics

VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted. Figure 4. Supply Current Versus Supply Voltage for Figure 5. Supply Current Versus Supply Voltage for Figure 6. Supply Current Versus Supply Voltage for Figure 8. Supply Current Over Temperature for Figure 9. Leakage Current Over Temperature for

VDD = 3.3 V, VIT- = 2.93 V, Rpull-up = 10 kΩ to 6 V, CLoad = 50 pF, unless otherwise noted. Figure 28. Glitch Immunity Versus Overdrive for TLV809EA29

RESET (TLV803E, TLV809E) RESET (TLV810E) TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TLV8xxE is a family of easy to implement low power voltage supervisors (Reset ICs) with fixed threshold voltage and fixed reset delay. The TLV803E has open-drain active low output topology which requires a pull-up resistor, TLV809E has push-pull active low output topology and TLV810E has push-pull active high output topology. This family of devices features include integrated resistor divider threshold with hysteresis and a glitch immunity filter. TLV8xxE is available in SOT-23 (3) and SC70 (3) industry standard package and pinout.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Input Voltage (VDD)

VDD pin is monitored by the internal comparator with integrated reference to indicate when VDD falls below the fixed threshold voltage. VDD also functions as the supply for the following:

• Internal bandgap (reference voltage)
• Internal regulator
• State machine
• Buffers
• Other control logic blocks Good design practice involves placing a 0.1-µF to 1-µF bypass capacitor at VDD input for noisy applications and to ensure enough charge is available for the device to power up correctly. The reset output is undefined when VDD is below VPOR.

8.3.2 VDD Hysteresis

The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD pin falls below the falling voltage threshold VIT–, the output reset is asserted. When the voltage at the VDD pin rises above the rising voltage threshold (VIT+) equivalent to VIT– plus hysteresis (VHYS), the output reset is deasserted after TD time delay.

8.3.3 VDD Glitch Immunity

These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on both transient duration and transient overdrive. Overdrive is defined by how much VDD exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1.

• VIT– is the threshold voltage
• VDD is the input voltage crossing VIT– (1)

Figure 29. Overdrive Versus Pulse Duration Requirements. Figure 30 shows that VDD must fall below VIT- for tGI, otherwise the faling transistion is ignored. fault condition only if VDD remains above VIT+ for longer than the reset delay (tD). Figure 30. Glitch Immunity when VDD Rises Above VIT+ for Less than RESET Delay (TLV803EA29)

8.3.4 Output Logic

8.3.4.1 RESET Output, Active Low

negative threshold (VIT–), then reset is asserted and RESET goes to low impedance pulling output low VOL. the reset delay has elapsed, the RESET pin goes back to high impedance and output goes high voltage (VOH). up resistor value is determined by VOL, the output capacitive loading, and the output leakage current (ILKG(OD)). The push-pull variant does not require a pull-up resistor.

TLV803E, TLV809E, TLV810E SLVSES2D –AUGUST 2018–REVISED FEBRUARY 2020 www.ti.com Product Folder Links: TLV803E TLV809E TLV810E Submit Documentation Feedback Copyright © 2018–2020, Texas Instruments Incorporated Feature Description (continued)

8.3.4.2 RESET Output, Active High

RESET remains low (de-asserted) as long as VDD is above the positive threshold (VIT+). If VDD falls below the negative threshold (VIT–), then reset is asserted and RESET goes to logic high VOH. When VDD rise above VIT+, the delay circuit holds RESET high for the specified reset delay period (tD). When the reset delay has elapsed the RESET pin goes back to low logic and output goes to low voltage (VOL). The push-pull variant does not require a pull-up resistor.

8.4 Device Functional Modes

summarizes the various functional modes of the device. VDD RESET (Active High) RESET(Active Low) VDD < VPOR Undefined Undefined VPOR < VDD < VIT– H L VDD ≥ VIT– L H

8.4.1 Normal Operation (VDD > VDD(min))

When VDD voltage is greater than VDD(min), the reset signal is determined by the voltage on the VDD pin with respect to the trip point (VIT–).

8.4.2 VDD Between VPOR and VDD(min)

When the voltage on VDD is less than the VDD(min) voltage and greater than the power-on-reset voltage (VPOR), the reset signal is asserted.

8.4.3 Below Power-On-Reset (VDD < VPOR)

When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the asserted output low or high and reset voltage level is undefined.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

components, if needed, as explained in the following sections.

9.2 Typical Application

supply enters brown-out conditions. Figure 31. The Output of LDO Powering the MCU is Monitored by the TLV803EA29

9.2.1 Design Requirements

up resistor is required because TLV809E has push-pull output topology.

9.2.2 Detailed Design Procedure

logic requirement while not violating the IRESET recommended limit.

9.2.3 Application Curves

high-to-low propagation delay tPD_HL expires, the internal MOSFET turns on and asserts RESET to logic low. high after the reset delay time (tD) expires. Figure 32. Propagation Delay when Fault Occurs after VDD Figure 33. RESET Delay when Returning from Fault after

1. Typical tPD_HL= 30 µs for VDD falling from (VIT+ + 30%) to (VIT- - 10%).
2. VDD does not fall all the way to 0 V so RESET momentarily discharges to VDD until tPD_HL expires.

9.3 Typical Application

variant naming nomenclature. Figure 34. TLV810E Overvoltage Monitor Circuit for Battery Charger

9.3.1 Design Requirements

9.3.2 Detailed Design Procedure

the TLV810E only consumes 250 nA typical.

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

for the open-drain output. Place the pull-up resistor on the RESET pin as close to the pin as possible.

11.2 Layout Example

Figure 35. TLV803E, TLV809E, and TLV810E Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

SOT23-3 pin package, and large reel option. the orderable device information table. Table 1. Device Naming Convention

12.2 Documentation Support

12.2.1 Related Documentation

• Texas Instruments, TLV803EA29EVM User Guide
• Texas Instruments, Voltage Supervisors (Reset ICs): Frequenctly Asked Questions (FAQs)

12.3 Related Links

resources, tools and software, and quick access to order now. Table 2. Related Links

12.4 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.5 Support Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

12.6 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.7 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.8 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 22-Feb-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV803EB29DBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PTLV809EA29DCKR ACTIVE SC70 DCK 3 3000 TBD Call TI Call TI -40 to 125 PTLV809EC26DBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 PTLV810EA29DBZR ACTIVE SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 TLV803EA26DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 326A TLV803EA29DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 329A TLV803EA29DCKR ACTIVE SC70 DCK 3 3000 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -40 to 125 39A TLV803EA29RDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 39AR TLV803EA43RDBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 34AR TLV809EA26DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 926A TLV809EA29DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 929A TLV809EA30DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 930A TLV809EA43DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 943A TLV809EA46DBZR ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 946A TLV810EA29DBZR PREVIEW SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 22-Feb-2020 Addendum-Page 2 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2020 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV803EA26DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV803EA29DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV803EA29DCKR SC70 DCK 3 3000 180.0 180.0 18.0 TLV803EA29RDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV803EA43RDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV809EA26DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV809EA29DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV809EA30DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV809EA43DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 TLV809EA46DBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2020 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP0.20 0.08 0.25 2.64 2.10

1.12 MAX

TYP0.10 0.01 3X 0.5 0.3 TYP0.6 0.2 1.9 0.95 TYP -80 A 3.04 2.80 B1.4 1.2 (0.95) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/C 04/2017 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 2X 0.65

1.1 MAX

0.1

0.0 TYP

5X 0.30 0.15 0.46

0.26 TYP

0 TYP

1.3 A 2.15 1.85 B1.4 1.1 (0.9) SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/A 03/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203.

0.1 C A B

0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.95)5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4220745/A 03/2019 SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95)5X (0.4) (R0.05) TYP SOT-SC70 - 1.1 max heightDCK0003A SMALL OUTLINE TRANSISTOR SC70 4220745/A 03/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG

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