TLV6002IDRG4

TLV6001 TI | Alldatasheet

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Technical content

-50 -25 0 25 50 75 100 125 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) Temperature (oC) C001 PSRR CMRR VCM = ±0.2 V to 5.2 V Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016–REVISED MAY 2017 TLV600xLow-Power,Rail-to-RailIn/Out,1-MHzOperationalAmplifierforCost-Sensitive Systems

1 Features

1• Precision Amplifiers for Cost-Sensitive Systems

• Low Quiescent Current: 75 µA/ch
• Supply Range: 1.8 V to 5.5 V
• Input Voltage Noise Density: 28 nV/√Hz at 1 kHz
• Rail-to-Rail Input and Output
• Gain Bandwidth: 1 MHz
• Low Input Bias Current: 1 pA
• Low Offset Voltage: 0.75 mV
• Unity-Gain Stable
• Internal RF and EMI Filter
• Extended Temperature Range: –40°C to +125°C

2 Applications

• Industrial and Consumer Electronics
• Portable Equipment
• Portable Blood Glucose Systems
• Smoke Detectors
• White Goods
• Power Banks CMRR and PSRR vs Temperature

3 Description

The TLV600x family of single-, dual-, and quad- channel operational amplifiers is specifically designed for general-purpose applications. Featuring rail-to-rail input and output (RRIO) swings, low quiescent current (75 μA, typical), wide bandwidth (1 MHz) and low noise (28 nV/√Hz at 1 kHz), this family is attractive for a variety of applications that require a good balance between cost and performance, such as consumer electronics, smoke detectors, and white goods. The low-input-bias current (±1.0 pA, typical) enables the TLV600x to be used in applications with megaohm source impedances. The robust design of the TLV600x provides ease-of- use to the circuit designer: unity-gain stability with capacitive loads of up to 150 pF, integrated RF/EMI rejection filter, no phase reversal in overdrive conditions, and high electrostatic discharge (ESD) protection (4-kV HBM). The devices are optimized for operation at voltages as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V), and are specified over the extended temperature range of –40°C to +125°C. The single-channel TLV6001 is available in SC70-5 and SOT23-5 packages. The dual-channel TLV6002 is offered in SOIC-8 and VSSOP-8 packages, and the quad-channel TLV6004 is offered in a TSSOP-14 package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV6001 SC70 (5) 2.00 mm × 1.25 mm SOT-23 (5) 2.90 mm × 1.60 mm TLV6002 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm TLV6004 TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents 7.7 Electrical Characteristics: VS= 1.8 V to 5 V (±0.9 V to

12.3 Receiving Notification of Documentation Updates 21

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision C (December 2016) to Revision D Page Changes from Revision B (October 2016) to Revision C Page Changes from Revision A (July 2016) to Revision B Page Changes from Original (June 2016) to Revision A Page

2V± 3+IN 4 ±IN 5 V+ Not to scale 1+IN 2V± 3±IN 4 OUT 5 V+ Not to scale TLV6001,TLV6002,TLV6004 www.ti.com SBOS779D – JUNE 2016– REVISED MAY 2017 Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

5 Device Comparison Table

NO. OF CHANNELS PACKAGE-LEADS SC70 SOT-23 SOIC VSSOP TSSOP TLV6001 1 5 5 — — — TLV6002 2 — — 8 8 — TLV6004 4 — — — — 14

6 Pin Configuration and Functions

TLV6001: DCK Package 5-Pin SC70 Top View TLV6001: DBV Package 5-Pin SOT-23 Top View Pin Functions: TLV6001 PIN I/O DESCRIPTION NAME DCK (SC70) DBV (SOT-23) –IN 3 4 I Inverting input +IN 1 3 I Noninverting input OUT 4 1 O Output V– 2 2 — Negative (lowest) power supply V+ 5 5 — Positive (highest) power supply

2V± 3±IN 4 OUT 5 V+ Not to scale 1OUT 2V+ 3+IN 4 ±IN

5 V ±

TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated TLV6001R: DBV Package 5-Pin SOT-23 Top View Pin Functions: TLV6001R PIN I/O DESCRIPTION NAME NO. –IN 4 I Inverting input +IN 3 I Noninverting input OUT 1 O Output V– 5 — Negative (lowest) power supply V+ 2 — Positive (highest) power supply TLV6001U: DBV Package 5-Pin SOT-23 Top View Pin Functions: TLV6001U PIN I/O DESCRIPTION NAME NO. –IN 3 I Inverting input +IN 1 I Noninverting input OUT 4 O Output V– 2 — Negative (lowest) power supply V+ 5 — Positive (highest) power supply

2±IN A 7 OUT B 3+IN A 6 ±IN B 4V± 5 +IN B Not to scale TLV6001,TLV6002,TLV6004 www.ti.com SBOS779D – JUNE 2016– REVISED MAY 2017 Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated TLV6002: D, DGK Packages 8-Pin SOIC, 8-Pin VSSOP TLV6002 Top View Pin Functions: TLV6002 PIN I/O DESCRIPTION NAME D (SOIC) DGK (VSSOP) –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B V– 4 4 — Negative (lowest) power supply V+ 8 8 — Positive (highest) power supply

2±IN A 13 ±IN D 3+IN A 12 +IN D 4V+ 11 V ± 5+IN B 10 +IN C 6±IN B 9 ±IN C 7OUT B 8 OUT C Not to scale TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated TLV6004: PW Package 14-Pin TSSOP Top View Pin Functions: TLV6004 PIN I/O DESCRIPTION NAME NO. –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B –IN C 9 I Inverting input, channel C –IN D 13 I Inverting input, channel D +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B +IN C 10 I Noninverting input, channel C +IN D 12 I Noninverting input, channel D OUT A 1 O Output, channel A OUT B 7 O Output, channel B OUT C 8 O Output, channel C OUT D 14 O Output, channel D V– 11 — Negative (lowest) power supply V+ 4 — Positive (highest) power supply

TLV6001,TLV6002,TLV6004 www.ti.com SBOS779D – JUNE 2016– REVISED MAY 2017 Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. (3) Short-circuit to ground, one amplifier per package.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply voltage 7 V Signal input pins, voltage(2) (V–) – 0.5 (V+) + 0.5 V Current Signal input pins, current(2) –10 10 mA Output short-circuit(3) Continuous mA Temperature Operating, TA –40 150 °C Junction, TJ 150 °C Storage, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 1.8 5.5 V TA Specified temperature range –40 125 °C

TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TLV6001

THERMAL METRIC(1) TLV6001 UNITDBV (SOT-23) DCK (SC70)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 228.5 281.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 99.1 91.6 °C/W RθJB Junction-to-board thermal resistance 54.6 59.6 °C/W ψJT Junction-to-top characterization parameter 7.7 1.5 °C/W ψJB Junction-to-board characterization parameter 53.8 58.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TLV6002

THERMAL METRIC(1) TLV6002 UNITD (SOIC) DGK (VSSOP)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 138.4 191.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.5 61.9 °C/W RθJB Junction-to-board thermal resistance 78.6 111.9 °C/W ψJT Junction-to-top characterization parameter 29.9 5.1 °C/W ψJB Junction-to-board characterization parameter 78.1 110.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Thermal Information: TLV6004

THERMAL METRIC(1) TLV6004 UNITPW (TSSOP)

14 PINS

RθJA Junction-to-ambient thermal resistance 121.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.4 °C/W RθJB Junction-to-board thermal resistance 62.8 °C/W ψJT Junction-to-top characterization parameter 5.9 °C/W ψJB Junction-to-board characterization parameter 62.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

TLV6001,TLV6002,TLV6004 www.ti.com SBOS779D – JUNE 2016– REVISED MAY 2017 Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Over- temperature limits are based on characterization and statistical analysis. 7.7 Electrical Characteristics: VS= 1.8 V to 5 V (±0.9 V to ±2.75 V)(1) at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage 0.75 4.5 mV dVOS/dT VOS vs temperature TA = –40°C to 125°C 2 μV/°C PSRR Power-supply rejection ratio 86 dB INPUT BIAS CURRENT IB Input bias current TA = 25°C ±1.0 pA IOS Input offset current ±1.0 pA INPUT IMPEDANCE ZID Differential 100 || 1 MΩ || pF ZIC Common-mode 1 || 5 1013Ω || pF INPUT VOLTAGE RANGE VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V CMRR Common-mode rejection ratio VCM = –0.2 V to 5.7 V 60 76 dB OPEN-LOOP GAIN AOL Open-loop voltage gain 0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ 90 110 Phase margin VS = 5.0 V, G = +1 65 degrees OUTPUT VO Voltage output swing from supply rails RL = 100 kΩ 5 mV RL = 2 kΩ 75 100 mV ISC Short-circuit current ±15 mA RO Open-loop output impedance 2300 Ω FREQUENCY RESPONSE GBW Gain-bandwidth product 1 MHz SR Slew rate 0.5 V/µs tS Settling time To 0.1%, VS = 5.0 V, 2-V step , G = +1 5 μs NOISE Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 μVPP en Input voltage noise density f = 1 kHz 28 nV/√Hz in Input current noise density f = 1 kHz 5 fA/√Hz POWER SUPPLY VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V IQ Quiescent current per amplifier IO = 0 mA, VS = 5.0 V 75 100 µA Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs

7.8 Typical Characteristics: Table of Graphs

Table 1. Table of Graphs

7.9 Typical Characteristics

at TA = 25°C, VS = 5 V, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, unless otherwise noted. Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Quiescent Current vs Supply Figure 3. Offset Voltage Production Distribution Figure 4. Offset Voltage vs Common-Mode Voltage Figure 5. CMRR and PSRR vs Frequency Figure 6. 0.1-Hz to 10-Hz Input Voltage Noise

VIN+ VIN– (Ground) VBIAS2 VBIAS1 Class AB Control Circuitry VO Copyright © 2017, Texas Instruments Incorporated TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TLV600x family of operational amplifiers are general-purpose, low-cost devices that are suitable for a wide range of portable applications. Rail-to-rail input and output swings, low quiescent current, and wide dynamic range make the op amps well-suited for driving sampling analog-to-digital converters (ADCs) and other single- supply applications.

8.2 Functional Block Diagram

TLV6001,TLV6002,TLV6004 www.ti.com SBOS779D – JUNE 2016– REVISED MAY 2017 Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Operating Voltage

with supply voltage are illustrated in the Typical Characteristics section.

8.3.2 Rail-to-Rail Input

The input common-mode voltage range of the TLV600x series extends 200 mV beyond the supply rails. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region may vary up to 300 mV with process variation. Thus, the transition region (both stages on) may range from transition region, PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.

8.3.3 Rail-to-Rail Output

Designed as a micro-power, low-noise operational amplifier, the TLV600x delivers a robust output drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability. For resistive loads up to 100 kΩ, the output swings typically to within 5 mV of either supply rail regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the rails, as shown in Figure 11.

8.3.4 Common-Mode Rejection Ratio (CMRR)

CMRR for the TLV600x is specified in several ways so the best match for a given application may be used; see Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when the application requires the use of one of the differential input pairs. Second, the CMRR over the entire common- mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the transition region, as shown in Figure 4.

8.3.5 Capacitive Load and Stability

The TLV600x is designed to be used in applications where driving a capacitive load is required. As with all op amps, there may be specific instances where the TLV600x may become unstable. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or not an amplifier is stable in operation. An op amp in the unity-gain (!~ +1-V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases. When operating in the unity-gain configuration, the TLV600x remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of some capacitors (CL greater than 1 μF) is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.

Figure 19. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. output that reduces the output swing. Figure 19. Improving Capacitive Load Drive

8.3.6 EMI Susceptibility and Input Filtering

for a cutoff frequency of approximately 35 MHz (–3 dB), with a !~ roll-off!~ rolloff of 20 dB per decade. Amplifiers (SBOA128), available for download from www.ti.com.

8.4 Device Functional Modes

8.5 Input and ESD Protection

noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications. Figure 20. Input Current Protection

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

TLV600x to be used in any single-supply application.

9.2 Typical Application

output. In addition, amplification may be added by selecting the input resistor RI and the feedback resistor RF. Figure 21. Application Schematic

9.2.1 Design Requirements

limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must be considered. sufficient to accommodate this application.

9.2.2 Detailed Design Procedure

9.2.3 Application Curve

Figure 22. Inverting Amplifier Input and Output

9.3 System Examples

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. amplifier, as shown in Figure 23. Figure 23. Single-Pole Low-Pass Filter

filter frequency bandwidth. Failure to follow this guideline may result in phase shift of the amplifier. Figure 24. Two-Pole, Low-Pass, Sallen-Key Filter

10 Power Supply Recommendations

regard to operating voltage or temperature. Absolute Maximum Ratings table).

11 Layout

11.1 Layout Guidelines

• Noise may propagate into analog circuitry through the power pins of the circuit and the operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If the traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RF and RG close to the inverting input in order to minimize parasitic capacitance, as shown in Figure 25.
• Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 25. Operational Amplifier Board Layout for Noninverting Configuration Figure 26. Schematic Representation of Figure 25

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• EMI Rejection Ratio of Operational Amplifiers (SBOA128)
• Circuit Board Layout Techniques (SLOA089)

12.2 Related Links

tools and software, and quick access to sample or buy. Table 2. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

TLV6001,TLV6002,TLV6004 SBOS779D – JUNE 2016– REVISED MAY 2017 www.ti.com Product Folder Links: TLV6001 TLV6002 TLV6004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 5-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV6001IDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 14W2 TLV6001IDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14W2 TLV6001IDBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 14W2 TLV6001IDBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14W2 TLV6001IDCKR Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 13X TLV6001IDCKR.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 125 13X TLV6001IDCKT Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 13X TLV6001IDCKT.A Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 125 13X TLV6001RIDBVR NRND Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 16O2 TLV6001RIDBVR.A NRND Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 16O2 TLV6001RIDBVT NRND Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 16O2 TLV6001RIDBVT.A NRND Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 16O2 TLV6001UIDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 16P2 TLV6001UIDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 16P2 TLV6001UIDBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 16P2 TLV6001UIDBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 16P2 TLV6002IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14TV TLV6002IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (TL6002, V6002) TLV6002IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (TL6002, V6002) TLV6002IDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 V6002 TLV6002IDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 V6002 TLV6004IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TLV6004 TLV6004IPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV6004 Addendum-Page 1

www.ti.com 5-Nov-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV6004IPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV6004 TLV6004IPWRG4.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV6004 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV6001, TLV6002 :

• Automotive : TLV6001-Q1 , TLV6002-Q1 NOTE: Qualified Version Definitions: Addendum-Page 2

www.ti.com 5-Nov-2025

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV6001IDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV6001IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV6001IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV6001IDCKR SC70 DCK 5 3000 208.0 191.0 35.0 TLV6001IDCKR SC70 DCK 5 3000 210.0 185.0 35.0 TLV6001IDCKT SC70 DCK 5 250 210.0 185.0 35.0 TLV6001IDCKT SC70 DCK 5 250 208.0 191.0 35.0 TLV6001RIDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV6001RIDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV6001UIDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV6001UIDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV6001UIDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV6002IDGKR VSSOP DGK 8 2500 356.0 356.0 36.0 TLV6002IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 TLV6002IDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 TLV6002IDGKT VSSOP DGK 8 250 353.0 353.0 32.0 TLV6002IDR SOIC D 8 2500 353.0 353.0 32.0 TLV6002IDRG4 SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV6004IPWR TSSOP PW 14 2000 356.0 356.0 35.0 TLV6004IPWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.15 2.4 1.8 2X 0.65 1.3

1.1 MAX

0.1

0.0 TYP

5X 0.33 0.15 NOTE 5

0.1 C A B

0.46

0.26 TYP

0 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C 0.22 0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8 0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

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