TLV5606IDR

TLV5606_16 TI1 | Alldatasheet

Document overview

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Technical content

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 1WWW.TI.COM

features

/C006810-Bit Voltage Output DAC /C0068Programmable Settling Time vs Power Consumption 3 µs in Fast Mode 9 µs in Slow Mode /C0068Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V /C0068Differential Nonlinearity... <0.2 LSB Typ /C0068Compatible With TMS320 and SPI Serial Ports /C0068Power-Down Mode (10 nA) /C0068Buffered High-Impedance Reference Input /C0068Voltage Output Range ... 2 Times the Reference Input Voltage /C0068Monotonic Over Temperature /C0068Available in MSOP Package

applications

/C0068Digital Servo Control Loops /C0068Digital Offset and Gain Adjustment /C0068Industrial Process Control /C0068Machine and Motion Control Devices /C0068Mass Storage Devices

description

The TLV5606 is a 10-bit voltage output digital-to- analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5606 is pro- grammed with a 16-bit serial string containing 4 control and 10 data bits. Developed for a wide range of supply voltages, the TLV5606 can operate from 2.7 V to 5.5 V. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0°C to 70°C. The TLV5606I is characterized for operation from −40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE † (D) MSOP † (DGK) 0°C to 70°C TLV5606CD TLV5606CDGK −40°C to 85°C TLV5606ID TLV5606IDGK † Available in tape and reel as the TLV5606CDR, TLV5606IDR, TLV5606CDGKR, and the TLV5606IDGKR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002−2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 DIN SCLK CS FS VDD OUT REFIN AGND D OR DGK PACKAGE (TOP VIEW)

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 2 WWW.TI.COM functional block diagram Serial Input Register

16 Cycle

I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND 5 Analog ground CS 3 I Chip select. Digital input used to enable and disable inputs, active low. DIN 1 I Serial digital data input FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. OUT 7 O DAC analog output REFIN 6 I Reference analog input voltage SCLK 2 I Serial digital clock input VDD 8 Positive power supply

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 3WWW.TI.COM absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD VDD = 5 V 4.5 5 5.5 V Supply voltage, VDD VDD = 3 V 2.7 3 3.3 V High-level digital input voltage, VIH DV DD = 2.7 V 2 V High-level digital input voltage, VIH DV DD = 5.5 V 2.4 V Low-level digital input voltage, VIL DV DD = 2.7 V 0.6 V Low-level digital input voltage, VIL DV DD = 5.5 V 1 V Reference voltage, Vref to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD −1.5 V Reference voltage, Vref to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD −1.5 V Load resistance, RL 2 10 kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz Operating free-air temperature, TA TLV5606C 0 70 °C Operating free-air temperature, TA TLV5606I −40 85 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 5 V, VREF = 2.048 V, No load, Fast 0.9 1.35 mA IDD Power supply current No load, All inputs = AGND or VDD , DAC latch = 0x800 Slow 0.4 0.6 mA IDD Power supply current VDD = 3 V, VREF = 1.024 V No load, Fast 0.7 1.1 mANo load, All inputs = AGND or VDD , DAC latch = 0x800 Slow 0.3 0.45 mA Power down supply current (see Figure 12) 10 nA PSRR Power supply rejection ratio Zero scale See Note 2 −80 dBPSRR Power supply rejection ratio Full scale See Note 3 −80 dB Power on threshold voltage, POR 2 V NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS (VDD max) − EZS (VDD min))/VDD max] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG (VDD max) − EG (VDD min))/VDD max]

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 4 WWW.TI.COM electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) static DAC specifications RL = 10 kΩ, CL = 100 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 10 10 bits INL Integral nonlinearity See Note 4 ± 0.5 ±1.5 LSB DNL Differential nonlinearity See Note 5 ± 0.2 ± 1 LSB EZS Zero-scale error (offset error at zero scale) See Note 6 ±10 mV Zero-scale-error temperature coefficient See Note 7 10 ppm/°C EG Gain error See Note 8 ±0.6 % of FS voltage Gain-error temperature coefficient See Note 9 10 ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 1023. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 10 to code 1023. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax ) − EZS (Tmin)]/Vref × 106/(Tmax − Tmin). 8. Gain error is the deviation from the ideal output (2Vref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG (Tmax ) − EG (Tmin)]/Vref × 106/(Tmax − Tmin). output specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Voltage output range R L = 10 kΩ 0 AV DD −0.1 V Output load regulation accuracyR L = 2 kΩ, vs 10 kΩ 0.1 ±0.25 % of FS voltage reference input (REF) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage range 0 VDD −1.5 V R I Input resistance 10 M Ω C I Input capacitance 5 pF Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc Slow 525 kHz Reference input bandwidth REFIN = 0.2 V pp + 1.024 V dc Fast 1.3 MHz Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) −75 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level digital input current VI = VDD ±1 µA IIL Low-level digital input current VI = 0 V ±1 µA C I Input capacitance 3 pF

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 5WWW.TI.COM operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ts(FS) Output settling time, full scale R L = 10 kΩ, C L = 100 pF, Fast 3 5.5 sts(FS) Output settling time, full scale R L = 10 kΩ, See Note 11 C L = 100 pF, Slow 9 20 µs ts(CC) Output settling time, code to code R L = 10 kΩ, C L = 100 pF, Fast 1 µs ts(CC) Output settling time, code to code R L = 10 kΩ, See Note 12 C L = 100 pF, Slow 2 µs SR Slew rate R L = 10 kΩ, C L = 100 pF, Fast 3.6 V/ sSR Slew rate R L = 10 kΩ, See Note 13 C L = 100 pF, Slow 0.9 V/µs Glitch energy Code transition from 0x7FF to 0x800 10 nV−s S/N Signal to noise fs = 400 KSPS fout = 1.1 kHz, 62 dB S/(N+D) Signal to noise + distortion fs = 400 KSPS fout = 1.1 kHz, R L = 10 kΩ C L = 100 pF, 60 dB THD Total harmonic distortion R L = 10 kΩ, C L = 100 pF, BW = 20 kHz −61 dB Spurious free dynamic range BW = 20 kHz 68 dB NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS−FS) Setup time, CS low before FS↓ 10 ns tsu(FS−CK) Setup time, FS low before first negative SCLK edge 8 ns tsu(C16−FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16−CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH Pulse duration, SCLK high 25 ns twL Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns twH(FS) Pulse duration, FS high 20 ns

Figure 1. Timing Diagram

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 7WWW.TI.COM TYPICAL CHARACTERISTICS Figure 2 1.998 1.996 1.994 1.990 − Output Voltage − V 2.002 Load Current − mA OUTPUT VOLTAGE vs LOAD CURRENT 2.004

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

1.992 VO VDD = 3 V, Vref = 1 V, Full Scale Figure 3 3.995 3.99 3.985 3.975 4.005 OUTPUT VOLTAGE vs LOAD CURRENT 4.01 3.98 − Output Voltage − V Load Current − mA

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

VDD = 5 V, Vref = 2 V, Full Scale Figure 4 0.1 0.08 0.04 0.16 0.18 OUTPUT VOLTAGE vs LOAD CURRENT 0.2 0.14 0.12 0.06 0.02 − Output Voltage − V Load Current − mA

3 V Slow Mode, SINK

3 V Fast Mode, SINK

VDD = 3 V, Vref = 1 V, Zero Code Figure 5 0.2 0.15 0.1 0.25 0.3 OUTPUT VOLTAGE vs LOAD CURRENT 0.35 0.05 − Output Voltage − V Load Current − mA

5 V Slow Mode, SINK

5 V Fast Mode, SINK

VDD = 5 V, Vref = 2 V, Zero Code

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 11WWW.TI.COM

APPLICATION INFORMATION

The TLV5606 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2R E FCODE 2n [V] where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n−1, where n = 10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which updates the voltage output to the new level. The serial interface of the TLV5606 can be used in two basic modes: /C0068Four wire (with chip select) /C0068Three wire (without chip select) Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5606s connected directly to a TMS320 DSP. TMS320 DSP XF0 XF1 FSX DX CLKX TLV5606 CS FS DIN SCLK TLV5606 CS FS DIN SCLK Figure 15. TMS320 Interface

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 12 WWW.TI.COM serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5606 to a TMS320, SPI, or Microwire port using only three pins. TMS320 DSP FSX DX CLKX TLV5606 FS DIN SCLK CS SPI SS MOSI SCLK TLV5606 FS DIN SCLK CS Microwire I/O SO SK TLV5606 FS DIN SCLK CS Figure 16. Three-Wire Interface on the next positive clock edge following the sixteenth falling clock edge. In power-down mode, all amplifiers within the TLV5606 are disabled.

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 14 WWW.TI.COM ;* Main Program .ps 1000h .entry start: ; disable interrupts setc INTM ; disable maskable interrupts splk #0ffffh, IFR splk #0004h, IMR ; set up the timer to interrupt ever 205uS splk #0000h, 60h splk #00FFh, 61h out 61h, PRD out 60h, TIM splk #0c2fh, 62h out 62h, TCR ; Configure SSP to use internal clock, internal frame sync and burst mode splk #0CC0Eh, 63h out 63h, SSPCR splk #0CC3Eh, 63h out 63h, SSPCR splk #0000h, 64h ; set initial DAC value ; enable interrupts clrc INTM ; enable maskable interrupts ; loop forever! next: idle ;wait for interrupt b next ; all else fails stop here done: b done ;hang there ;* Interrupt Service Routines INT1: ret ;do nothing and return INT23: ret ;do nothing and return TIM_ISR: lacl 64h ; restore counter value to ACC add #4h ; increment DAC value and #0FFCh ; mask 4 MSBs sacl 64h ; store 12 bit counter value or #4000h ; set DAC control bits sacl 65h ; store DAC value out 65h, SDTR ; send data clrc intm ; re-enable interrupts ret .END

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 16 WWW.TI.COM LJMP start ; Execution starts at address 0 on power−up. ; Code in the timer0 interrupt vector CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ; Define program variables RSEG VAR1 rolling_ptr: DS 1 ; Interrupt service routine for timer 0 interrupts RSEG ISR timer0isr: PUSH PSW PUSH ACC CLR T0 ; set CSB low CLR T1 ; set FS low ; The signal to be output on the dac is a sine function. One cycle of a sine wave is ; held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes). The pointer, ; rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on ; each interrupt (at the end of this routine). MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values MOV A,rolling_ptr ; ACC loaded with the pointer into the sine table MOVC A,@A+DPTR ; get msb from the table ORL A, #00H ; set control bits MOV SBUF,A ; send out msb of data word MOVA,rolling_ptr; move rolling pointer in to ACC INC A ; increment ACC holding the rolling pointer MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC MSB_TX: JNB TI, MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb LSB_TX: JNB TI, LSB_TX ; wait for lsb transmit to complete SETB T1 ; set FS = 1 CLR TI ; clear for new transmit MOV A,rolling_ptr ; load ACC with rolling pointer INC A ; increment the ACC twice, to get next sample INC A ANL A,#03FH ; wrap back round to 0 if >64 MOV rolling_ptr,A ; move value held in ACC back to the rolling pointer SETB T0 ; CSB high POP ACC POP PSW RETI ; Set up stack

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 17WWW.TI.COM DS 10h ; 16 Byte Stack! ; Main Program RSEG MAIN start: MOV SP,#STACK−1 ; first set Stack Pointer CLR A MOV SCON,A ; set serial port 0 to mode 0 MOV TMOD,#02H ; set timer 0 to mode 2 − auto−reload MOV TH0,#0C8H ; set TH0 for 16.67 kHs interrupts SETB T1 ; set FS = 1 SETB T0 ; set CSB = 1 SETB ET0 ; enable timer 0 interrupts SETB EA ; enable all interrupts MOV rolling_ptr,A ; set rolling pointer to 0 SETB TR0 ; start timer 0 always: SJMP always ; while(1) ! RET ; Table of 32 sine wave samples used as DAC data RSEG SINTBL sinevals: DW 01000H DW 0903CH DW 05094H DW 0305CH DW 0B084H DW 070C8H DW 0F0E0H DW 0F066H DW 0F038H DW 0F06CH DW 0F0E0H DW 070C8H DW 0B084H DW 0305CH DW 05094H DW 0903CH DW 01000H DW 06020H DW 0A0E8H DW 0C060H DW 040F8H DW 080B4H DW 0009CH DW 00050H DW 00024H DW 00050H DW 0009CH DW 080B4H DW 040F8H DW 0C060H DW 0A0E8H DW 06020H END

/C0084/C0076/C0086/C0053/C0054/C0048/C0054 /C0050/C0046/C0055/C0262/C0086 /C0084/C0079 /C0053/C0046/C0053/C0262/C0086 /C0076/C0079/C0087 /C0080/C0079/C0087/C0069/C0082 /C0049/C0048/C0262/C0066/C0073/C0084 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0080/C0079/C0087/C0069/C0082 /C0068/C0079/C0087/C0078 SLAS259B − DECEMBER 1999 − REVISED APRIL 2004 19WWW.TI.COM definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS ) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG ) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TLV5606CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 5606C TLV5606CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 5606C TLV5606CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGX TLV5606CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGX TLV5606CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGX TLV5606CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM 0 to 70 AGX TLV5606CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 5606C TLV5606CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 5606C TLV5606ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5606I TLV5606IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5606I TLV5606IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AGY TLV5606IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AGY TLV5606IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AGY TLV5606IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AGY TLV5606IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5606I TLV5606IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 5606I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.

www.ti.com 11-Apr-2013 Addendum-Page 2 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5606CDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 TLV5606CDR SOIC D 8 2500 367.0 367.0 38.0 TLV5606IDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 TLV5606IDR SOIC D 8 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2

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