TLV5580IPWR

TLV5580_15 TI1 | Alldatasheet

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/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com /C00688-Bit Resolution 80 MSPS Sampling Analog-to-Digital Converter (ADC) /C0068Low Power Consumption: 165 mW Typ Using External references /C0068Wide Analog Input Bandwidth: 700 MHz Typ /C00683.3 V Single-Supply Operation /C00683.3 V TTL/CMOS-Compatible Digital I/O /C0068Internal Bottom and Top Reference Voltages /C0068Adjustable Reference Input Range /C0068Power Down (Standby) Mode /C0068Separate Power Down for Internal Voltage References /C0068Three-State Outputs /C006828-Pin Small Outline IC (SOIC) and Thin Shrink SOP (TSSOP) Packages /C0068Applications − Digital Communications − Flat Panel Displays − High-Speed DSP Front-End (TMS320C6000) − Medical Imaging − Graphics Processing (Scan Rate/Format Conversion) − DVD Read Channel Digitization

DESCRIPTION

The TLV5580 is an 8-bit 80 MSPS high-speed A/D converter. It converts the analog input signal into 8-bit binary-coded digital words up to a sampling rate of 80 MHz. All digital inputs and outputs are 3.3 V TTL/CMOS-compatible. The device consumes very little power due to the

3.3 V supply and an innovative single-pipeline

architecture implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage references from user-supplied voltages. If no external references are available, on-chip references are available for internal and external use. The full-scale range is 1 Vpp up to 1.6 Vpp, depending on the analog supply voltage. If external references are available, the internal references can be disabled independently from the rest of the chip, resulting in an even greater power saving. While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD read channel digitization, medical imaging and communications. This device is suitable for IF sampling of communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. DRV DD DRV SS DV SS CLK OE DV DD AV SS AV DD AIN CML PWDN_REF AV SS REFBO REFBI REFTI REFTO AV SS BG AV DD STBY DW OR PW PACKAGE (TOP VIEW) Copyright  1999−2003, Texas Instruments Incorporated www.ti.com

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com FUNCTIONAL BLOCK DIAGRAM SHA DACADC − ADC Correction Logic Output Buffers 22 2 2 2 D0(LSB)−D7(MSB) SHA SHA SHA SHA SHA The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction logic ensures no missing codes over the full operating temperature range. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLV5580 SOIC, 28 DW 0°C to +70°C TLV5580C TLV5580CDW Rails, 20 ″ ″ ″ ″ ″ TLV5580CDWR Tape and Reel, 1000 TLV5580 TSSOP . 28 PW 0°C to +70°C TV5580 TLV5580CPW Rails, 20 ″ ″ ″ ″ ″ TLV5580CPWR Tape and Reel, 2000 TLV5580 SOIC, 28 DW −40°C to +85°C TLV5580I TLV5580IDW Rails, 50 ″ ″ ″ ″ ″ TLV5580IDWR Tape and Reel, 1000 TLV5580 TSSOP , 28 PW −40°C to +85°C TY5580 TLV5580IPW Rails, 50 ″ ″ ″ ″ ″ TLV5580IPWR Tape and Reel, 2000 (1)For the most current specifications and package information, refer to our web site at www .ti.com.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com CIRCUIT DIAGRAMS OF INPUTS AND OUTPUTS DV DD AV DD AV DD 0.5 pF Internal Reference Generator REFTO or REFBO AV DD REFBI or REFTI OE ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT REFERENCE INPUT CIRCUIT D0−D7 OUTPUT CIRCUIT DRV DD DRV SS D_Out D

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AIN 26 I Analog input AV DD 16, 27 I Analog supply voltage AV SS 18, 23, 28 I Analog ground BG 17 O Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be connected between this terminal and AVSS for external filtering. CLK 12 I Clock input. The input is sampled on each rising edge of CLK. CML 25 O Common mode level. This voltage is equal to (AVDD − AVSS ) ÷ 2. An external 0.1 µF capacitor should be connected between this terminal and AVSS . D0 − D7 2 − 9 O Data outputs. D7 is the MSB DRV DD 1 I Supply voltage for digital output drivers DRV SS 10 I Ground for digital output drivers DV DD 14 I Digital supply voltage OE 13 I Output enable. When high the D0 − D7 outputs go in high-impedance mode. DV SS 11 I Digital ground PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal will disable the internal reference circuit. REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering should be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AVSS is recommended. Additionally , a 0.1 µF capacitor can be connected between REFTI and REFBI. REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AVSS will provide sufficient decoupling required for this output. REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC. It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be applied to this input. The use of a 0.1 µF capacitor between REFTI and AVSS is recommended. Additionally, a 0.1 µF capacitor can be connected between REFTI and REFBI. REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be connected to REFTI or left unconnected. A 1 µF capacitor between REFTO and AVSS will provide sufficient decoupling required for this output. STBY 15 I Standby input. A high level on this input enables a power-down mode.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (unless otherwise noted)† Reference voltage input range to AGND: V(REFTI), V(REFTO), V(REFBI), V(REFBO) −0.5 V to AVDD + 0.5 V (1) †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS OVER OPERATING FREE-TEMPERATURE RANGE POWER SUPPLY MIN NOM MAX UNIT AV DD Supply voltage DV DD 3 3.3 3.6 VSupply voltage DRV DD 3 3.3 3.6 V ANALOG AND REFERENCE INPUTS MIN NOM MAX UNIT Reference input voltage (top), V(REFTI) (NOM) − 0.2 2 + (AVDD − 3) (NOM) + 0.2 V Reference input voltage (bottom), V(REFBI) 0.8 1 1.2 V Reference voltage differential, V(REFTI) − V(REFBI) 1 + (AVDD − 3) V Analog input voltage, V(AIN) V(REFBI) V(REFTI) V DIGITAL INPUTS MIN NOM MAX UNIT High-level input voltage, VIH 2.0 DV DD V Low-level input voltage, VIL DGND 0.2xDVDD V Clock period, tc 12.5 ns Pulse duration, clock high, tw(CLKH) 5.25 ns Pulse duration, clock low, tw(CLKL) 5.25 ns

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH F CLK = 80 MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) POWER SUPPLY PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AV DD AV DD = DVDD = 3.3 V, DRVDD = 3 V, 57 71 IDD Operating supply currentDV DD AV DD = DVDD = 3.3 V, DRVDD = 3 V, C L = 15 pF, VI = 1 MHz, −1 dBFS 3 3.6 mAIDD Operating supply current DRV DD C L = 15 pF, VI = 1 MHz, −1 dBFS 5 7.5 mA PD Power dissipation PWDN_REF = L 213 270 PD Power dissipation PWDN_REF = H 165 210 mW PD(STBY) Standby power STBY = H, CLK held high or low 11 15 mW DIGITAL LOGIC INPUTS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level input current on CLK† AV DD = DVDD = DRVDD = CLK = 3.6 V 10 µA IIL Low-level input current on digital inputs (OE, STDBY, PWDN_REF, CLK) AV DD = DVDD = DRVDD = 3.6 V, Digital inputs at 0 V 10 µA C I Input capacitance 5 pF † IIH leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of 4 KΩ to DGND. LOGIC OUTPUTS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage AV DD = DVDD = DRVDD = 3 V at IOH = 50 µA, Digital output forced high 2.8 V VOL Low-level output voltage AV DD = DVDD = DRVDD = 3.6 V at IOL = 50 µA, Digital output forced low 0.1 V C O Output capacitance 5 pF IOZH High-impedance state output current to high level AV DD = DVDD = DRVDD = 3.6 V 10 µA IOZL High-impedance state output current to low level AV DD = DVDD = DRVDD = 3.6 V 10 µA

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH F CLK = 80 MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) DC ACCURACY PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Integral nonlinearity (INL), best-fitInternal references (see Note 1) TA = −40°C to 85°C −2.4 ±1 2.4 LSBIntegral nonlinearity (INL), best-fitInternal references (see Note 1) TA = −40°C to 85°C −2.4 ±1 2.4 LSB Differential nonlinearity (DNL)Internal references (see Note 2) TA = −40°C to 85°C −1 ±0.6 1.3 LSB Zero error AV DD = DVDD = 3.3 V, DRVDD = 3 V See Note 3 5 %FS Full scale error AV DD = DVDD = 3.3 V, DRVDD = 3 V See Note 3 5 %FS 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full−scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two endpoints. 2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition level − first transition level) ÷ (2n − 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than −1 LSB ensures no missing codes. 3. Zero error is defined as the difference in analog input voltage − between the ideal voltage and the actual voltage − that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256). ANALOG INPUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C I Input capacitance 4 pF REFERENCE INPUT (AV DD = DVDD = DRVDD = 3.6 V) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R ref Reference input resistance 200 Ω Iref Reference input current 5 mA REFERENCE OUTPUTS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(REFTO) Reference top offset voltage Absolute min/max values valid2.07 2 + [(AVDD − 3) ÷ 2] 2.21 V V(REFBO) Reference bottom offset voltage Absolute min/max values valid and tested for AVDD = 3.3 V 1.09 1 + [(AVDD − 3) ÷ 2] 1.21 V

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH F CLK = 80 MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted) (continued) DYNAMIC PERFORMANCE † PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fin = 1 MHz 6.2 6.7 Effective number of bits, ENOB fin = 4.43 MHz 6.2 6.7 BitsEffective number of bits, ENOB fin = 15 MHz 6.4 Bits fin = 76 MHz 6.5 fin = 1 MHz 39 42 Signal-to-total harmonic distortion + noise, S/(THD+N) fin = 4.43 MHz 39 42 dBSignal-to-total harmonic distortion + noise, S/(THD+N)fin = 15 MHz 40 dB fin = 76 MHz 40 fin = 1 MHz −46 −50 Total harmonic distortion (THD) fin = 4.43 MHz −45.5 −49 dBTotal harmonic distortion (THD) fin = 15 MHz −44 dB fin = 76 MHz −45.5 fin = 1 MHz 48 51 Spurious free dynamic range (SFDR) fin = 4.43 MHz 48 51 dBSpurious free dynamic range (SFDR) fin = 15 MHz 46 dB fin = 76 MHz 48 Analog input full-power bandwidth, BW See Note 4 700 MHz Differential phase, DP fclk = 40 MHz, fin = 4.43 MHz, 0.8 °Differential phase, DP fclk = 40 MHz, fin = 4.43 MHz, 20 IRE amplitude vs. full-scale of 140 IRE 0.8 ° Differential gain, DG fclk = 40 MHz, fin = 4.43 MHz, 20 IRE amplitude vs. full-scale of 140 IRE 0.6 %Differential gain, DG 20 IRE amplitude vs. full-scale of 140 IRE 0.6 % † Based on analog input voltage of −1 dBFS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at fclk = 80 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3.0 V at 25°C. 4. The analog input bandwidth is defined as the maximum frequency of a −1 dBFS input sine that can be applied to the device for which an extra 3 dB attenuation is observed in the reconstructed output signal.

1. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital output load

is load is not less than 2 pF. Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant. The OE signal is asynchronous. output load is not higher than 10 pF.

1. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available from the

Figure 1. Timing Diagram

80 MSPS

40 MSPS

60 MSPS

Figure 4. S/(THD+N) vs VIN At 80 MSPS (Internal Reference),

60 MSPS (External Reference), 40 MSPS (External Reference)

Figure 5. Spectral Plot fIN = 1.011 MHz At 60 MSPS

and input range can be modified to suit the application. word. All digital logic operates at the rising edge of CLK. Figure 12. Simplified Equivalent Input Circuit capacitor requires no input current and the equivalent input impedance is very high. So, for applications running at a lower fCLK , the total source resistance can increase proportionally.

module for an example circuit. also have limits on their useful range. These limits are also dependent on AVDD . Table 3 summarizes these limits for 3 cases. Table 1. Recommended Operating Modes references when left unconnected. have changes in the LSB of the ADC output due to the total aperture error.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com PRINCIPLE OF OPERATION DIGITAL OUTPUTS The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading causes higher dynamic output currents and can increase noise coupling into the device’s analog front end. To drive higher loads, use an output buffer is recommended. When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the specification section for more details. LAYOUT, DECOUPLING AND GROUNDING RULES It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated performance. Separate analog and digital ground planes that are spliced underneath the device are advisable. TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier. Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB. Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised. As for power supplies, separate analog and digital supply terminals are provided on the device (AV DD /DVDD ). The supply to the digital output drivers is kept separate also (DRVDD ). Lowering the voltage on this supply from the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output buffers. Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the TLV5580 EVM is recommended.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com TLV5580 EVALUATION MODULE TLV5580 EVALUATION MODULE TI provides an evaluation module (EVM) for TLV5580. The EVM also includes a 10-bit 80 MSPS DAC so that the user can convert the digitized signal back to the analog domain for functional testing. Performance measurements can be done by capturing the ADC’s output data. The EVM provides the following additional features: /C0068Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock input. /C0068Use of TLV5580 internal or external voltage references. In the case of external references, an onboard circuit is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two potentiometers allow for the independent adjustments of both references. The full scale ADC range can be adjusted to the input signal amplitude. /C0068All digital output, control signal I/O (output enable, standby, reference power-down) and clock I/O are provided on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping. /C0068Onboard prototyping area with analog and digital supply and ground connections. Figure 15 shows the EVM schematic. The EVM is factory shipped for use in the following configuration: /C0068Use of external (onboard) voltage references /C0068External clock input ANALOG INPUT A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector J10. This signal is onboard terminated with 50Ω. There is no onboard biasing of the signal. When using external (onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device is specified depends on AV DD and is shown under the Recommended Operating Conditions. Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics section. CLOCK INPUT A clock signal should be applied with amplitudes ranging from 0 to AVDD with a frequency equal to the desired sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC series of programmable high-frequency crystal oscillators. Refer to the TLV5580 EVM Settings for selecting between the different clock modes.

caused by the output drivers. Table 2. Power Supplies internal references are used and no D/A conversion is required. to power down the internal voltage references by asserting PWN_REF when onboard references are used. The references are measured at test points TP3 (V(REFB)) and TP4 (V(REFT)). capturing the ADC output data available on connector J11 and not by evaluating the DAC output.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com TLV5580 EVALUATION MODULE TLV5580 EVM SETTINGS CLOCK INPUT SETTINGS REFERENCE DESIGNATOR FUNCTION W1 Clock selection switch 1−2 J11: clock from pin1 on J11 connector 2−3 J9: clock from J9 SMA connector W2 Clock source switch /C0074XTL: clock from onboard crystal oscillator /C0106CLK: clock from pin 1 on J11 connector (if W1/1−2) or J9 SMA connector (if W1/2−3) NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1 setting. W3 Clock output switch 1−2 Rising: clock output on J11 connector is the same phase as the clock to the digital output buffer. Data changes on rising CLK edge. 2−3 Falling: clock output on J11 connector is the opposite phase as the digital output buffer. Data changes on falling CLK edge. REFERENCE SETTINGS REFERENCE DESIGNATOR FUNCTION SW1 REFT external/internal switch /C0074/C0106REFT internal: REFT from TLV5580 internal reference /C0106/C0074REFT external: REFT from onboard voltage reference circuit SW2 REFB external/internal switch /C0074/C0106REFB internal: REFB from TLV5580 internal reference /C0106/C0074REFB external: REFB from onboard voltage reference circuit CONTROL SETTINGS REFERENCE DESIGNATOR FUNCTION W4 TLV5580 and digital output buffer output enable control (1) /C00745580-574 OE-connected:Connects OEs of TLV5580 and digital output buffer (574 buffer). Use this when no board-external OE is used. In addition, close W5 to have both OEs permanently enabled. /C01065580-574 OE-disconnected:Disconnects OEs of TLV5580 and digital output buffer (574 buffer). The OE for the output buffer needs to be pulled low from pin 5 on J11 connector to enable. The OE for TLV5580 is independently controlled from pin 7 on J11 connector (W5 open) or is permanently enabled if W5 is closed. W5 TLV5580 and digital output buffer output enable control (2) /C00745580 OE to GND: Connects OEs of TLV5580 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5580-574 OE -connected. /C01065580 OE external: Enables control of OE of TLV5580 via pin 7 on J11 connector. When taken high (internal pulldown) the output can be disabled. W6 TLV5580 STDBY control /C0074Stdby:STDBY is active (high). /C0106Active: STDBY is low, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby mode.

/C0084/C0076/C0086/C0053/C0053/C0056/C0048 /C0056/C0262/C0066/C0073/C0084 /C0044 /C0056/C0048 /C0077/C0083/C0080/C0083 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0065/C0047/C0068 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003 www.ti.com TLV5580 EVALUATION MODULE CONTROL SETTINGS (Continued) REFERENCE DESIGNATOR FUNCTION W7 TLV5580 PWDN REF control /C0074Pwdn_ref:PWDN_REF is active (high). /C0106Active:PWDN_REF is low, via internal pulldown. PWDN_REF can be taken high from pin 10 on J11 connector to enable pwdn_ref mode. W8 DAC enable /C0074Active:D/A on /C0106Standby:D/A off

11 R13

8 R17

1 DRVDD AVSS

Figure 15. EVM Schematic

Figure 15. EVM Schematic (Continued)

Table 3. TLV5580EVM Bill of Material

7 C1, C11, C13, C3, C5, C7, C9 1 µF 1206 ceramic multi-layer capacitorAny

18 C10, C12, C14, C15, C16, C17,

19 C24, C25, C26, C27, C28, C29,

7 J1, J2, J3, J4, J5, J6, J7 Screw Con 2 terminal screw connector Lumberg

3 J10, J8, J9 SMA PCM mount, SMA Jack Johnson Components

1 R2 0 1206 Chip resistor Any

2 R26, R27 10 1206 Chip resistor Any

12 R1, R11, R14, R40, R41, R42,

10 K 1206 Chip resistor Any

6 R10, R12, R15, R16, R8, R9 1 K 1206 Chip resistor Any

20 R13, R17, R18, R19, R20, R21,

1 R3 200 1206 Chip resistor Any

1 R6 5 K 4 mm SM pot-top adjust Bourns

1 R7 1 K 4 mm SM pot-top adjust Bourns

2 SW1, SW2 SPDT C&K tiny series−slide switchC&K

1 U3 CXD2306Q Sony

1 U2 SN74ALVC00D 14-SOIC (D) Quad 2-input positive NAND Texas Instruments

1 U5 SN74LVT574DW 20-SOP (DW) Texas Instruments

† Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.

Table 3. TLV5580EVM Bill of Material (Continued)

1 U4 TLE2144CDW 16-SOP(D) Quad op amp Texas Instruments

1 U6 TLV5580PW 28-TSSOP (PW) Texas Instruments

1 U1 TPS7133 8-SOP(D) Low-dropout voltage regulatorTexas Instruments

1 X1 NA Crystal oscillator Epson

† Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.

www.ti.com 2-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV5580CDW NRND SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5580C TLV5580CPW NRND TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TV5580 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 2-Oct-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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