TLV4021R2YKAR

TLV4021_19 TI1 | Alldatasheet

Document overview

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Technical content

1 Features

• Adjustable thresholds down to 0.2 V and 1.2 V
• Fixed threshold of 3.2 V
• High threshold accuracy – 0.5% at 25°C – 1% over temperature
• Low quiescent current: 2 µA
• Propagation delay: 360 ns
• Push-pull and open-drain output options
• Known startup conditions
• Non-inverting and inverting input options
• Precision hysteresis
• Temperature range: –40°C to +125°C
• Packages: – 0.73 mm × 0.73 mm DSBGA (4-bump)

2 Applications

• Self-diagnostics
• Lithium ion battery monitoring
• Battery management and protection
• Current and voltage sensing
• Analog front end
• Power management
• Non-isolated power supply
• Point of load regulators
• DC/DC power supply
• AC/DC power supply
• System control and monitoring

3 Description

signals must be converted into clean digital outputs. TLV4031 and TLV4051 have an inverting input. Figure 1. Continuous Table 1. TLV40x1 Family of Internal Reference

TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04A –MARCH 2019–REVISED MAY 2019 www.ti.com Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 24

12 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (October 2018) to Revision A Page

A B Top View TLV4021, TLV4031, TLV4041, TLV4051 www.ti.com SNVSB04A –MARCH 2019–REVISED MAY 2019 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

OUT A1 O Comparator output: OUT is push-pull on TLV4041/4051 and open-drain on TLV4021/4031 V+ B1 P Positive (highest) power supply V– B2 P Negative (lowest) power supply IN A2 I Comparator input: IN is non-Inverting on TLV4021/4041 and inverting on TLV4031/4051

TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04A –MARCH 2019–REVISED MAY 2019 www.ti.com Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or less. In addition, IN can be greater than (V+) and OUT as long as it is within the –0.3 V to 6 V range. Input signals that can swing beyond this range must be current-limited to 10 mA or less. (3) Short-circuit to ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) –0.3 6 V Input voltage (IN) from (V–) (2) –0.3 6 V Input Current (IN)(2) ±10 mA Output voltage (OUT) from (V-) TLV4021, TLV4031 –0.3 6 V TLV4041, TLV4051 –0.3 (V+) + 0.3 V Output short-circuit duration(3) 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) 1.6 5.5 V Ambient temperature, TA –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC (1) TLV40x1 UNITYKA (DSBGA)

4 BUMPS

RθJA Junction-to-ambient thermal resistance 205.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 1.8 °C/W RθJB Junction-to-board thermal resistance 75.3 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 74.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

TLV4021, TLV4031, TLV4041, TLV4051 www.ti.com SNVSB04A –MARCH 2019–REVISED MAY 2019 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) See Section 7.4.3 (Switching Thresholds and Hysteresis) for more details. (2) See Section 7.4.1 (Power ON Reset) for more details.

6.5 Electrical Characteristics

VS = 1.8 V to 5 V, typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1R2 0.197 0.2 0.203 V Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 0.196 0.204 VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 0.177 0.18 0.183 Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40°C to +125°C 0.176 0.184 VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1R1 1.194 1.2 1.206 V Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 1.188 1.212 VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 1.174 1.18 1.186 Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40°C to +125°C 1.168 1.192 VHYS (1) Input hysteresis voltage VS = 1.8 V and 5 V, TA = 25℃ TLV40x1Ry 20 mV VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV4021S5 3.238 3.254 3.270 Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 3.221 3.287 VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 3.184 3.2 3.216 Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 3.168 3.232 VHYS (1) Input hysteresis voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1S5 54 mV VIN Input voltage range TA = -40℃ to +125℃ V– 5.5 V IBIAS Input bias current Over VIN range 10 pA IBIAS Input bias current (TLV4021S5 only) IN = 3.3 V 1.65 µA VOL Voltage output swing from (V–) ISINK = 200 µA, OUT asserted low, VS = 5 V, TA = –40°C to +125°C 100 mV ISINK = 3 mA, OUT asserted low, VS = 5 V, TA = –40°C to +125°C 400 mV VOH Voltage output swing from (V+) (TLV4041/4051 only) ISOURCE = 200 µA, OUT asserted high, VS = 5 V, TA = –40°C to +125°C 100 mV ISOURCE = 3 mA, OUT asserted high, VS = 5 V, TA = –40°C to +125°C 400 mV IO-LKG Open-drain output leakage current (TLV4021/4031 only) VS = 5 V, OUT asserted high VPULLUP = (V+), TA = 25°C 20 pA ISC Short-circuit current VS = 5 V, sinking, TA = 25°C 55 mA ISC Short-circuit current VS = 5 V, sourcing, TA = 25°C (TLV4041/4051 only) 50 mA IQ Quiescent current No load, TA = 25°C, Output Low, VS = 1.8 V 2 3.5 µA No load, TA = –40°C to +125°C, Output Low, VS = 1.8 V 5 µA VPOR (2) Power-on reset voltage 1.45 V

(1) High-to-low and low-to-high refers to the transition at the input. output is controlled by the POR circuit.

6.6 Switching Characteristics

TLV4021S5, RP=4.99 kΩ for open-drain options (unless otherwise noted). Figure 2. Timing Diagram Non-Inverting Input

6.7 Typical Characteristics

Figure 3. Positive Threshold vs Temperature Figure 4. Positive Threshold Histogram Figure 5. Negative Threshold vs Temperature Figure 6. Negative Threshold Histogram Figure 7. Hysteresis vs Temperature Figure 8. Hysteresis Histogram

Figure 33. Propagation Delay High-Low vs Input Overdrive

7 Detailed Description

7.1 Overview

conscious systems to monitor and respond quickly to fault conditions. any voltage above the internal reference voltage, an external resistor divider network is required. higher than the internal reference voltage of 1.2V without any external components. Table 2. TLV40x1 Truth Table

0.2V t IN OUT 0.2V t IN OUT 1.2V t VPU IN OUT 1.2V t VPU TLV4021R2 TLV4021R1 TLV4041R2 TLV4041R1 IN OUT 0.2V t IN OUT 0.2V t IN OUT 1.2V t VPU IN OUT 1.2V t VPU TLV4031R2 TLV4031R1 TLV4051R2 TLV4051R1 IN V+ 1.2V t VPU TLV4021S5 TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04A –MARCH 2019–REVISED MAY 2019 www.ti.com Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Description

configurations as well as non-inverting and inverting inputs.

7.4 Device Functional Modes

7.4.1 Power ON Reset (POR)

connected to (V+). Note how the output goes high when VS reaches 1.45V. Figure 34. TLV4021/4031 Output for VS Rising Figure 35. TLV4021/4031 Output for VS Falling Figure 36. TLV4041/4051 Output for VS Rising Figure 37. TLV4041/4051 Output for VS Falling

7.4.2 Input (IN)

the Electrical Characteristics Table, the TLV40x1 is equally suited for undervoltage and overvoltage detection.

extremely noisy applications, place a 1 nF to 100 nF bypass capacitor at the comparator input. series resistor is recommended to limit the input current when sources have signal content that is less than (V-).

7.4.3 Switching Thresholds and Hysteresis (VHYS)

The TLV40x1 transfer curve is shown in Figure 38.

• VIT+ represents the positive-going input threshold that causes the comparator output to change from a logic low state to a logic high state.
• VIT- represents the negative-going input threshold that causes the comparator output to change from a logic high state to a logic low state.
• VHYS represents the difference between VIT+ and VIT- and is 20 mV for TLV40x1Ry and 54 mV for TLV4021S5.

Figure 38. Transfer Curve example, if VIT+ has a positive 0.5% error, VIT- would have a tendency to have a similar positive percentage error. and the lowest VIT- value of its range.

Figure 39. VHYST Histogram (TLV40x1R2, VS=5V) Figure 40. VHYST Histogram (TLV40x1R1, VS=5V) Figure 41. VHYST Histogram (TLV40x1S5, VS=5V)

7.4.4 Output (OUT)

independent of the supply voltage. utilized in order to eliminate the need for the pull-up resistor.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

family are well suited for monitoring voltages and currents in portable, battery powered devices.

8.1.1 Monitoring (V+)

is simply connected to the (V+) rail. Figure 42. Supply Monitoring

8.1.2 Monitoring a Voltage Other than (V+)

resistor divider used to set the desired threshold is connected to the rail that is being monitored. Figure 43. Monitoring a Voltage Other than the Supply network. Likewise, the TLV40x1 can monitor voltages as low as the internal reference voltage (0.2 V or 1.2 V). and minimum sensing voltage.

8.1.3 VPULLUP to a Voltage Other than (V+)

Figure 44. Level-Shifting

8.2 Typical Application

8.2.1 Under-Voltage Detection

the TLV4051 option with an inverting input stage would be utilized. Figure 45. Under-Voltage Detection

8.2.1.1 Design Requirements

• Operate from 3.3 V power supply that powers the microcontroller.
• Under-voltage alert is active low.
• Logic low output when VBAT is less than 2.0V.

8.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 45. Connect (V+) to 3.3 V which also powers the micro-controller. comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal. minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy. Equation 1 is derived from the analysis of Figure 45.

• R1 and R2 are the resistor values for the resistor divider connected to IN
• VBAT is the voltage source that is being monitored for an undervoltage condition.
• VIT- is the falling edge threshold where the comparator output changes state from high to low Rearranging Equation 1 and solving for R1 yields Equation 2.

For the specific undervoltage detection of 2.0 V using the TLV4041R1, the following results are calculated.

• R2 is set to 1 MΩ
• VBAT is set to 2.0 V
• VIT- is set to1.18 V Choose RTOTAL (R1 + R2) such that the current through the divider is at least 100 times higher than the input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.

8.2.1.3 Application Curve

Figure 46. Under-Voltage Detection

8.2.2 Additional Application Information

8.2.2.1 Pull-up Resistor Selection

requirement of the logic device that is being driven by the comparator when calculating the maximum RPU value. from the logic device being driven to determine RPU maximum using Equation 4.

TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04A –MARCH 2019–REVISED MAY 2019 www.ti.com Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Application (continued) Next, determine the minimum value for RPU by using the VIL maximum from the logic device being driven. In order for the comparator output to be recognized as a logic low, VIL maximum is used to determine the upper boundary of the comparator's VOL. VOL maximum for the comparator is available in the EC Table for specific sink current levels and can also be found from the VOUT versus ISINK curve in the Typical Application curves. A good design practice is to choose a value for VOL maximum that is 1/2 the value of VIL maximum for the input logic device. The corresponding sink current and VOL maximum value will be needed to calculate the minimum RPU. This method will ensure enough noise margin for the logic low level. With VOL maximum determined and the corresponding ISINK obtained, the minimum RPU value is calculated with Equation 5. (5) Since the range of possible RPU values is large, a value between 5 kΩ and 100 kΩ is generally recommended. A smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value consumes less power when in a logic low output state.

8.2.2.2 Input Supply Capacitor

Although an input capacitor is not required for stability, for good analog design practice, connect a 100 nF low equivalent series resistance (ESR) capacitor from (V+) to (V-).

8.2.2.3 Sense Capacitor

Although not required in most cases, for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor from the comparator input (IN) to the (V-) for good analog design practice. This capacitor placement reduces device sensitivity to transients.

8.3 What to Do and What Not to Do

Do connect a 100 nF decoupling capacitor from (V+) to (V-) for best system performance. If the monitored voltage is noisy, do connect a decoupling capacitor from the comparator input (IN) to (V-). Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input current of the comparator without also accounting for the impact on accuracy. Don't use a pull-up resistor that is too small because the larger current sunk by the output may exceed the desired low-level output voltage (VOL).

9 Power Supply Recommendations

These devices operate from an input voltage supply range between 1.7 V and 5.5 V.

10 Layout

10.1 Layout Guidelines

circumstance, the system would benefit from a bypass capacitor across the supply pins.

10.2 Layout Example

Figure 47. Layout Example

11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to order now. Table 3. Related Links

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

TLV4021, TLV4031, TLV4041, TLV4051 www.ti.com SNVSB04A –MARCH 2019–REVISED MAY 2019 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 11-Jun-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTLV4021R1YKAR ACTIVE DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 PTLV4021R2YKAR ACTIVE DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 TLV4021R1YKAR PREVIEW DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 TLV4021R2YKAR PREVIEW DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 TLV4021S5YKAR ACTIVE DSBGA YKA 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 O TLV4031R1YKAR PREVIEW DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 TLV4041R2YKAR ACTIVE DSBGA YKA 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 8 TLV4051R1YKAR PREVIEW DSBGA YKA 4 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 11-Jun-2019 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV4021S5YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4041R2YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C0.4 MAX 0.18 0.13

0.35 TYP

4X 0.25 0.15 0.35 TYP B E A D 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C 1 2

0.015 C A B

B A SCALE 14.000 D: Max = E: Max = 0.76 mm, Min = 0.76 mm, Min = 0.7 mm 0.7 mm

www.ti.com EXAMPLE BOARD LAYOUT 4X ( 0.2) (0.35) TYP (0.35) TYP ( 0.2) METAL 0.0325 MAX ( 0.2) SOLDER MASK OPENING

0.0325 MIN

DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X 1 2 A B NON-SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4X ( 0.21) (R0.05) TYP METAL TYP 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm - 0.1 mm THICK STENCIL SCALE:60X 1 2 A B

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