TLV4021 TI | Alldatasheet

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Technical content

TLV40x1 Small-Size, Low-Power Comparator with Precision Reference

1 Features

  • Wide supply voltage range: 1.6 V to 5.5 V
  • Precision References: 0.2 V, 0.5 V, and 1.2 V
  • Fixed threshold of 3.2 V
  • Reference accuracy – 0.5% at 25°C – 1% over temperature
  • Low quiescent current: 2 µA
  • Propagation delay: 360 ns
  • Push-pull and open-drain output options
  • Known startup conditions
  • Non-inverting and inverting input options
  • Precision hysteresis
  • Temperature range: –40°C to +125°C
  • Packages: – 0.73 mm × 0.73 mm DSBGA (4-bump) – SOT-23 (5-pin)

2 Applications

  • Self-diagnostics
  • Lithium ion battery monitoring
  • Battery management and protection
  • Current and voltage sensing
  • Analog front end
  • Power management
  • Point of load regulators
  • DC/DC and AC/DC power supplies
  • System control and monitoring

3 Description

The TLV40x1 devices are low-power, high-accuracy comparators with precision references and fast response. The comparators are available in an ultra- small, DSBGA package measuring 0.73 mm × 0.73 mm, making the TLV40x1 applicable for space-critical designs like portable or battery-powered electronics where low-power and fast response to changes in operating conditions is required. The factory-trimmed references and precision hysteresis combine to make the TLV40x1 appropriate for voltage and current monitoring in harsh, noisy environments where slow moving input signals must be converted into clean digital outputs. Similarly, brief glitches on the input are rejected ensuring stable output operation without false triggering. The TLV40x1 are available in multiple configurations allowing system designers to achieve their desired output response. For example, the TLV4021 and TLV4041 offer a non-inverting input, while the TLV4031 and TLV4051 have an inverting input. Furthermore, the TLV4021 and TLV4031 feature an open-drain output stage, while the TLV4041 and TLV4051 feature a push-pull output stage. Lastly, each comparator in the TLV40x1 family is available with a 0.2V, 0.5V, or 1.2V precision reference. Device Information PART NUMBER PACKAGE (1) BODY SIZE (NOM) TLV4021, TLV4031, TLV4041, TLV4051 DSBGA (4) 0.73 mm × 0.73 mm TLV4041, TLV4051 SOT-23 (5) 2.9 mm × 1.6 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. IN V+ V 1.2V Fixed Threshold TLV4021S5x IN OUT V REF Inver ng TLV4031 TLV4051 IN OUT V REF Non-Inver ng TLV4021 TLV4041 TLV40x1 Configurations TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table 3-1. TLV40x1 Truth Table DEVICE Input Configuration Reference Output Type TLV4021R1 Non-Inverting 1.2 V Open-Drain TLV4041R1 Push-Pull TLV4041R5 0.5 v Push-Pull TLV4021R2 0.2 V Open-Drain TLV4041R2 Push-Pull TLV4031R1 Inverting 1.2 V Open-Drain TLV4051R1 Push-Pull TLV4051R5 0.5 V Push-Pull TLV4031R2 0.2 V Open-Drain TLV4051R2 Push-Pull DEVICE Input Configuration Fixed Threshold Output Type TLV4021S5x Non-Inverting 3.2 V Open-Drain IN OUT V 0.2V – IN OUT V 0.2V – IN OUT V 1.2V VPU IN OUT V 1.2V VPU TLV4021R2 TLV4021R1 TLV4041R2 TLV4041R1 IN OUT V 0.2V IN OUT V 0.2V IN OUT V 1.2V VPU IN OUT V 1.2V VPU TLV4031R2 TLV4031R1 TLV4051R2 TLV4051R1 IN V+ V 1.2V VPU TLV4021S5x IN OUT V 0.5V TLV4051R5 IN OUT V 0.5V TLV4041R5 TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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12.1 Receiving Notification of Documentation Updates..25

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2020) to Revision C (December 2021) Page Changes from Revision A (May 2019) to Revision B (March 2020) Page Changes from Revision * (October 2018) to Revision A (May 2019) Page www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

5 Pin Configuration and Functions

A B Top View Figure 5-1. YKA Package 4-Bump DSBGA Top View Table 5-1. DSBGA Package Pin Functions PIN I/O DESCRIPTION NAME NUMBER OUT A1 O Comparator output: OUT is push-pull on TLV4041/4051 and open-drain on TLV4021/4031 V+ B1 P Positive (highest) power supply V– B2 P Negative (lowest) power supply IN A2 I Comparator input: IN is non-Inverting on TLV4021/4041 and inverting on TLV4031/4051 OUTV+ NC IN Top View Figure 5-2. SOT-23 Package 5-pin Top View Table 5-2. SOT-23 Pin Functions PIN I/O DESCRIPTION NAME NUMBER V+ 1 P Positive (highest) power supply V- 2 P Negative (lowest) power supply NC 3 x No connect; this pin is not internally connected to the die. It can be grounded if that is preferred in the system. IN 4 I Comparator input: IN is inverting on TLV4031/4051 OUT 5 O Comparator output: OUT is push-pull on TLV4041/4051 TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) –0.3 6 V Input voltage (IN) from (V–) (2) –0.3 6 V Input Current (IN)(2) ±10 mA Output voltage (OUT) from (V-) TLV4021, TLV4031 –0.3 6 V TLV4041, TLV4051 –0.3 (V+) + 0.3 V Output short-circuit duration(3) 10 s Junction temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Input terminals are diode-clamped to (V–). Input signals that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or less. In addition, IN can be greater than (V+) and OUT as long as it is within the –0.3 V to 6 V range. Input signals that can swing beyond this range must be current-limited to 10 mA or less. (3) Short-circuit to ground.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage: VS = (V+) – (V–) 1.6 5.5 V Ambient temperature, TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC (1) TLV40x1 UNITYKA (DSBGA) SOT-23 (DBV)

4 BUMPS 5 PINS

RθJA Junction-to-ambient thermal resistance 205.5 181.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 1.8 101.1 °C/W RθJB Junction-to-board thermal resistance 75.3 52.0 °C/W ψJT Junction-to-top characterization parameter 0.9 28.2 °C/W ψJB Junction-to-board characterization parameter 74.7 51.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

6.5 Electrical Characteristics

VS = 1.8 V to 5 V, typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1R1 1.194 1.2 1.206 V Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 1.188 1.212 VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 1.174 1.18 1.186 Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40°C to +125°C 1.168 1.192 VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1R2 0.197 0.2 0.203 V Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 0.196 0.204 VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 0.177 0.18 0.183 Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40°C to +125°C 0.176 0.184 VIT+ Postive-going input threshold voltage (TLV40x1R5 only) VS = 1.8 V and 5 V, TA = 25°C TLV40x1R5 0.495 0.5 0.505 V Postive-going input threshold voltage (TLV40x1R5 only) VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 0.49 0.51 V VIT- Negative-going input threshold voltage (TLV40x1R5 only) VS = 1.8 V and 5 V, TA = 25°C 0.4752 0.48 0.4848 V Negative-going input threshold voltage (TLV40x1R5 only) VS = 1.8 V and 5 V, TA = -40°C to +125°C 0.4704 0.4896 V VIT+ Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C TLV4021S5x 3.238 3.254 3.270 V Postive-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 3.221 3.287 V VIT- Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = 25°C 3.184 3.2 3.216 V Negative-going input threshold voltage VS = 1.8 V and 5 V, TA = -40℃ to +125℃ 3.168 3.232 V VHYS (2) Input hysteresis voltage VS = 1.8 V and 5 V, TA = 25℃ TLV40x1Ry 20 mV VHYS Input hysteresis voltage (TLV40x1R5 only) VS = 1.8 V and 5 V, TA = 25℃ TLV40x1R5 20 mV VHYS (2) Input hysteresis voltage VS = 1.8 V and 5 V, TA = 25°C TLV40x1S5x 54 mV VIN Input voltage range TA = -40℃ to +125℃ V– 5.5 V IBIAS Input bias current Over VIN range 10 pA IBIAS Input bias current (TLV4021S5x only) IN = 3.3 V 1.65 µA VOL Voltage output swing from (V–) ISINK = 200 µA, OUT asserted low, VS = 5 V, TA = –40°C to +125°C 100 mV ISINK = 3 mA, OUT asserted low, VS = 5 V, TA = –40°C to +125°C 400 mV VOH Voltage output swing from (V+) (TLV4041/4051 only) ISOURCE = 200 µA, OUT asserted high, VS = 5 V, TA = –40°C to +125°C 100 mV ISOURCE = 3 mA, OUT asserted high, VS = 5 V, TA = –40°C to +125°C 400 mV IO-LKG Open-drain output leakage current (TLV4021/4031 only) VS = 5 V, OUT asserted high VPULLUP = (V+), TA = 25°C 20 pA ISC Short-circuit current VS = 5 V, sinking, TA = 25°C 55 mA ISC Short-circuit current VS = 5 V, sourcing, TA = 25°C (TLV4041/4051 only) 50 mA TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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6.5 Electrical Characteristics (continued)

VS = 1.8 V to 5 V, typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IQ Quiescent current No load, TA = 25°C, Output Low, VS = 1.8 V 2 3.5 µA No load, TA = –40°C to +125°C, Output Low, VS = 1.8 V 5 µA VPOR (1) Power-on reset voltage 1.45 V (1) See Section 7.4.1 (Power ON Reset) for more details. (2) See Section 7.4.3 (Switching Thresholds and Hysteresis) for more details.

6.6 Switching Characteristics

Typical values are at TA = 25°C, VS = 3.3 V, CL = 15 pF; Input overdrive = 100 mV for TLV40x1Ry & 5% for TLV4021S5x, RP=4.99 kΩ for open-drain options (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHL Propagation delay, high-to-low (1) Midpoint of input to midpoint of output 360 ns tPLH Propagation delay, low-to-high (1) Midpoint of input to midpoint of output 360 ns tPHL Propagation delay, high-to-low (1) (TLV4021S5x only) Midpoint of input to midpoint of output 2 µs tPLH Propagation delay, low-to-high (1) (TLV4021S5x only) Midpoint of input to midpoint of output 2 µs tR Rise time (TLV4041/4051 only) 20% to 80% 10 ns tF Fall time 20% to 80% 10 ns tON Power-up time (2) 500 µs (1) High-to-low and low-to-high refers to the transition at the input. (2) During power on cycle, VS must exceed 1.6 V for tON before the output will reflect the condition on the input. Prior to tON elapsing, the output is controlled by the POR circuit. www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

7 Typical Characteristics

at TJ = 25°C and VS = 3.3 V (unless otherwise noted) Temperature (°C) VIT+ (V) -40 -20 0 20 40 60 80 100 120 140 1.1985 1.1988 1.1991 1.1994 1.1997 1.2 1.2003 1.2006 1.2009 1.2012 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R1 Figure 7-1. Positive Threshold vs Temperature VIT+ (V) Device Count 1500 3000 4500 6000 7500 9000 10500 12000 13500 15000 16500 18000 19500 21000 TLV40x1R1 VS = 5 V Figure 7-2. Positive Threshold Histogram Temperature (°C) VIT- (V) -40 -20 0 20 40 60 80 100 120 140 1.1781 1.1784 1.1787 1.179 1.1793 1.1796 1.1799 1.1802 1.1805 1.1808 1.1811 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R1 Figure 7-3. Negative Threshold vs Temperature VIT- (V) Device Count 1500 3000 4500 6000 7500 9000 10500 12000 13500 15000 16500 18000 19500 21000 TLV40x1R1 VS = 5 V Figure 7-4. Negative Threshold Histogram Temperature (°C) VHYST (mV) -40 -20 0 20 40 60 80 100 120 140 19.92 20.08 20.16 20.24 20.32 20.4 20.48 20.56 20.64 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R1 Figure 7-5. Hysteresis vs Temperature VHYST (mV) Device Count 17 18 19 20 21 22 23 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 TLV40x1R1 VS = 5 V Figure 7-6. Hysteresis Histogram TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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7 Typical Characteristics (continued)

at TJ = 25°C and VS = 3.3 V (unless otherwise noted) Temperature (°C) VIT+ (V) -40 -20 0 20 40 60 80 100 120 140 0.1992 0.19935 0.1995 0.19965 0.1998 0.19995 0.2001 0.20025 0.2004 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R2 Figure 7-7. Positive Threshold vs Temperature VIT+ (V) Device Count 3000 6000 9000 12000 15000 18000 21000 24000 27000 30000 TLV40x1R2 VS = 5 V Figure 7-8. Positive Threshold Histogram Temperature (°C) VIT- (V) -40 -20 0 20 40 60 80 100 120 140 0.17944 0.17952 0.1796 0.17968 0.17976 0.17984 0.17992 0.18 0.18008 0.18016 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R2 Figure 7-9. Negative Threshold vs Temperature VIT- (V) Device Count 3000 6000 9000 12000 15000 18000 21000 24000 27000 30000 TLV40x1R2 VS = 5 V Figure 7-10. Negative Threshold Histogram Temperature (°C) VHYST (mV) -40 -20 0 20 40 60 80 100 120 140 20.02 20.04 20.06 20.08 20.1 20.12 20.14 20.16 20.18 20.2 20.22 VS = 1.8V VS = 3.3V VS = 5.0V TLV40x1R2 Figure 7-11. Hysteresis vs Temperature VHYST (mV) Device Count 17 18 19 20 21 22 23 100 150 200 250 300 350 400 450 500 TLV40x1R2 VS = 5 V Figure 7-12. Hysteresis Histogram www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

at TJ = 25°C and VS = 3.3 V (unless otherwise noted) Temperature (°C) VIT+ (V) -40 -20 0 20 40 60 80 100 120 140 3.248 3.2485 3.249 3.2495 3.25 3.2505 3.251 3.2515 3.252 3.2525 3.253 3.2535 3.254 3.2545 VS = 1.8V VS = 3.3V VS = 5.0V TLV4021S5x Figure 7-13. Positive Threshold vs Temperature VIT+ (V) Device Count 2500 5000 7500 10000 12500 15000 17500 20000 22500 25000 TLV4021S5x Figure 7-14. Positive Threshold Histogram Temperature (°C) VIT- (mV) -40 -20 0 20 40 60 80 100 120 140 3.1945 3.195 3.1955 3.196 3.1965 3.197 3.1975 3.198 3.1985 3.199 3.1995 3.2 3.2005 3.201 3.2015 VS = 1.8V VS = 3.3V VS = 5.0V TLV4021S5x Figure 7-15. Negative Threshold vs Temperature VIT- (V) Device Count 2500 5000 7500 10000 12500 15000 17500 20000 22500 25000 TLV4021S5x Figure 7-16. Negative Threshold Histogram VS (V) VHYST (mV) 52.4 52.6 52.8 53.2 53.4 53.6 53.8 -40°C 25°C 85°C 125°C TLV4021S5x Figure 7-17. Hysteresis vs Supply Voltage Hysteresis (mV) Device Count 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 2000 4000 6000 8000 10000 12000 14000 16000 18000 TLV4021S5x Figure 7-18. Hysteresis Histogram TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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at TJ = 25°C and VS = 3.3 V (unless otherwise noted) VIN (V) IBIAS (pA) 0.001 0.01 0.1 100 1000 5000 -40°C 25°C 85°C 125°C VS = 1.8V to 5V TLV40x1Ry Figure 7-19. Bias Current vs Common Mode Voltage Temperature (°C) IO-LKG (pA) -40 -20 0 20 40 60 80 100 120 140 0.001 0.01 0.1 100 1000 5000 VS = 1.8V VS = 3.3V VS = 5V Figure 7-20. Output Current Leakage vs Temperature Output Sinking Current (mA) Output Voltage from V- (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 -40°C 0°C 25°C 125°C VS = 1.8V Figure 7-21. Output Voltage vs Output Sinking Current Output Sourcing Current (mA) Output Voltage from V+ (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 -40°C 0°C 25°C 125°C VS = 1.8V Figure 7-22. Output Voltage vs Output Sourcing Current Output Sinking Current (mA) Output Voltage from V- (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 5 5 -40°C 0°C 25°C 125°C VS = 3.3V Figure 7-23. Output Voltage vs Output Sinking Current Output Sourcing Current (mA) Output Voltage from V+ (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.005 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 5 5 -40°C 0°C 25°C 125°C VS = 3.3V Figure 7-24. Output Voltage vs Output Sourcing Current www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

at TJ = 25°C and VS = 3.3 V (unless otherwise noted) Output Sinking Current (mA) Output Voltage from V- (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.005 0.01 0.02 0.05 0.1 0.2 0.5 -40°C 0°C 25°C 125°C VS = 5V Figure 7-25. Output Voltage vs Output Sinking Current Output Sourcing Current (mA) Output Voltage from V+ (V) 0.1 0.2 0.3 0.5 1 2 3 4 5 67 10 20 30 50 70100 0.005 0.01 0.02 0.05 0.1 0.2 0.5 -40°C 0°C 25°C 125°C VS = 5V Figure 7-26. Output Voltage vs Output Sourcing Current Temperature (°C) IQ (uA) -40 -20 0 20 40 60 80 100 120 140 1.4 1.6 1.8 2.2 2.4 2.6 2.8 3.2 VS = 1.8V VS = 3.3V VS = 5V Figure 7-27. Supply Current vs Temperature VOD (mV) tpLH (ns) 0 20 40 60 80 100 120 140 160 180 200 220 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 -40°C 25°C 85°C 125°C VS = 1.8V to 5V TLV40x1R2 Figure 7-28. Propagation Delay Low-High vs Input Overdrive VOD (mV) tpHL (ns) 0 20 40 60 80 100 120 140 160 180 200 220 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 -40°C 25°C 85°C 125°C VS = 1.8V to 5V TLV40x1R2 Figure 7-29. Propagation Delay High-Low vs Input Overdrive VOD (%) tpLH (us) 0 1 2 3 4 5 6 7 8 9 10 11 1.5 2.5 3.5 4.5 5.5 -40°C 25°C 85°C 125°C VS = 1.8V to 5V TLV4021Sx5 Figure 7-30. Propagation Delay Low-High vs Input Overdrive TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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at TJ = 25°C and VS = 3.3 V (unless otherwise noted) VOD (%) tpHL (us) 0 1 2 3 4 5 6 7 8 9 10 11 1.5 2.5 3.5 4.5 5.5 6.5 7.5 -40°C 25°C 85°C 125°C VS = 1.8V to 5V TLV4021Sx5 Figure 7-31. Propagation Delay High-Low vs Input Overdrive www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

8 Detailed Description

8.1 Overview

The TLV40x1 devices are low-power comparators that are well suited for compact, low-current, precision voltage quiescent current, and propagation delay of 450ns and 2us, the TLV40x1 comparator family enables power conscious systems to monitor and respond quickly to fault conditions. The TLV40x1Ry comparators assert the output signal as shown in Table 8-1. VIT+ represents the positive-going input threshold that causes the comparator output to change state, while VIT- represents the negative-going input threshold that causes the output to change state. Since V IT+ and V IT- are factory trimmed and warranted over temperature, the TLV40x1 is equally suited for undervoltage and overvoltage applications. In order to monitor any voltage above the internal reference voltage, an external resistor divider network is required. The TLV4021S5x functions similar to the TLV40x1Ry comparators except the resistor divider is internal to the device. Having the resistor divider internal to the device allows the TLV4021S5x to have switching thresholds higher than the internal reference voltage of 1.2V without any external components. Table 8-1. TLV40x1 Truth Table DEVICE (VIT+, VIT-) OUTPUT TOPOLOGY INPUT VOLTAGE OUTPUT LOGIC LEVEL TLV4021R2 TLV4021R1 0.2V, 0.18V 1.2V, 1.18V Open-Drain IN > VIT+ Output high impedance IN < VIT- Output asserted low TLV4041R2 TLV4041R5 TLV4041R1 0.2V, 0.18V 0.5V, 0.48V 1.2V, 1.18V Push-Pull IN > VIT+ Output asserted high IN < VIT- Output asserted low TLV4031R2 TLV4031R1 0.2V, 0.18V 1.2V, 1.18V Open-Drain IN > VIT+ Output asserted low IN < VIT- Output high impedance TLV4051R2 TLV4051R5 TLV4051R1 0.2V, 0.18V 0.5V, 0.48V 1.2V, 1.18V Push-Pull IN > VIT+ Output asserted low IN < VIT- Output asserted high TLV4021S5x 3.254V, 3.2V Open-Drain IN > VIT+ Output high impedance IN < VIT- Output asserted low TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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8.2 Functional Block Diagram

V 0.2V – IN OUT V 0.2V – IN OUT V 1.2V VPU IN OUT V 1.2V VPU TLV4021R2 TLV4021R1 TLV4041R2 TLV4041R1 IN OUT V 0.2V IN OUT V 0.2V IN OUT V 1.2V VPU IN OUT V 1.2V VPU TLV4031R2 TLV4031R1 TLV4051R2 TLV4051R1 IN V+ V 1.2V VPU TLV4021S5x IN OUT V 0.5V TLV4051R5 IN OUT V 0.5V TLV4041R5 www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

8.3 Feature Description

The TLV40x1 is a family of 4-pin, precision, low-power comparators with precision switching thresholds. The TLV40x1 comparators feature a rail-to-rail input stage with factory programmed switching thresholds for both rising and falling input waveforms. The comparator family also supports open-drain and push-pull output configurations as well as non-inverting and inverting inputs.

8.4 Device Functional Modes

8.4.1 Power ON Reset (POR)

The TLV40x1 comparators have a Power-on-Reset (POR) circuit which provides system designers a known start-up condition for the output of the comparators. When the power supply (VS) is ramping up or ramping down, the POR circuit will be active when V S is below V POR. For the TLV4021 and TLV4031, the POR circuit will force the output to High-Z, and for the TLV4041 and TLV4051, the POR circuit will hold the output low at (V-). When VS is greater than, or equal to, the minimum recommended operating voltage, the comparator output reflects the state of the input (IN). The following pictures represent how the TLV40x1 outputs respond for VS rising and falling. For the comparators with open-drain outputs (TLV4021/4031), IN is connected to (V-) to highlight the transition from POR circuit control to standard comparator operation where the output reflects the input condition. Note how the output goes low when V S reaches 1.45V. Likewise, for the comparators with push-pull outputs (TLV4041/4051), the input is connected to (V+). Note how the output goes high when VS reaches 1.45V. Time (s) Voltage (V) -0.5 0.5 1.5 2.5 3.5 4.5 VS VOUT Figure 8-1. TLV4021/4031 Output for VS Rising Time (s) Voltage (V) -0.5 0.5 1.5 2.5 3.5 4.5 VS VOUT Figure 8-2. TLV4021/4031 Output for VS Falling Time (s) Voltage (V) -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VS VOUT Figure 8-3. TLV4041/4051 Output for VS Rising Time (s) Voltage (V) -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VS VOUT Figure 8-4. TLV4041/4051 Output for VS Falling TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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8.4.2 Input (IN)

The TLV40x1 comparators have two inputs: one external input (IN) and one internal input that is connected to the integrated voltage reference. The comparator rising threshold is trimmed to the reference voltage (VIT+) while the falling threshold is trimmed to (V IT-). Since the rising and falling thresholds are both trimmed and warranted in the Electrical Characteristics Table, the TLV40x1 is equally suited for undervoltage and overvoltage detection. The difference between (VIT+) and (VIT-) is referred to as the comparator hysteresis and is 20 mV for TLV40x1Ry and 54 mV for TLV4021S5x. The integrated hysteresis makes the TLV40x1 less sensitive to supply-rail noise and provides stable operation in noisy environments without having to add external positive feedback to create hysteresis. The comparator input (IN) is able to swing 5.5 V above (V-) regardless of the device supply voltage. This includes the instance when no supply voltage is applied to the comparator (V S = 0 V). As a result, the TLV40x1 is referred to as fault tolerant, meaning it maintains the same high input impedance when V S is unpowered or ramping up. While not required in most cases, in order to reduce sensitivity to transients and layout parasitics for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor at the comparator input. For the TLV40x1Ry comparators, the input bias current is typically 10 pA for input voltages between (V-) and (V+) and the value typically doubles for every 10°C temperature increase. The comparator input is protected from voltages below (V-) by an internal diode connected to (V-). As the input voltage goes below (V-), the protection diode becomes forward biased and begins to conduct causing the input bias current to increase exponentially. A series resistor is recommended to limit the input current when sources have signal content that is less than (V-). For the TLV4021S5x, the input bias current is limited by the internal resistor divider with typical impedance of 2M ohms.

8.4.3 Switching Thresholds and Hysteresis (VHYS)

The TLV40x1 transfer curve is shown in Figure 8-5.

  • VIT+ represents the positive-going input threshold that causes the comparator output to change from a logic low state to a logic high state.
  • VIT- represents the negative-going input threshold that causes the comparator output to change from a logic high state to a logic low state.
  • VHYS represents the difference between VIT+ and VIT- and is 20 mV for TLV40x1Ry and 54 mV for TLV4021S5x. VIT- V IT+ VHYS = (VIT+) ± (VIT-) Figure 8-5. Transfer Curve VIT+ and VIT- have mV's of variation over temperature. The significant portion of the variation of these parameters is a result of the internal bandgap voltage from which V IT+ and V IT- are derived. The following hysteresis histograms demonstrate the performance of the TLV40x1 hysteresis circuitry. Since the bandgap reference is used to set V IT+ and V IT-, each of these parameters have a tendency to error (track) in the same direction. For example, if V IT+ has a positive 0.5% error, V IT- would have a tendency to have a similar positive percentage error. As a result, the variation of hysteresis will never be equal to the difference of the highest V IT+ value of its range and the lowest VIT- value of its range. www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

VHYST (mV) Device Count 17 18 19 20 21 22 23 100 150 200 250 300 350 400 450 500 Figure 8-6. VHYST Histogram (TLV40x1R2, VS=5V) VHYST (mV) Device Count 17 18 19 20 21 22 23 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Figure 8-7. VHYST Histogram (TLV40x1R1, VS=5V) Hysteresis (mV) Device Count 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 2000 4000 6000 8000 10000 12000 14000 16000 18000 Figure 8-8. VHYST Histogram (TLV40x1S5, VS=5V)

8.4.4 Output (OUT)

The TLV4041 and TLV4051 feature a push-pull output stage which eliminates the need for an external pull-up resistor while providing a low impedance output driver. Likewise, the TLV4021 and TLV4031 feature an open- drain output stage which enables the output logic levels to be pulled-up to an external source as high as 5.5 V independent of the supply voltage. In a typical TLV40x1 application, OUT is connected to an enable input of a processor or a voltage regulator such as a dc-dc converter or low-dropout regulator (LDO). The open-drain output versions (TLV4021/4031) are used if the power supply of the comparator is different than the supply voltage of the device being controlled. In this usage case, a pull-up resistor holds OUT high when the comparator output goes high impedance. The correct interface-voltage level is provided (also known as level-shifting) by connecting the pull-up resistor on OUT to the appropriate voltage rail. The TLV4021/4031 output can be pulled up to 5.5 V, independent of the device supply voltage (VS). However, if level-shifting is not required, the push-pull output versions (TLV4041/4051) should be utilized in order to eliminate the need for the pull-up resistor. TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TLV40x1 is a 4-pin, low-power comparator with a precision, integrated reference. The comparators in this family are well suited for monitoring voltages and currents in portable, battery powered devices.

9.1.1 Monitoring (V+)

Many applications monitor the same rail that is powering the comparator. In these applications the resistor divider is simply connected to the (V+) rail. IN OUT Supply Figure 9-1. Supply Monitoring www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

9.1.2 Monitoring a Voltage Other than (V+)

Some applications monitor rails other than the one that is powering the comparator. In these applications the resistor divider used to set the desired threshold is connected to the rail that is being monitored. VMON Supply IN OUT REF TLV40x1 Figure 9-2. Monitoring a Voltage Other than the Supply The TLV40x1Ry can monitor a voltage greater than the maximum (V+) with the use of an external resistor divider network. Likewise, the TLV40x1 can monitor voltages as low as the internal reference voltage (0.2 V, 0.5 V, or 1.2 V). The TLV40x1Ry also has the advantage of being able to monitor high impedance sources since the input bias current of the input (IN) is low. This provides an advantage over voltage supervisors that can only monitor the voltage rail that is powering them. Supervisors configured in this fashion have limitations in source impedance and minimum sensing voltage.

9.1.3 VPULLUP to a Voltage Other than (V+)

For applications where the output of the comparator needs to interface with a reset/enable pin that operates from a different supply voltage, the open-drain comparators (TLV4021/4031) should be selected. In these usage cases, the output can be pulled up to any voltage that is lower than 5.5V (independent of (V+)). This technique is commonly referred to as "level-shifting." VMON IN OUT Supply VPULLUP RPULLUP (up to 5.5V) Figure 9-3. Level-Shifting TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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9.2 Typical Application

9.2.1 Under-Voltage Detection

Under-voltage detection is frequently required in battery-powered, portable electronics to alert the system that a battery voltage has dropped below the usable voltage level. Figure 9-4 shows a simple under-voltage detection circuit using the TLV4041R1 which is a non-inverting comparator with an integrated 1.2 V reference and a push- pull output stage. The non-inverting TLV4041 option was selected in this example since the micro-controller required an active low signal when an undervoltage level occurs. However, if an active high signal was required, the TLV4051 option with an inverting input stage would be utilized. VBAT IN OUT ALERT 3.3V Micro- controller 1.2V t TLV4041R1 Figure 9-4. Under-Voltage Detection

9.2.1.1 Design Requirements

For this design, follow these design requirements:

  • Operate from 3.3 V power supply that powers the microcontroller.
  • Under-voltage alert is active low.
  • Logic low output when VBAT is less than 2.0V.

9.2.1.2 Detailed Design Procedure

Configure the circuit as shown in Figure 9-4 . Connect (V+) to 3.3 V which also powers the micro-controller. Resistors R1 and R2 create the under-voltage alert level of 2.0 V. When the battery voltage sags down to 2.0 V, the resistor divider voltage crosses the (V IT-) threshold of the TLV4041R1. This causes the comparator output to transition from a logic high to a logic low. The push-pull option of the TLV40x1 family is selected since the comparator operating voltage is shared with the microcontroller which is receiving the under-voltage alert signal. The TLV4041 option with the 1.2 V internal reference is selected because it is the closest internal reference option that is less than the critical under-voltage level of 2.0 V. Choosing the internal reference option that is closest to the critical under-voltage level minimizes the resistor divider ratio which optimizes the accuracy of the circuit. Error at the falling edge threshold of (V IT-) is amplified by the inverse of the resistor divider ratio. So minimizing the resistor divider ratio is a way of optimizing voltage monitoring accuracy. www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

Equation 1 is derived from the analysis of Figure 9-4. (1) where

  • R1 and R2 are the resistor values for the resistor divider connected to IN
  • VBAT is the voltage source that is being monitored for an undervoltage condition.
  • VIT- is the falling edge threshold where the comparator output changes state from high to low Rearranging Equation 1 and solving for R1 yields Equation 2. (2) For the specific undervoltage detection of 2.0 V using the TLV4041R1, the following results are calculated. (3) where
  • R2 is set to 1 MΩ
  • VBAT is set to 2.0 V
  • VIT- is set to1.18 V Choose RTOTAL (R1 + R2) such that the current through the divider is at least 100 times higher than the input bias current (IBIAS). The resistors can have high values to minimize current consumption in the circuit without adding significant error to the resistive divider.

9.2.1.3 Application Curve

3.3V 2.03V Figure 9-5. Under-Voltage Detection TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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9.2.2 Additional Application Information

9.2.2.1 Pull-up Resistor Selection

For the TLV4021 (open-drain output versions of the TLV40x1 family), care should be taken in selecting the pull-up resistor (RPU) value to ensure proper output voltage levels. First, consider the required output high logic level requirement of the logic device that is being driven by the comparator when calculating the maximum R PU value. When in a logic high output state, the output impedance of the comparator is very high but there is a finite amount of leakage current that needs to be accounted for. Use I O-LKG from the EC Table and the V IH minimum from the logic device being driven to determine RPU maximum using Equation 4. (4) Next, determine the minimum value for R PU by using the V IL maximum from the logic device being driven. In order for the comparator output to be recognized as a logic low, V IL maximum is used to determine the upper boundary of the comparator's VOL. VOL maximum for the comparator is available in the EC Table for specific sink current levels and can also be found from the V OUT versus ISINK curve in the Typical Application curves. A good design practice is to choose a value for V OL maximum that is 1/2 the value of V IL maximum for the input logic device. The corresponding sink current and V OL maximum value will be needed to calculate the minimum R PU. This method will ensure enough noise margin for the logic low level. With V OL maximum determined and the corresponding ISINK obtained, the minimum RPU value is calculated with Equation 5. (5) Since the range of possible R PU values is large, a value between 5 k Ω and 100 k Ω is generally recommended. A smaller R PU value provides faster output transition time and better noise immunity, while a larger R PU value consumes less power when in a logic low output state.

9.2.2.2 Input Supply Capacitor

Although an input capacitor is not required for stability, for good analog design practice, connect a 100 nF low equivalent series resistance (ESR) capacitor from (V+) to (V-).

9.2.2.3 Sense Capacitor

Although not required in most cases, for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor from the comparator input (IN) to the (V-) for good analog design practice. This capacitor placement reduces device sensitivity to transients.

9.3 What to Do and What Not to Do

Do connect a 100 nF decoupling capacitor from (V+) to (V-) for best system performance. If the monitored voltage is noisy, do connect a decoupling capacitor from the comparator input (IN) to (V-). Don't use resistors for the voltage divider that cause the current through them to be less than 100 times the input current of the comparator without also accounting for the impact on accuracy. Don't use a pull-up resistor that is too small because the larger current sunk by the output may exceed the desired low-level output voltage (VOL). www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

10 Power Supply Recommendations

These devices operate from an input voltage supply range between 1.7 V and 5.5 V.

11 Layout

11.1 Layout Guidelines

A power supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due to the fast rising and falling edge rates and high-output sink and source capability of the TLV40x1 output stage, higher than normal quiescent current can be drawn from the power supply when the output transitions. Under this circumstance, the system would benefit from a bypass capacitor across the supply pins.

11.2 Layout Example

C1 (0402) R1 (0402) R2 (0402) OUT Figure 11-1. Layout Example TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 www.ti.com

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLV4021, TLV4031, TLV4041, TLV4051 SNVSB04C – MARCH 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLV4021 TLV4031 TLV4041 TLV4051

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV4021R1YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 Z TLV4021R1YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 Z TLV4021R2YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 6 TLV4021R2YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 6 TLV4021S5MYKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 Q TLV4021S5MYKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 Q TLV4021S5YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 O TLV4021S5YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 O TLV4031R1YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 1 TLV4031R1YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 1 TLV4031R2YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 7 TLV4031R2YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 7 TLV4041R1YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 2 TLV4041R1YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 2 TLV4041R2YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8 TLV4041R2YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 8 TLV4041R5DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23XT TLV4041R5DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23XT TLV4041R5DBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23XT TLV4041R5DBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23XT TLV4041R5YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 A TLV4041R5YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 A TLV4051R1YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 C TLV4051R1YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 C TLV4051R2DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3HQT TLV4051R2DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 3HQT TLV4051R2YKAR Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 9 TLV4051R2YKAR.A Active Production DSBGA (YKA) | 4 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 125 9 TLV4051R5DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23ZT Addendum-Page 1

www.ti.com 9-Nov-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV4051R5DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 23ZT (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV4021R1YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4021R2YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4021S5MYKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4021S5YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4021S5YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4031R1YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4031R2YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4041R1YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4041R2YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4041R5DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV4041R5DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV4041R5YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4051R1YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4051R2DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV4051R2YKAR DSBGA YKA 4 3000 182.0 182.0 20.0 TLV4051R5DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C0.4 MAX 0.18 0.13

0.35 TYP

4X 0.25 0.15 0.35 TYP B E A D 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C 1 2

0.015 C A B

B A SCALE 14.000 D: Max = E: Max = 0.76 mm, Min = 0.76 mm, Min = 0.7 mm 0.7 mm

www.ti.com EXAMPLE BOARD LAYOUT 4X ( 0.2) (0.35) TYP (0.35) TYP ( 0.2) METAL 0.0325 MAX ( 0.2) SOLDER MASK OPENING

0.0325 MIN

DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:60X 1 2 A B NON-SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.35) TYP (0.35) TYP 4X ( 0.21) (R0.05) TYP METAL TYP 4221909/B 08/2018 DSBGA - 0.4 mm max heightYKA0004 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm - 0.1 mm THICK STENCIL SCALE:60X 1 2 A B

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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