TLV2221CDBVR

TLV2221 TI | Alldatasheet

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/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE1996 − REVISED APRIL 2005 3−1WWW.TI.COM /C0068Output Swing Includes Both Supply Rails /C0068Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz /C0068Low Input Bias Current...1 p A T y p /C0068Fully Specified for Single-Supply 3-V and 5-V Operation /C0068Very Low Power ...1 1 0 µA Typ /C0068Common-Mode Input Voltage Range Includes Negative Rail /C0068Wide Supply Voltage Range

2.7 V to 10 V

/C0068Macromodel Included

description

The TLV2221 is a single low-voltage operational amplifier available in the SOT-23 package. It offers a compromise between the ac performance and output drive of the TLV2231 and the micropower TLV2211. It consumes only 150 µA (max) of supply current and is ideal for battery-powered applications. The device exhibits rail-to-rail output performance for increased dynamic range in single- or split-supply applications. The TLV2221 is fully characterized at 3 V and 5 V and is optimized for low-voltage applications. The TLV2221, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with analog-to-digital converters (ADCs). With a total area of 5.6mm 2, the SOT-23 package only requires one third the board space of the standard 8-pin SOIC package. This ultra-small package allows designers to place single amplifiers very close to the signal source, minimizing noise pick-up from long PCB traces. TI has also taken special care to provide a pinout that is optimized for board layout (see Figure 1). Both inputs are separated by GND to prevent coupling or leakage paths. The OUT and IN− terminals are on the same end of the board to provide negative feedback. Finally, gain setting resistors and decoupling capacitor are easily placed around the package. VI VDD+ OUTIN− VDD /GND IN+ C R I R F GND VO Figure 1. Typical Surface Mount Layout for a Fixed-Gain Noninverting Amplifier Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE1996 − REVISED APRIL 2005 3−2 WWW.TI.COM AVAILABLE OPTIONS TA VIOmax AT 25°C PACKAGED DEVICES SYMBOL CHIP FORM ‡TA VIOmax AT 25°C SOT-23 (DBV)† SYMBOL FORM ‡ (Y) 0°C to 70°C 3 mV TLV2221CDBV VADC TLV2221Y−40°C to 85°C 3 mV TLV2221IDBV VADI TLV2221Y † The DBV package available in tape and reel only. ‡ Chip forms are tested at TA = 25°C only. TLV2221Y chip information This chip, when properly assembled, displays characteristics similar to the TLV2221C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 10 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (2) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. OUT IN+ IN− VDD+ (5)(1) (3) (4) (2) VDD− /GND (3) (2) (1) (5) (4)

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044/C0032/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0086/C0069/C0082/C0089/C0032/C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082/C0032/C0083/C0073/C0078/C0071/C0076/C0069/C0032/C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076/C0032/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1997 − REVISED APRIL 2005 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076/C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100/C0032/C0076/C0105/C0110/C0067/C0077/C0079/C0083 WWW.TI.COM• 6−3 equivalent schematic Q3 Q6 Q9 Q12 Q14 Q16 Q2 Q5 Q7 Q8 Q10 Q11 Q17Q15Q13 Q4Q1 VDD+ IN+ IN− OUT VDD−/GND COMPONENT COUNT † Transistors Diodes Resistors Capacitors † Includes both amplifiers and all ESD, bias, and trim circuitry

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 4 WWW.TI.COM absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to VDD − . 2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below VDD− − 0.3 V. 3. The output can be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°CPACKAGE TA ≤ 25C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70C POWER RATING TA = 85C POWER RATING DBV 150 mW 1.2 mW/°C 96 mW 78 mW recommended operating conditions TLV2221C TLV2221I UNITMIN MAX MIN MAX UNIT Supply voltage, VDD /C0040/C0115/C0101/C0101 /C0078/C0111/C0116/C0101 /C0049/C0041 2.7 10 2.7 10 V Input voltage range, VI VDD− VDD+ −1.3 VDD− VDD+ −1.3 V Common-mode input voltage, VIC VDD− VDD+ −1.3 VDD− VDD+ −1.3 V Operating free-air temperature, TA 0 70 −40 85 °C NOTE 1: All voltage values, except differential voltages, are with respect to VDD − .

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 5WWW.TI.COM electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2221C TLV2221I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 0.62 3 0.62 3 mV VIO Temperature coefficient of input Full range 1 1 V/°CαVIO coefficient of input offset voltage Full range 1 1 µV/°C Input offset voltage long-term drift (see Note 4) VDD ± = ±1.5 V, VO = 0, VIC = 0, R S = 50 Ω 25°C 0.003 0.003 µV/mo IIO Input offset current O S 25°C 0.5 0.5 pAIIO Input offset current Full range 150 150 pA IIB Input bias current 25°C 1 1 pAIIB Input bias current Full range 150 150 pA 0 −0.3 0 −0.3 25°C to −0.3 to to −0.3 to VICR Common-mode input R S = 50 Ω |VIO|≤ 5 mV

25 C to

2.2 to to 2.2 VVICR Common-mode input voltage range R S = 50 Ω, |VIO| ≤5 mV 0 0 Vvoltage range Full range to toFull range to 1.7 to 1.7 High-level output IOH = −100 µA 25°C 2.97 2.97 VOH High-level output voltage IOH = −400 A 25°C 2.88 2.88 VVOH voltage IOH = −400 µA Full range 2.5 2.5 V Low-level output VIC = 1.5 V, IOL = 50 µA 25°C 15 15 VOL Low-level output voltage VIC = 1.5 V, IOL = 500 A 25°C 150 150 mVVOL voltage VIC = 1.5 V, IOL = 500 µA Full range 500 500 mV Large-signal V = 1.5 V, R L = 2 kΩ‡ 25°C 2 3 2 3 AVD Large-signal differential voltageVIC = 1.5 V, VO = 1 V to 2 V R L = 2 kΩ‡ Full range 1 1 V/mVAVD differential voltage amplification VO = 1 V to 2 V R L = 1 MΩ‡ 25°C 250 250 V/mV rid Differential input resistance 25°C 1012 1012 Ω ric Common-mode input resistance 25°C 1012 1012 Ω cic Common-mode input capacitance f = 10 kHz 25°C 6 6 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 90 90 Ω CMRR Common-mode VIC = 0 to 1.7 V, 25°C 70 82 70 82 dBCMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 1.5 V, R S = 50Ω Full range 65 65 dB kSVR Supply voltage rejection ratio VDD = 2.7 V to 8 V, 25°C 80 95 80 95 dBkSVR rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load Full range 80 80 dB IDD Supply current VO = 1.5 V, No load 25°C 100 150 100 150 µAIDD Supply current VO = 1.5 V, No load Full range 200 200 µA † Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 6 WWW.TI.COM operating characteristics at specified free-air temperature, VDD = 3 V PARAMETER TEST CONDITIONS TA † TLV2221C TLV2221I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT Slew rate at unity VO = 1.1 V to 1.9 V,R L = 2 kΩ‡, 25°C 0.1 0.18 0.1 0.18 SR Slew rate at unity gain VO = 1.1 V to 1.9 V, C L = 100 pF‡ R L = 2 kΩ‡, Full range 0.05 0.05 V/µs Vn Equivalent input f = 10 Hz 25°C 120 120 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 20 20 nV/√Hz VN(PP) Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 680 680 nVVN(PP ) equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 860 860 nV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz VO = 1 V to 2 V, f = 20 kHz, AV = 1 25°C 2.52% 2.52% THD+N Total harmonic O f = 20 kHz, R L = 2 kΩ‡ AV = 10 25°C 7.01% 7.01% THD+N Total harmonic distortion plus noiseVO = 1 V to 2 V, f = 20 kHz, AV = 1 25°C 0.076% 0.076%O f = 20 kHz, R L = 2 kΩ§ AV = 10 25°C 0.147% 0.147% Gain-bandwidth product f = 1 kHz, C L = 100 pF‡ R L = 2 kΩ‡, 25°C 480 480 kHz BOM Maximum output-swing bandwidth VO(PP) = 1 V, R L = 2 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 30 30 kHz ts Settling time AV = −1, Step = 1 V to 2 V, To 0.1% 25°C 4.5 4.5 µs ts Settling time Step = 1 V to 2 V, R L = 2 kΩ‡, C L = 100 pF‡ To 0.01% 25°C 6.8 6.8 µs φm Phase margin at unity gain R L = 2 kΩ‡, C L = 100 pF‡ 25°C 51° 51° Gain margin R L = 2 kΩ‡, C L = 100 pF‡ 25°C 12 12 dB † Full range is −40°C to 85°C. ‡ Referenced to 1.5 V § Referenced to 0 V

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 7WWW.TI.COM electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2221C TLV2221I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 0.61 3 0.61 3 mV VIO Temperature coefficient of input Full range 1 1 V/°CαVIO coefficient of input offset voltage Full range 1 1 µV/°C Input offset voltage long-term drift (see Note 4) VDD ± = ±2.5 V, VO = 0, VIC = 0, R S = 50 Ω 25°C 0.003 0.003 µV/mo IIO Input offset current O S 25°C 0.5 0.5 pAIIO Input offset current Full range 150 150 pA IIB Input bias current 25°C 1 1 pAIIB Input bias current Full range 150 150 pA VICR Common-mode input R S = 50 Ω |VIO|≤ 5 mV 25°C to −0.3 to 4.2 to −0.3 to 4.2 VVICR Common-mode input voltage range R S = 50 Ω, |VIO| ≤5 mV Full range to 3.5 to 3.5 V VOH High-level output IOH = −500 µA 25°C 4.75 4.88 4.75 4.88 VVOH High-level output voltage IOH = −1 mA 25°C 4.5 4.76 4.5 4.76 V Low-level output VIC = 2.5 V, IOL = 50 µA 25°C 12 12 VOL Low-level output voltage VIC = 2.5 V, IOL = 500 A 25°C 120 120 mVVOL voltage VIC = 2.5 V, IOL = 500 µA Full range 500 500 mV Large-signal V = 2.5 V, R L = 2 kΩ‡ 25°C 3 5 3 5 AVD Large-signal differential voltageVIC = 2.5 V, VO = 1 V to 4 V R L = 2 kΩ‡ Full range 1 1 V/mVAVD differential voltage amplification VO = 1 V to 4 V R L = 1 MΩ‡ 25°C 800 800 V/mV rid Differential input resistance 25°C 1012 1012 Ω ric Common-mode input resistance 25°C 1012 1012 Ω cic Common-mode input capacitance f = 10 kHz 25°C 6 6 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 70 70 Ω CMRR Common-mode VIC = 0 to 2.7 V,VO = 1.5 V, 25°C 70 85 70 85 dBCMRR Common-mode rejection ratio VIC = 0 to 2.7 V, R S = 50Ω VO = 1.5 V, Full range 65 65 dB kSVR Supply voltage rejection ratio VDD = 4.4 V to 8 V, 25°C 80 95 80 95 dBkSVR rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, VIC = VDD /2, No load Full range 80 80 dB IDD Supply current VO = 2.5 V, No load 25°C 110 150 110 150 µAIDD Supply current VO = 2.5 V, No load Full range 200 200 µA † Full range for the TLV2221C is 0°C to 70°C. Full range for the TLV2221I is − 40°C to 85°C. ‡ Referenced to 2.5 V NOTE 5: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 8 WWW.TI.COM operating characteristics at specified free-air temperature, VDD = 5 V PARAMETER TEST CONDITIONS TA † TLV2221C TLV2221I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT Slew rate at unity VO = 1.5 V to 3.5 V,R L = 2 kΩ‡, 25°C 0.1 0.18 0.1 0.18 SR Slew rate at unity gain VO = 1.5 V to 3.5 V, C L = 100 pF‡ R L = 2 kΩ‡, Full range 0.05 0.05 V/µs Vn Equivalent input f = 10 Hz 25°C 90 90 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 19 19 nV/√Hz VN(PP) Peak-to-peak equivalent input f = 0.1 Hz to 1 Hz 25°C 800 800 nVVN(PP ) equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 960 960 nV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz VO = 1.5 V to 3.5 V, f = 20 kHz, AV = 1 25°C 2.45% 2.45% THD+N Total harmonic O f = 20 kHz, R L = 2 kΩ‡ AV = 10 25°C 5.54% 5.54% THD+N Total harmonic distortion plus noiseVO = 1.5 V to 3.5 V, f = 20 kHz, AV = 1 25°C 0.142% 0.142%O f = 20 kHz, R L = 2 kΩ§ AV = 10 25°C 0.257% 0.257% Gain-bandwidth product f = 1 kHz, C L = 100 pF‡ R L = 2 kΩ‡, 25°C 510 510 kHz BOM Maximum output- swing bandwidth VO(PP) = 1 V, R L = 2 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 40 40 kHz ts Settling time AV = −1, Step = 1.5 V to 3.5 V, To 0.1% 25°C 6.8 6.8 sts Settling time Step = 1.5 V to 3.5 V, R L = 2 kΩ‡, C L = 100 pF‡ To 0.01% 25°C 9.2 9.2 µs φm Phase margin at unity gain R L = 2 kΩ‡, C L = 100 pF‡ 25°C 52° 52° Gain margin R L = 2 kΩ‡, C L = 100 pF‡ 25°C 12 12 dB † Full range is −40°C to 85°C. ‡ Referenced to 2.5 V § Referenced to 0 V

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 9WWW.TI.COM electrical characteristics at VDD = 3 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLV2221Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VDD ± = ±1.5 V, VIC = 0, VO = 0, 620 µV IIO Input offset current VDD ± = ±1.5 V, R S = 50 Ω VIC = 0, V O = 0, 0.5 pA IIB Input bias current R S = 50 Ω 1 pA −0.3 VICR Common-mode input voltage range | VIO| ≤5 mV, R S = 50 Ω −0.3 to VVICR Common-mode input voltage range | VIO| ≤5 mV, R S = 50 Ω to 2.2 V VOH High-level output voltage IOH = −100 µA 2.97 V VOL Low-level output voltage VIC = 1.5 V, IOL = 50 µA 15 mVVOL Low-level output voltage VIC = 1.5 V, IOL = 500 µA 150 mV AVD Large-signal differential VO = 1 V to 2 V R L = 2 kΩ† 3 V/mVAVD Large-signal differential voltage amplification VO = 1 V to 2 V R L = 1 MΩ† 250 V/mV rid Differential input resistance 1012 Ω ric Common-mode input resistance 1012 Ω cic Common-mode input capacitance f = 10 kHz 6 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 90 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, R S = 50 Ω 82 dB kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V,VIC = 0, No load 95 dB IDD Supply current VO = 0, No load 100 µA † Referenced to 1.5 V electrical characteristics at VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLV2221Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VDD ± = ±1.5 V, VIC = 0, VO = 0, 610 µV IIO Input offset current VDD ± = ±1.5 V, R S = 50 Ω VIC = 0, V O = 0, 0.5 pA IIB Input bias current R S = 50 Ω 1 pA −0.3 VICR Common-mode input voltage range | VIO| ≤5 mV, R S = 50 Ω −0.3 to VVICR Common-mode input voltage range | VIO| ≤5 mV, R S = 50 Ω to 4.2 V VOH High-level output voltage IOH = −500 µA 4.88 V VOL Low-level output voltage VIC = 2.5 V, IOL = 50 µA 12 mVVOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA 120 mV AVD Large-signal differential VO = 1 V to 4 V R L = 2 kΩ† 5 V/mVAVD Large-signal differential voltage amplification VO = 1 V to 4 V R L = 1 MΩ† 800 V/mV rid Differential input resistance 1012 Ω ric Common-mode input resistance 1012 Ω cic Common-mode input capacitance f = 10 kHz 6 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 70 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 0, R S = 50 Ω 85 dB kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V,VIC = 0, No load 95 dB IDD Supply current VO = 0, No load 110 µA † Referenced to 2.5 V

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 10 WWW.TI.COM TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution vs Common-mode input voltage 2, 3 4, 5 αVIO Input offset voltage temperature coefficientDistribution 6, 7 IIB/IIO Input bias and input offset currents vs Free-air temperature 8 VI Input voltage vs Supply voltage vs Free-air temperature VOH High-level output voltage vs High-level output current 11, 14 VOL Low-level output voltage vs Low-level output current 12, 13, 15 VO(PP) Maximum peak-to-peak output voltage vs Frequency 16 IOS Short-circuit output current vs Supply voltage vs Free-air temperature VO Output voltage vs Differential input voltage 19, 20 AVD Differential voltage amplification vs Load resistance 21 AVD Large signal differential voltage amplificationvs Frequency vs Free-air temperature 22, 23 24, 25 zo Output impedance vs Frequency 26, 27 CMRR Common-mode rejection ratio vs Frequency vs Free-air temperature kSVR Supply-voltage rejection ratio vs Frequency vs Free-air temperature 30, 31 IDD Supply current vs Supply voltage 33 SR Slew rate vs Load capacitance vs Free-air temperature VO Inverting large-signal pulse response vs Time 36, 37 VO Voltage-follower large-signal pulse responsevs Time 38, 39 VO Inverting small-signal pulse response vs Time 40, 41 VO Voltage-follower small-signal pulse responsevs Time 42, 43 Vn Equivalent input noise voltage vs Frequency 44, 45 Input noise voltage (referred to input) Over a 10-second period 46 THD + N Total harmonic distortion plus noise vs Frequency 47 Gain-bandwidth product vs Free-air temperature vs Supply voltage φm Phase margin vs Frequency vs Load capacitance 22, 23 52, 53 Gain margin vs Load capacitance 50, 51 B1 Unity-gain bandwidth vs Load capacitance 54, 55

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 11WWW.TI.COM TYPICAL CHARACTERISTICS Figure 2 Precentage of Amplifiers − % DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE VIO − Input Offset Voltage − mV

385 Amplifiers From 1 Wafer Lot

VDD = ±1.5 V TA = 25°C Figure 3 Precentage of Amplifiers − % DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE VIO − Input Offset Voltage − mV VDD = ±2.5 V TA = 25°C − Input Offset Voltage − mV INPUT OFFSET VOLTAGE † vs COMMON-MODE INPUT VOLTAGE ÁÁ ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1 0 1 2 VDD = 3 V R S = 50 Ω TA = 25°C Figure 5 − Input Offset Voltage − mV INPUT OFFSET VOLTAGE † vs COMMON-MODE INPUT VOLTAGE ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1 0 1 2 VDD = 5 V R S = 50 Ω TA = 25°C 3 45 † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 12 WWW.TI.COM TYPICAL CHARACTERISTICS Figure 6 DISTRIBUTION OF TLV2221 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † Percentage of Amplifiers − % α VIO − Input Offset Voltage Temperature Coefficient − µV/°C −4 −3 −2 0 1 2 3 VDD = ±1.5 V P Package TA = 25°C to 125°C −1 4

32 Amplifiers From 1 Wafer Lot

DISTRIBUTION OF TLV2221 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT † Percentage of Amplifiers − % α VIO − Input Offset Voltage Temperature Coefficient − µV/°C −4 −3 −2 0 1 2 3 VDD = ±2.5 V P Package TA = 25°C to 125°C −1 4 IIB and IIO − Input Bias and Input Offset Currents − pA INPUT BIAS AND INPUT OFFSET CURRENTS vs FREE-AIR TEMPERATURE IIB IIO TA − Free-Air Temperature − °C 25 45 65 85 100 105 125 VDD ± = ±2.5 V VIC = 0 VO = 0 R S = 50 Ω IIB IIO Figure 9 1 1.5 2 2.5 − Input Voltage − V INPUT VOLTAGE vs SUPPLY VOLTAGE 3 3.5 4 R S = 50 Ω TA = 25°C |VIO| ≤5 mV ÁÁ ÁÁ VI |VDD ±| − Supply Voltage − V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0050/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0086/C0069/C0082/C0089 /C0076/C0079/C0087/C0262/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS157B − JUNE 1996 − REVISED APRIL 2005 26 WWW.TI.COM

APPLICATION INFORMATION

Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 57 are generated using the TLV2221 typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity-gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). OUT − + .SUBCKT TLV2221 1 2 3 4 5 C1 11 12 12.53E−12 C2 6 7 50.00E−12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX FB 7 99 POLY (5) VB VC VE VLP + VLN 0 893.6E3 −90E3 90E3 90E3 −90E3 GA 6 0 11 12 94.25E−6 GCM 0 6 10 99 9.300E−9 ISS 3 10 DC 9.000E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 RD1 60 11 10.61E3 RD2 60 12 10.61E3 R01 8 5 35 R02 7 99 35 RP 3 4 49.50E3 RSS 10 99 22.22E6 VAD 60 4 −.5 VB 9 0 DC 0 VC 3 53 DC .666 VE 54 4 DC .666 VLIM 7 8 DC 0 VLP 91 0 DC 3.4 VLN 0 92 DC 11.4 .MODEL DX D (IS=800.0E−18) .MODEL JX PJF (IS=500.0E−15 BETA=1.527E−3 + VTO=−.001) .ENDS VDD+ RP IN − IN+ VDD− VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DLP DLN VLNVLP Figure 57. Boyle Macromodel and Subcircuit PSpice and Parts are trademark of MicroSim Corporation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV2221CDBVR Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI 0 to 70 VADC TLV2221CDBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI 0 to 70 VADC TLV2221IDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 VADI TLV2221IDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 VADI TLV2221IDBVRG4 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - Call TI Call TI -40 to 85 TLV2221IDBVT Obsolete Production SOT-23 (DBV) | 5 - - Call TI Call TI - VADI (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 23-May-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2221IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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