TLV2211CDBV

TLV2211 TI | Alldatasheet

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SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Output Swing Includes Both Supply Rails /C0068Low Noise . . . 21 nV/√Hz Typ at f = 1 kHz /C0068Low Input Bias Current...1 p A T y p /C0068Very Low Power ...1 1 µA Per Channel Typ /C0068Common-Mode Input Voltage Range Includes Negative Rail /C0068Wide Supply Voltage Range

2.7 V to 10 V

/C0068Available in the SOT-23 Package /C0068Macromodel Included

description

The TLV2211 is a single low-voltage operational amplifier available in the SOT-23 package. It consumes only 11 µA (typ) of supply current and is ideal for battery-power applications. Looking at Figure 1, the TLV2211 has a 3-V noise level of 22 nV/√Hz at 1kHz; 5 times lower than competitive SOT-23 micropower solutions. The device exhibits rail-to-rail output performance for in- creased dynamic range in single- or split-supply applications. The TLV2211 is fully characterized at 3 V and 5 V and is optimized for low-voltage applications. The TLV2211, exhibiting high input impedance and low noise, is excellent for small-signal conditioning for high-impedance sources, such as piezoelectric transducers. Because of the micro- power dissipation levels combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with analog-to-digital converters (ADCs). AVAILABLE OPTIONS TA VIOmax AT 25°C PACKAGED DEVICES SYMBOL CHIP FORM ‡ TA VIOmax AT 25°C SOT-23 (DBV)† SYMBOL CHIP FORM ‡ (Y) 0°C to 70°C 3 mV TLV2211CDBV VACC TLV2211Y −40°C to 85°C 3 mV TLV2211IDBV VACI TLV2211Y † The DBV package available in tape and reel only. ‡ Chip forms are tested at TA = 25°C only. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DBV PACKAGE (TOP VIEW) IN− VDD− /GND IN+ V DD+ OUT − Equivalent Input Noise Voltage − f − Frequency − Hz EQUIVALENT INPUT NOISE VOLTAGE † vs FREQUENCY V n nV/ Hz VDD = 3 V R S = 20 Ω TA = 25°C 101 102 103 104 Figure 1. Equivalent Input Noise Voltage † All loads are referenced to 1.5 V. Advanced LinCMOS is a trademark of Texas Instruments.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

setting resistors and decoupling capacitor are easily placed around the package. Figure 2. Typical Surface Mount Layout for a Fixed-Gain Noninverting Amplifier

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV2211Y chip information This chip, when properly assembled, displays characteristics similar to the TLV2211C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 10 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (2) IS INTERNALLY CONNECTED TO BACK SIDE OF CHIP. OUT IN+ IN− VDD+ (5)(1) (3) (4) (2) VDD− /GND (3) (2) (1) (5) (4)

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IN− OUT VDD−/GND COMPONENT COUNT † Transistors Diodes Resistors Capacitors † Includes both amplifiers and all ESD, bias, and trim circuitry D2R4

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to VDD − . 2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below VDD− − 0.3 V. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°CPACKAGE TA ≤ 25C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70C POWER RATING TA = 85C POWER RATING DBV 150 mW 1.2 mW/°C 96 mW 78 mW recommended operating conditions TLV2211C TLV2211I UNITMIN MAX MIN MAX UNIT Supply voltage, VDD /C0040/C0115/C0101/C0101 /C0078/C0111/C0116/C0101 /C0049/C0041 2.7 10 2.7 10 V Input voltage range, VI VDD− VDD+ −1.3 VDD− VDD+ −1.3 V Common-mode input voltage, VIC VDD− VDD+ −1.3 VDD− VDD+ −1.3 V Operating free-air temperature, TA 0 70 −40 85 °C NOTE 1: All voltage values, except differential voltages, are with respect to VDD − .

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2211C TLV2211I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 0.47 3 0.47 3 mV VIO Temperature coefficient of input Full range 1 1 V/°CαVIO coefficient of input offset voltage VDD = ±1.5 V, VIC = 0, Full range 1 1 µV/°C Input offset voltage long-term drift (see Note 4) VDD ± = ±1.5 V, VO = 0, VIC = 0, R S = 50 Ω 25°C 0.003 0.003 µV/mo IIO Input offset current Full range 0.5 60 0.5 60 pA IIB Input bias current Full range 1 60 1 60 pA 0 −0.3 0 −0.3 25°C to −0.3 to to −0.3 to VICR Common-mode input |VIO |≤ 5 mV, R S = 50 Ω

25 C to

2.2 to to 2.2 VVICR Common-mode input voltage range |VIO | ≤5 mV, R S = 50 Ω 0 0 Vvoltage range Full range to toFull range to 1.7 to 1.7 High-level output IOH = −100 µA 25°C 2.94 2.94 VOH High-level output voltage IOH = −250 A 25°C 2.85 2.85 VVOH voltage IOH = −250 µA Full range 2.5 2.5 V Low-level output VIC = 1.5 V, IOL = 50 µA 25°C 15 15 VOL Low-level output voltage VIC = 1.5 V, IOL = 500 A 25°C 150 150 mVVOL voltage VIC = 1.5 V, IOL = 500 µA Full range 500 500 mV Large-signal V = 1.5 V, R L = 10 kΩ‡ 25°C 3 7 3 7 AVD Large-signal differential voltageVIC = 1.5 V, VO = 1 V to 2 V R L = 10 kΩ‡ Full range 1 1 V/mVAVD differential voltage amplification VO = 1 V to 2 V R L = 1 MΩ‡ 25°C 600 600 V/mV ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, 25°C 5 5 pF zo Closed-loop output impedance f = 7 kHz, AV = 1 25°C 200 200 Ω CMRR Common-mode VIC = 0 to 1.7 V, VO = 1.5 V, 25°C 65 83 65 83 dBCMRR Common-mode rejection ratio VIC = 0 to 1.7 V, R S = 50Ω VO = 1.5 V, Full range 60 60 dB kSVR Supply voltage rejection ratio VDD = 2.7 V to 8 V,VIC = VDD /2 25°C 80 95 80 95 dBkSVR rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, No load VIC = VDD /2 , Full range 80 80 dB IDD Supply current VO = 1.5 V, No load 25°C 11 25 11 25 µAIDD Supply current VO = 1.5 V, No load Full range 30 30 µA † Full range for the TLV2211C is 0°C to 70°C. Full range for the TLV2211I is − 40°C to 85°C. ‡ Referenced to 1.5 V NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2211C TLV2211I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT 25°C 0.01 0.025 0.01 0.025 VO = 1.1 V to 1.9 V,R L = 10 kΩ‡, 25°C 0.01 0.025 0.01 0.025 SR Slew rate at unity gainVO = 1.1 V to 1.9 V, C L = 100 pF‡ R L = 10 kΩ‡, Full 0.005 0.005 V/µsSR Slew rate at unity gainC L = 100 pF‡ Full range 0.005 0.005 V/µs Vn Equivalent input noisef = 10 Hz 25°C 80 80 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 22 22 nV/√Hz VN(PP) Peak-to-peak equivalentf = 0.1 Hz to 1 Hz 25°C 660 660 nVVN(PP ) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 880 880 nV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Gain-bandwidth productf = 10 kHz, R L = 10 kΩ‡, 25°C 56 56 kHzGain-bandwidth productf = 10 kHz, C L = 100 pF‡ R L = 10 kΩ‡, 25°C 56 56 kHz BOM Maximum output-swing VO(PP) = 1 V, AV = 1, ‡ 25°C 7 7 kHzBOM Maximum output-swing bandwidth VO(PP) = 1 V, R L = 10 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 7 7 kHz φm Phase margin at unity gain R L = 10 kΩ‡, C L = 100 pF‡ 25°C 56° 56° Gain margin R L = 10 kΩ‡, C L = 100 pF‡ 25°C 20 20 dB † Full range is −40°C to 85°C. ‡ Referenced to 1.5 V

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2211C TLV2211I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT VIO Input offset voltage 0.45 3 0.45 3 mV αVIO Temperature coefficient of input Full range 0.5 0.5 µV/°CαVIO coefficient of input offset voltage Full range 0.5 0.5 µV/°C Input offset voltage long-term drift (see Note 5) VDD ± = ±2.5 V, VO = 0, VIC = 0, R S = 50 Ω 25°C 0.003 0.003 µV/mo IIO Input offset current VO = 0, R S = 50 25°C 0.5 60 0.5 60 pAIIO Input offset current Full range 150 150 pA IIB Input bias current 25°C 1 60 1 60 pAIIB Input bias current Full range 150 150 pA 0 −0.3 0 −0.3 25°C to −0.3 to to −0.3 to VICR Common-mode input |VIO |≤ 5 mV R S = 50 Ω 4.2 to to 4.2 VVICR Common-mode input voltage range |VIO | ≤5 mV R S = 50 Ω 0 0 Vvoltage range Full range to toFull range to 3.5 to 3.5 High-level output IOH = −100 µA 25°C 4.95 4.95 VOH High-level output voltage IOH = −250 µA 25°C 4.875 4.875 VVOH voltage IOH = −250 µA Full range 4.5 4.5 V Low-level output VIC = 2.5 V, IOL = 50 µA 25°C 12 12 VOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA 25°C 120 120 mVVOL voltage VIC = 2.5 V, IOL = 500 µA Full range 500 500 mV Large-signal VIC = 2.5 V, R L = 10 kΩ‡ 25°C 6 12 6 12 AVD Large-signal differential voltage amplification VIC = 2.5 V, VO = 1 V to 4 V R L = 10 kΩ‡ Full range 3 3 V/mVAVD differential voltage amplificationVO = 1 V to 4 V R L = 1 MΩ‡ 25°C 800 800 V/mV ri(d) Differential input resistance 25°C 1012 1012 Ω ri(c) Common-mode input resistance 25°C 1012 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz, 25°C 5 5 pF zo Closed-loop output impedance f = 7 kHz, AV = 1 25°C 200 200 Ω CMRR Common-mode VIC = 0 to 2.7 V, VO = 2.5 V, 25°C 70 83 70 83 dBCMRR Common-mode rejection ratio VIC = 0 to 2.7 V, R S = 50Ω VO = 2.5 V, Full range 70 70 dB kSVR Supply voltage rejection ratio VDD = 4.4 V to 8 V,VIC = VDD /2, 25°C 80 95 80 95 dBkSVR rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V, No load VIC = VDD /2, Full range 80 80 dB IDD Supply current VO = 2.5 V, No load 25°C 13 25 13 25 µAIDD Supply current VO = 2.5 V, No load Full range 30 30 µA † Full range for the TLV2211C is 0°C to 70°C. Full range for the TLV2211I is − 40°C to 85°C. ‡ Referenced to 1.5 V NOTE 5: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLV2211C TLV2211I UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX MIN TYP MAX UNIT 25°C 0.01 0.025 0.01 0.025 VO = 1.5 V to 3.5 V,R L = 10 kΩ‡, 25°C 0.01 0.025 0.01 0.025 SR Slew rate at unity gainVO = 1.5 V to 3.5 V, C L = 100 pF‡ R L = 10 kΩ‡, Full 0.005 0.005 V/µsSR Slew rate at unity gainC L = 100 pF‡ Full range 0.005 0.005 V/µs Vn Equivalent input noisef = 10 Hz 25°C 72 72 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 21 21 nV/√Hz VN(PP) Peak-to-peak equivalentf = 0.1 Hz to 1 Hz 25°C 600 600 nVVN(PP ) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 25°C 800 800 nV In Equivalent input noise current 25°C 0.6 0.6 fA/√Hz Gain-bandwidth productf = 10 kHz, R L = 10 kΩ‡, 25°C 65 65 kHzGain-bandwidth productf = 10 kHz, C L = 100 pF‡ R L = 10 kΩ‡, 25°C 65 65 kHz BOM Maximum output-swing VO(PP) = 2 V, AV = 1, ‡ 25°C 7 7 kHzBOM Maximum output-swing bandwidth VO(PP) = 2 V, R L = 10 kΩ‡, AV = 1, C L = 100 pF‡ 25°C 7 7 kHz φm Phase margin at unity gain R L = 10 kΩ‡, C L = 100 pF‡ 25°C 56° 56° Gain margin R L = 10 kΩ‡, C L = 100 pF‡ 25°C 22 22 dB † Full range is −40°C to 85°C. ‡ Referenced to 1.5 V electrical characteristics at VDD = 3 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLV2211Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VDD = ±1.5 V, VO = 0, VIC = 0, 0.47 mV IIO Input offset current VDD ± = ±1.5 V, R S = 50 Ω VO = 0, V IC = 0, 0.5 60 pA IIB Input bias current R S = 50 Ω 1 60 pA −0.3VICR Common-mode input voltage range | VIO |≤ 5 mV, R S = 50 Ω −0.3 to 2.2 VVICR Common-mode input voltage range | VIO | ≤5 mV, R S = 50 Ω to 2.2 V VOH High-level output voltage IOH = −100 µA 2.94 VVOH High-level output voltage IOH = −200 µA 2.85 V VOL Low-level output voltage VIC = 0, IOL = 50 µA 15 mVVOL Low-level output voltage VIC = 0, IOL = 500 µA 150 mV AVD Large-signal differential VIC = 1.5 V, VO = 1 V to 2 V R L = 10 kΩ† 7 V/mVAVD Large-signal differential voltage amplification VIC = 1.5 V, VO = 1 V to 2 V R L = 1 MΩ† 600 V/mV ri(d) Differential input resistance 1012 Ω ri(c) Common-mode input resistance 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz 5 pF zo Closed-loop output impedance f = 7 kHz, AV = 1 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 1.7 V, VO = 1.5 V, R S = 50 Ω 83 dB kSVR Supply voltage rejection ratio VDD = 2.7 V to 8 V,VIC = VDD /2, No load 95 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 8 V, VIC = VDD /2, No load 95 dB IDD Supply current VO = 1.5 V, No load 11 µA † Referenced to 1.5 V

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLV2211Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage VDD ± = ±2.5 V, VIC = 0, VO = 0, 0.45 mV IIO Input offset current VDD ± = ±2.5 V, R S = 50 Ω VIC = 0, V O = 0, 0.5 60 pA IIB Input bias current R S = 50 Ω 1 60 pA −0.3VICR Common-mode input voltage range| VIO |≤ 5 mV, R S = 50 Ω −0.3 to 4.2 VVICR Common-mode input voltage range| VIO | ≤5 mV, R S = 50 Ω to 4.2 V VOH High-level output voltage IOH = −100 µA 4.95 VVOH High-level output voltage IOH = −250 µA 4.875 V VOL Low-level output voltage VIC = 2.5 V, IOL = 50 µA 12 mVVOL Low-level output voltage VIC = 2.5 V, IOL = 500 µA 120 mV AVD Large-signal differential VIC = 2.5 V, VO = 1 V to 4 V R L = 10 kΩ† 12 V/mVAVD Large-signal differential voltage amplification VIC = 2.5 V, VO = 1 V to 4 V R L = 1 MΩ† 800 V/mV ri(d) Differential input resistance 1012 Ω ri(c) Common-mode input resistance 1012 Ω ci(c) Common-mode input capacitance f = 10 kHz 5 pF zo Closed-loop output impedance f = 7 kHz, AV = 1 200 Ω CMRR Common-mode rejection ratio VIC = 0 to 2.7 V, VO = 2.5 V, R S = 50 Ω 83 dB kSVR Supply voltage rejection ratio VDD = 4.4 V to 8 V,VIC = VDD /2, No load 95 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.4 V to 8 V,VIC = VDD /2, No load 95 dB IDD Supply current VO = 2.5 V, No load 13 µA † Referenced to 1.5 V

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution vs Common-mode input voltage 3, 4 5, 6 αVIO Input offset voltage temperature coefficientDistribution 7, 8 IIB/IIO Input bias and input offset currents vs Free-air temperature 9 VI Input voltage vs Supply voltage vs Free-air temperature VOH High-level output voltage vs High-level output current 12, 15 VOL Low-level output voltage vs Low-level output current 13, 14, 16 VO(PP) Maximum peak-to-peak output voltage vs Frequency 17 IOS Short-circuit output current vs Supply voltage vs Free-air temperature VO Output voltage vs Differential input voltage 20, 21 AVD Differential voltage amplification vs Load resistance vs Frequency vs Free-air temperature 23, 24 25, 26 zo Output impedance vs Frequency 27, 28 CMRR Common-mode rejection ratio vs Frequency vs Free-air temperature kSVR Supply-voltage rejection ratio vs Frequency vs Free-air temperature 31, 32 IDD Supply current vs Supply voltage 34 SR Slew rate vs Load capacitance vs Free-air temperature VO Large-signal pulse response vs Time 37, 38, 39, 40 VO Small-signal pulse response vs Time 41, 42, 43, 44 Vn Equivalent input noise voltage vs Frequency 45, 46 Noise voltage (referred to input) Over a 10-second period 47 THD + N Total harmonic distortion plus noise vs Frequency 48 Gain-bandwidth product vs Free-air temperature vs Supply voltage φm Phase margin vs Frequency vs Load capacitance 23, 24 Gain margin vs Load capacitance 52 B1 Unity-gain bandwidth vs Load capacitance 53

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Precentage of Amplifiers − % DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE VIO − Input Offset Voltage − mV

376 Amplifiers From 1 Wafer Lot

VDD = ±1.5 V TA = 25°C Figure 4 Precentage of Amplifiers − % DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE VIO − Input Offset Voltage − mV VDD = ±2.5 V TA = 25°C Figure 5 − Input Offset Voltage − mV INPUT OFFSET VOLTAGE † vs COMMON-MODE INPUT VOLTAGE ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 −1 0 1 2 VDD = 3 V R S = 50 Ω TA = 25°C Figure 6 − Input Offset Voltage − mV INPUT OFFSET VOLTAGE † vs COMMON-MODE INPUT VOLTAGE ÁÁ ÁÁ ÁÁ VIO VIC − Common-Mode Input Voltage − V 0.8 0.6 0.4 0.2 −0.2 −0.4 −0.6 −0.8 − 1 01234 5 VDD = 5 V R S = 50 Ω TA = 25°C † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 7 DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Percentage of Amplifiers − % α VIO − Temperature Coefficient − µ V/°C −3 −2 −1 0 1 2 3

32 Amplifiers From 1 Wafer Lot

VDD = ±1.5 V P Package TA = 25°C Figure 8 DISTRIBUTION OF TLV2211 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT Percentage of Amplifiers − % α VIO − Temperature Coefficient − µ V/°C −3 −2 −1 0 1 2 3 VDD = ±2.5 V P Package TA = 25°C Figure 9 IIB and IIO − Input Bias and Input Offset Currents − pA INPUT BIAS AND INPUT OFFSET CURRENTS † vs FREE-AIR TEMPERATURE IIB IIO TA − Free-Air Temperature − °C 25 45 65 85 100 105 125 IIB IIO VDD ± = ±2.5 V VIC = 0 VO = 0 R S = 50 Ω Figure 10 1 1.5 2 2.5 − Input Voltage − V INPUT VOLTAGE vs SUPPLY VOLTAGE 3 3.5 4 R S = 50 Ω TA = 25°C | VIO | ≤5 mV ÁÁ ÁÁ VI | VDD ± | − Supply Voltage − V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

− Input Voltage − V INPUT VOLTAGE †‡ vs FREE-AIR TEMPERATURE ÁÁÁ VI TA − Free-Air Temperature − °C −55 −35 −15 5 25 45 65 85 | VIO | ≤5 mV VDD = 5 V 105 125 Figure 12 − High-Level Output Voltage − V HIGH-LEVEL OUTPUT VOLTAGE †‡ vs HIGH-LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ VOH | IOH | − High-Level Output Current − µ A 1.5 0 200 400 2.5 600 800 VDD = 3 V TA = −40°C 0.5 TA = 25°C TA = 85°C TA = 125°C Figure 13 − Low-Level Output Voltage − V LOW-LEVEL OUTPUT VOLTAGE ‡ vs LOW-LEVEL OUTPUT CURRENT ÁÁ ÁÁ VOL IOL − Low-Level Output Current − mA 0.6 0.4 0.2 0123 0.8 1.2 VDD = 3 V TA = 25°C VIC = 0 VIC = 0.75 V VIC = 1.5 V Figure 14 − Low-Level Output Voltage − V LOW-LEVEL OUTPUT VOLTAGE †‡ vs LOW-LEVEL OUTPUT CURRENT ÁÁ ÁÁ ÁÁ VOL IOL − Low-Level Output Current − mA 0.4 0.2 1.2 012 3 0.8 0.6 1.4 TA = 85°C TA = − 40°C TA = 25°C TA = 125°C VDD = 3 V VIC = 1.5 V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

− Short-Circuit Output Current − mA SHORT-CIRCUIT OUTPUT CURRENT †‡ vs FREE-AIR TEMPERATURE IOS TA − Free-Air Temperature − °C −50 −25 0 25 50 75 100−75 125 VID = −100 mV VID = 100 mV VDD = 5 V VIC = 2.5 V VO = 2.5 V Figure 20 0.5 1.5 2.5 −250−500−750−1000 250 500 750 100 00 VDD = 3 V R I = 10 kΩ VIC = 1.5 V TA = 25°C OUTPUT VOLTAGE ‡ vs DIFFERENTIAL INPUT VOLTAGE VID − Differential Input Voltage − µV − Output Voltage − VV O Figure 21 VID − Differential Input Voltage − µV − Output Voltage − VV O VDD = 5 V VIC = 2.5 V R L = 10 kΩ TA = 25°C −250−500−750−1000 250 500 750 1000 0 OUTPUT VOLTAGE ‡ vs DIFFERENTIAL INPUT VOLTAGE Figure 22 DIFFERENTIAL VOLTAGE AMPLIFICATION ‡ vs LOAD RESISTANCE R L − Load Resistance − kΩ − Differential Voltage Amplification − V/mV ÁÁ ÁÁ A VD 103 102 101 0.1 1 10 1 102 103 VO(PP) = 2 V TA = 25°C VDD = 5 V VDD = 3 V † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VOLTAGE AMPLIFICATION †‡ vs FREE-AIR TEMPERATURE TA − Free-Air Temperature − °C − Large-Signal Differential Voltage A VD Amplification − V/mV −50 −25 0 25 50 75 100 R L = 10 kΩ R L = 1 MΩ 103 102 101 VDD = 3 V VIC = 1.5 V VO = 0.5 V to 2.5 V −75 125 Figure 26 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION †‡ vs FREE-AIR TEMPERATURE TA − Free-Air Temperature − °C − Large-Signal Differential Voltage A VD Amplification − V/mV 104 103 102 101 −75 −50 −25 0 25 50 75 100 12 5 VDD = 5 V VIC = 2.5 V VO = 1 V to 4 V R L = 1 MΩ R L = 10 kΩ Figure 27 − Output Impedance − f− Frequency − Hz OUTPUT IMPEDANCE ‡ vs FREQUENCY Ωzo 101 102 103 104 AV = 100 AV = 10 AV = 1 VDD = 3 V TA = 25°C 103 102 101 Figure 28 − Output Impedance − f− Frequency − Hz OUTPUT IMPEDANCE ‡ vs FREQUENCY Ωzo AV = 100 AV = 1 VDD = 5 V TA = 25°C 101 102 103 104 AV = 10 103 102 101 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

− Supply-Voltage Rejection Ratio − dB SUPPLY-VOLTAGE REJECTION RATIO † vs FREE-AIR TEMPERATURE Á Á Á kSVR TA − Free-Air Temperature − °C 100 −50 −25 0 25 50 75 100 VDD = 2.7 V to 8 V VIC = VO = VDD /2 125−75 Figure 34 − Supply Current − Aµ ÁÁ ÁÁ ÁÁ IDD VDD − Supply Voltage − V SUPPLY CURRENT † vs SUPPLY VOLTAGE VO = VDD/2 VIC = VDD/2 No Load TA = 25°C TA = 85°C TA = −40°C 0246 81 0 Figure 35 SR − Slew Rate − SLEW RATE ‡ vs LOAD CAPACITANCE C L − Load Capacitance − pF 0.030 0.05 0.020 0.040 0.025 0.035 0.010 0.015 101 102 103 104 105 VDD = 5 V AV = −1 TA = 25°C SR− SR+ sµV/ Figure 36 SLEW RATE †‡ vs FREE-AIR TEMPERATURE TA − Free-Air Temperature − °C SR − Slew Rate − sµV/ 0.020 0.010 0.030 0.040 0.050 −50 −25 0 25 50 75 100 SR− SR+ VDD = 5 V R L = 10 kΩ C L = 100 pF A V = 1 −75 125 † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PULSE RESPONSE † − Output Voltage − VVO t − Time − µs 0.68 0.66 074 0.64 01 0 2 0 3 0 0.7 0.72 0.76 40 50 VDD = 3 V R L = 10 kΩ C L = 100 pF AV = −1 TA = 25°C Figure 42 VO − Output Voltage − V INVERTING SMALL-SIGNAL PULSE RESPONSE † VO t − Time − µs 2.5 2.46 2.44 01 0 2 03 0 2.52 2.56 2.58 40 50 VDD = 5 V R L = 10 kΩ C L = 100 pF AV = −1 TA = 25°C 2.48 2.54 Figure 43 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE † VO − Output Voltage − VVO t − Time − µs VDD = 3 V R L = 10 kΩ C L = 100 pF AV = 1 TA = 25°C 0.7 0.68 0.66 0.64 01 02 03 04 05 0 0.72 0.74 0.76 Figure 44 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE † VO − Output Voltage − VVO t − Time − µs 2.5 2.48 2.46 2.44 01 0 2 03 04 05 0 2.54 2.56 2.58 2.52 VDD = 5 V R L = 10 kΩ C L = 100 pF AV = 1 TA = 25°C † For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Gain-Bandwidth Product − kHz GAIN-BANDWIDTH PRODUCT †‡ vs FREE-AIR TEMPERATURE TA − Free-Air Temperature − °C −50 −25 0 25 50 100 75 VDD = 5 V f = 10 kHz R L = 10 kΩ C L = 100 pF 125−75 Figure 50 GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE VDD − Supply Voltage − V Gain-Bandwidth Product − kHz 123 4 5 7 6 R L = 10 kΩ C L = 100 pF TA 25°C Figure 51 om − Phase Margin PHASE MARGIN vs LOAD CAPACITANCE C L − Load Capacitance − pF mφ 75° 60° 45° 30° 15° 101 102 103 104 105 10 kΩ 10 kΩ VDD − VDD + R null C L VI + R null = 0 R null = 1000 Ω R null = 500 Ω TA = 25°C Figure 52 Gain Margin − dB GAIN MARGIN vs LOAD CAPACITANCE C L − Load Capacitance − pF 101 102 103 104 105 R null = 0 R null = 1000 Ω R null = 500 Ω TA = 25°C † Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. ‡ For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are referenced to 1.5 V.

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS − Unity-Gain Bandwidth − kHz UNITY-GAIN BANDWIDTH vs LOAD CAPACITANCE C L − Load Capacitance − pF ÁÁÁ ÁÁÁ 101 102 103 104 105 TA = 25°C 106 Figure 53

APPLICATION INFORMATION

driving large capacitive loads The TLV2211 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figures 51 and 52 illustrate its ability to drive loads up to 600 pF while maintaining good gain and phase margins null = 0). A smaller series resistor (Rnull) at the output of the device (see Figure 54) improves the gain and phase margins when driving large capacitive loads. Figures 51 and 52 show the effects of adding series resistances of 500 Ω and 1000 Ω. The addition of this series resistor has two effects: the first is that it adds a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the output load in the transfer function. The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To calculate the improvement in phase margin, equation 1 can be used. m1 /C0043tan–1 /C04662 ×π× UGB W × R null× C L/C0467 ∆φm1 /C0043improvement in phase margin UGBW /C0043unity-gain bandwidth frequency R null/C0043output series resistance C L /C0043load capacitance (1) Where :

/C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

driving large capacitive loads (continued) The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 54). To use equation 1, UGBW must be approximated from Figure 54. 10 kΩ 10 kΩ VDD− /GND VDD+ R null C L VI Figure 54. Series-Resistance Circuit maximum quiescent IDD of 25 µA. This provides a greater than 90% power efficiency. distortion occurs only when the output signal swings through the point where the load is referenced. 10-kΩ load tied to 2.5 V. The third load condition shows no distortion for a 10-kΩ load tied to 0 V. illustrates the difference seen on the output for a 10-kΩ load and a 100-kΩ load with both tied to 2.5 V.

SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0044 /C0084/C0076/C0086/C0050/C0050/C0049/C0049/C0089 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0076/C0105/C0110/C0067/C0077/C0079/C0083 /C0082/C0065/C0073/C0076/C0262/C0084/C0079/C0262/C0082/C0065/C0073/C0076 /C0077/C0073/C0067/C0082/C0079/C0080/C0079/C0087/C0069/C0082 /C0083/C0073/C0078/C0071/C0076/C0069 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 6) and subcircuit in Figure 54 are generated using the TLV2211 typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity-gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). OUT − + .SUBCKT TLV2211 1 2 3 4 5 C1 11 12 8.86E−12 C2 6 7 50.00E−12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX D P 43D X FB 7 99 POLY (5) VB VC VE VLP + VLN 0 4.29E6 −6E6 6E6 6E6 −6E6 GA 6 0 11 12 9.425E−6 GCM 0 6 10 99 1320.2E−12 ISS 3 10 DC 1.250E−6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3 RD1 60 11 106.1E3 RD2 60 12 106.1E3 R01 8 5 50 R02 7 99 150 RP 3 4 419.2E3 RSS 10 99 160.0E6 VAD 60 4 −.5 VB 9 0 DC 0 VC 3 53 DC .55 VE 54 4 DC .55 VLIM 7 8 DC 0 VLP 91 0 DC 0.1 VLN 0 92 DC 2.6 .MODEL DX D (IS=800.0E−18) .MODEL JX PJF (IS=500.0E−15 BETA=166E−6 + VTO=−.004) .ENDS VDD+ RP IN − IN+ VDD− VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DLP DLN VLNVLP Figure 55. Boyle Macromodel and Subcircuit PSpice and Parts are trademark of MicroSim Corporation.

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2211IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV2211IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

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