Amplifier

TLV2186IDR

Texas Instruments

TLV2186 Precision, Rail-to-Rail Input and Output, 24-V, Zero-Drift Operational Amplifier

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PDF pages: 38

Technical content

Input Common-mode Voltage (V) Input-referred Offset Voltage (µV)

6 V to 24 V

0 V to 5 V

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV2186 SBOS947 –JULY 2019 TLV2186Precision,Rail-to-RailInputandOutput,24-V,Zero-DriftOperationalAmplifier

1 Features

1• High precision: – Offset drift: 0.1 μV/°C – Low offset voltage: 10 μV

Low quiescent current: 90 µA
Excellent dynamic performance: – Gain bandwidth: 750 kHz – Slew rate: 0.35 V/µs
Robust design: – RFI/EMI filtered inputs
Rail-to-rail input/output
Supply range: 4.5 V to 24 V

2 Applications

Precision high-side current sensing
Bridge amplifier
Strain gauge
Temperature measurement
Resistance temperature detector
Weigh scale
Thermal meter
Power supply

3 Description

The TLV2186 is a low-power, 24-V, rail-to-rail input and output zero-drift operational amplifier (op amp). The TLV2186 features only 10 µV of offset voltage (typical) and 0.1 µV/°C of offset voltage drift over temperature (typical). This device is a great choice for precision instrumentation, signal measurement, and active filtering applications. Low quiescent current consumption (90 μA) makes the TLV2186 an excellent option for power-sensitive applications, such as battery-powered instrumentation and portable systems. Moreover, the high common-mode architecture along with low offset voltage allows for high-side current shunt monitoring at the positive rail. This device also provides robust ESD protection during shipment, handling, and assembly. The device is specified for operation from –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV2186 SOIC (8) 4.90 mm × 3.90 mm (1) For all available packages, see the package option addendum at the end of the data sheet. High-Side Current Shunt Monitor Application VOS vs Input Common Mode Voltage

11.3 Receiving Notification of Documentation Updates 30

12 Mechanical, Packaging, and Orderable

4 Revision History

July 2019 * Initial release

5 Pin Configuration and Functions

NAME NO. –IN A 2 I Inverting input channel A +IN A 3 I Noninverting input channel A –IN B 6 I Inverting input channel B +IN B 5 I Noninverting input channel B OUT A 1 O Output channel A OUT B 7 O Output channel B V– 4 — Negative supply V+ 8 — Positive supply

SBOS947 –JULY 2019 www.ti.com Product Folder Links: TLV2186 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability. (2) Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS Supply voltage, VS = (V+) – (V–) 26 V Input voltage Common-mode (V–) –0.5 (V+) + 0.5 V Differential (V+) – (V–) + 0.2 Output short-circuit(2) Continuous TJ Operating junction temperature -40 150 °C Tstg Storage temperature -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS Supply Voltage Single supply 4.5 24 Dual supply ±2.25 ±12 V TA Specified temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLV2186 UNITD (SOIC)

8 PINS

RθJA Junction-to-ambient thermal resistance 129.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.6 °C/W RθJB Junction-to-board thermal resistance 72.8 °C/W ΨJT Junction-to-top characterization parameter 20.8 °C/W ΨJB Junction-to-board characterization parameter 72.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

6.5 Electrical Characteristics

at TA = 25°C, VS = ±2.25V to ±12V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage ±10 ±250 μV dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±0.1 ±1.0 μV/°C PSRR Power-supply rejection ratio TA = –40°C to +125°C ±0.05 ±1 μV/V INPUT BIAS CURRENT IB Input bias current 0.1 0.6 nATA = –40℃ to +85℃ 0.6 TA = –40℃ to +125℃ 5 IOS Input offset current 0.1 1.2 nATA = –40℃ to +85℃ 1.2 TA = –40℃ to +125℃ 2 NOISE Input voltage noise f = 0.1 Hz to 10 Hz 110 nVRMS eN Input voltage noise density f = 1 kHz 38 nV/√Hz iN Input current noise f = 1 kHz 100 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage (V–) – 0.2 (V+) + 0.2 V CMRR Common-mode rejection ratio TA = –40℃ to +125℃ VS = ±2.25 V 108 126 dB VS = ±12 V 110 134 TA = –40℃ to +125℃ VS = ±2.25 V 106 114 VS = ±12 V 106 120 FREQUENCY RESPONSE GBW Gain-bandwidth product 750 kHz SR Slew rate 1-V step, G = 1 0.35 V/μs tS Settling time To 0.1%, 1-V step , G = 1 7.5 μs Overload recovery time VIN × gain > VS 10 μs INPUT CAPACITANCE ZID Differential 100 || 5 MΩ || pF ZICM Common-mode 50 || 2.5 GΩ || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = ±12 V

0.3 V, RL = 10 kΩ 120 140

0.3 V, RL = 10 kΩ, TA =

–40°C to 125°C 120 134

0.65 V, RL = 2 kΩ 120 140

0.65 V, RL = 2 kΩ, TA =

–40°C to 125°C 120 134 OUTPUT VO Voltage output swing from both rails No load 5 20 mV RL = 10 kΩ 60 100 RL = 2 kΩ 340 500 RL = 10 kΩ, TA = –40℃ to +125℃ 90 115 ISC Short-circuit current ±20 mA CLOAD Capacitive load drive See typical curves RO Open-loop output impedance See typical curves POWER SUPPLY IQ Quiescent current per amplifier VS = ±2.25 to ±12 V 90 130 µA TA = –40°C to 125°C 150

6.6 Typical Characteristics

Table 1. Typical Characteristic Graphs

Figure 37. EMIRR vs Frequency Figure 38. Channel Separation

+IN ±IN CHOP1 CHOP2 Notch Filter GM2 GM3 OUT GM_FF GM1 24-V Differential Front End TLV2186 SBOS947 –JULY 2019 www.ti.com Product Folder Links: TLV2186 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TLV2186 operational amplifier combines precision offset and drift with excellent overall performance, making the device a great choice for a wide variety of precision applications. The precision offset drift of only 0.1 µV/°C provides stability over the entire operating temperature range of –40°C to +125°C. In addition, this device offers excellent linear performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. See the Layout Guidelines section for details and a layout example. The TLV2186 is part of a family of zero-drift, MUX-friendly, rail-to-rail output operational amplifiers. This device operates from 4.5 V to 24 V, is unity-gain stable, and is designed for a wide range of general-purpose and precision applications. The zero-drift architecture provides ultra-low input offset voltage and near-zero input offset voltage drift over temperature and time. This choice of architecture also offers outstanding ac performance, such as ultra-low broadband noise, zero flicker noise, and outstanding distortion performance when operating below the chopper frequency.

7.2 Functional Block Diagram

The Functional Block Diagram shows a representation of the proprietary TLV2186 architecture.

7.3 Feature Description

clock feedthrough, EMI rejection, electrical overstress protection and MUX-friendly Inputs.

7.3.1 Rail-to-Rail Inputs

requirements by not requiring headroom over the input signal range. operating voltage or temperature are presented in the Typical Characteristics section.

7.3.2 Phase-Reversal Protection

output limits into the appropriate rail. This performance is shown in Figure 39. Figure 39. No Phase Reversal

7.3.3 Input Bias Current Clock Feedthrough

at the amplifier output is to use a low-pass filter, such as an RC network.

Frequency (Hz) EMIRR IN+ (dB) 100 125 150 175 10M 100M 1G 10G TLV2186 SBOS947 –JULY 2019 www.ti.com Product Folder Links: TLV2186 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Feature Description (continued)

7.3.4 EMI Rejection

The TLV2186 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI interference from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV2186 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 40 shows the results of this testing on the TLV2186. Table 2 lists the EMIRR +IN values for the TLV2186 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com. Figure 40. EMIRR Testing Table 2. TLV2186 EMIRR IN+ for Frequencies of Interest

400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency

900 MHz

applications

52.8 dB

1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band

(1 GHz to 2 GHz) 69.1 dB

2.4 GHz

802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S- band (2 GHz to 4 GHz) 88.9 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 82.5 dB 5 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 95.5 dB

Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the supply or output pins.
The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching EMIRR performance
EMIRR is more simple to measure on noninverting pins than on other pins because the noninverting input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input terminal with no complex interactions from other components or connecting PCB traces. High-frequency signals conducted or radiated to any pin of the operational amplifier may result in adverse effects, as the amplifier would not have sufficient loop gain to correct for signals with spectral content outside the bandwidth. Conducted or radiated EMI on inputs, power supply, or output may result in unexpected dc offsets, transient voltages, or other unknown behavior. Take care to properly shield and isolate sensitive analog nodes from noisy radio signals and digital clocks and interfaces. The EMIRR +IN of the TLV2186 is plotted versus frequency as shown in Figure 40. The TLV2186 unity-gain bandwidth is 750 kHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp bandwidth.

7.3.4.1 EMIRR +IN Test Configuration

isolates the multimeter from residual RF signals that may interfere with multimeter accuracy. Figure 41. EMIRR +IN Test Configuration

7.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. ESD events both before and during product assembly. protection circuitry is then dissipated as heat. device quickly activates and clamps the voltage across the supply rails to a safe level. current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device. (3) Suggested value is approximately 5 kΩ in example overvoltage condition. Figure 42. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

www.ti.com SBOS947 –JULY 2019 Product Folder Links: TLV2186 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Figure 42 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA. If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies V+ or V– are at 0 V. Again, this question depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current-steering diodes. This state is not a normal bias condition; the amplifier most likely does not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If there is any uncertainty about the ability of the supply to absorb this current, external zener diodes must be added to the supply pins, as shown in Figure 42. The zener voltage must be selected such that the diode does not turn on during normal operation. However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level.

7.3.6 MUX-Friendly Inputs

The TLV2186 features a proprietary input stage design that allows an input differential voltage to be applied while maintaining high input impedance. Typically, high-voltage CMOS or bipolar-junction input amplifiers feature antiparallel diodes that protect input transistors from large VGS voltages that may exceed the semiconductor process maximum and permanently damage the device. Large VGS voltages can be forced when applying a large input step, switching between channels, or attempting to use the amplifier as a comparator. The TLV2186 solves these problems with a switched-input technique that prevents large input bias currents when large differential voltages are applied. This solves many issues seen in switched or multiplexed applications, where large disruptions to RC filtering networks are caused by fast switching between large potentials. The TLV2186 offers outstanding settling performance as a result of these design innovations and built-in slew rate boost and wide bandwidth. The TLV2186 can also be used as a comparator. Differential and common-mode Absolute Maximum Ratings still apply relative to the power supplies.

7.4 Device Functional Modes

The TLV2186 has a single functional mode, and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the TLV2186 is 24 V (±12 V).

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV2186 operational amplifier combines precision offset and drift with excellent overall performance, making the device ideal for many precision applications. The precision offset drift of only 0.1 µV/°C provides stability over the entire temperature range. In addition, the device pairs excellent CMRR, PSRR, and AOL dc performance with outstanding low-noise operation. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate. The following application examples highlight only a few of the circuits where the TLV2186 can be used.

8.1.1 Basic Noise Calculations

Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise. Figure 43 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low current noise of the TLV2186 means that the current noise contribution can be neglected. The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations.

(2) For additional resources on noise calculations visit TI Precision Labs. Figure 43. Noise Calculation in Gain Configurations

8.2 Typical Applications

8.2.1 High-Side Current Sensing

Figure 44. High-Side Current Monitor

8.2.1.1 Design Requirements

normal current levels are being maintained, and also provides an alert if an overcurrent condition occurs. beyond each power supply rail allowing for operation at the supply rail. may be applied as well if the sense resistor can be placed between the load and ground.

Single supply: 24 V
Linear output voltage range: 0.3 V to 3.3 V
Iload: 1 A to 11 A The design details and equations below can be used to reconfigure this design for different output voltage ranges and current loads.

8.2.1.2 Detailed Design Procedure

mind while configuring the system. operating range must be taken into consideration.

1 A to 11 A

completely to 0 V, the specified lower swing limit must be observed in the design. difference amplifier operating parameters. minimum current of 1 A corresponds to 300 mV. of 10 mΩ. That value results in a power dissipation of 1 W, and a 0.1-V drop at 10 amps. current range of < 1 A to 11 A, with a VCM very close to the 24-V supply voltage. Figure 45. TLV2186 Configured as a High-Side Current Monitor

0 A to 11 A

sense current drops below 1 A, where VO is 300 mV and less. Figure 46. TLV2186 High-Side Current-Monitor Simulation Schematic continue well below the 300 mV output level. However, keep in mind that the linearity errors are becoming large.

All resistor values are critical for accurate gain results. The resistor pairs of [R1 and R3] and [R2 and R4] must be matched as closely as possible to minimize common-mode mismatch error. Use a 0.1% tolerance, or better. Often, selecting two adjacent resistors on a reel provides close matching compared to random selection.
Keep the closed-loop gain, GA, to which the TLV2186 difference amplifier is set, to a reasonable value. Doing so reduces gain error and can be used to maximize bandwidth. A GA of 30 V/V is used in the example.
Although current monitoring is often used for monitoring dc supply currents, ac current can also be monitored. The –3-dB bandwidth, or upper cutoff frequency, of the circuit of is: where
GBW is the amplifier unity gain bandwidth; 750 kHz for the TLV2186.
Noise gain is equal to the gain as seen looking into the op amp noninverting input, as shown in Equation 5. (4) (5)

normal operation is to be maintained. to 5.25 V. The 3.3-V or 5-V supply used by the ADC could be tapped as a power source.

8.2.1.3 Application Curve

Figure 47. High-Side Results

8.2.2 Bridge Amplifier

file: Bridge Amplifier Circuit. Figure 48. Bridge Amplifier

8.2.3 Low-Side Current Monitor

from 0 V to 10 V. The output range can be adjusted by changing the shunt resistor or gain of the configuration. Click the following link to download the TINA-TI file: Current-Sensing Circuit. Figure 49. Low-Side Current Monitor

8.2.4 RTD Amplifier With Linearization

Figure 50. Click the following link to download the TINA-TI file: RTD Amplifier with Linearization. (1) R5 provides positive-varying excitation to linearize output. Figure 50. RTD Amplifier With Linearization

9 Power Supply Recommendations

regard to operating voltage or temperature.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from connecting dissimilar conductors. Also: – Use low thermoelectric-coefficient conditions (avoid dissimilar metals). – Thermally isolate components from power supplies or other heat sources. – Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information, seeThe PCB is a component of op amp design.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
Place the external components as close as possible to the device. As illustrated in Figure 51, keep the feedback resistor (R3) and gain resistor (R4) close to the inverting input to minimize parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
For best performance, clean the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

1 NC 8 NC

4 V ± 5 NC

10.2 Layout Example

Figure 51. Operational Amplifier Board Layout for Difference Amplifier Configuration

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI™ (Free Software Download)

TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA- TI™ is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels in addition to a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™ ) or TINA-TI™ software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.

11.1.1.2 TI Precision Designs

TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, Zero-drift Amplifiers: Features and Benefits
Texas Instruments, The PCB is a component of op amp design
Texas Instruments, Op Amps for Everyone
Texas Instruments, Operational amplifier gain stability, Part 3: AC gain-error analysis
Texas Instruments, Operational amplifier gain stability, Part 2: DC gain-error analysis
Texas Instruments, Using infinite-gain, MFB filter topology in fully differential active filters
Texas Instruments, Op Amp Performance Analysis
Texas Instruments, Single-Supply Operation of Operational Amplifiers
Texas Instruments, Tuning in Amplifiers
Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes
Texas Instruments, Feedback Plots Define Op Amp AC Performance
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, Analog Linearization of Resistance Temperature Detectors
Texas Instruments, TI Precision Design TIPD102 High-Side Voltage-to-Current (V-I) Converter

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.5 Trademarks

TINA-TI, E2E are trademarks of Texas Instruments. Bluetooth is a registered trademark of Bluetooth SIG, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Aug-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLV2186IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 T2186 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2186IDR SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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Product Information

TLV2186IDR specifications and overview.

Summary

TLV2186 Precision, Rail-to-Rail Input and Output, 24-V, Zero-Drift Operational Amplifier

Description

TLV2186 Precision, Rail-to-Rail Input and Output, 24-V, Zero-Drift Operational Amplifier

Source title TLV2186IDR Datasheet(PDF) - Texas Instruments

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