TLV170 TI | Alldatasheet
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Technical content
Package Footprint Comparison (to Scale) Package Height (to Scale)Comparison D (SO-8) DBV (SOT23-5) Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 TLVx17036-V,Single-Supply,EMI-Hardened,Low-PowerOperationalAmplifiersfor Cost-SensitiveSystems
1 Features
1• Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V
- Low Noise: 22 nV/√Hz
- EMI-Hardened with RFI-Filtered Inputs
- Input Range Includes the Negative Supply
- Unity-Gain Stable: 200-pF Capacitive Load
- Rail-to-Rail Output
- Gain Bandwidth: 1.2 MHz
- Low Quiescent Current: 125 µA per Amplifier
- High Common-Mode Rejection: 110 dB
- Low Bias Current: 10 pA (typical)
2 Applications
- Currency Counters
- AC-DC Converters
- Tracking Amplifiers in Power Modules
- Server Power Supplies
- Inverters
- Test Equipment
- Battery-Powered Instruments
- Transducer Amplifiers
- Line Drivers or Line Receivers Smallest Packaging for 36-V Operational Amplifiers
3 Description
The TLVx170 family of electromagnetic interference (EMI)-hardened, 36-V, single-supply, low-noise operational amplifiers (op amps) have a THD+N of 0.0002% at 1 kHz and can operate on supplies that range from 2.7 V (±1.35 V) to 36 V (±18V). These features, along with low noise and very high power- supply rejection ratio (PSRR), make the single- channel TLV170, dual-channel TLV2170, and quad- channel TLV4170 suitable for use in microvolt-level signal amplification. The TLVx170 family of devices also gives good offset, drift, and bandwidth with low quiescent current. Unlike most op amps that are specified at only one supply voltage, the TLVx170 family of op amps is specified from 2.7 V to 36 V with the ability to swing input signals beyond the supply rails without phase reversal. The TLVx170 family is also unity-gain stable with a 200-pF capacitive load with a 1.2-MHz bandwidth and a 0.4-V/μs slew rate for use in current- to-voltage converters. The device inputs can operate 100 mV below the negative rail and within 2 V of the positive rail for normal operation, and with full rail-to-rail input with reduced performance. The TLVx170 devices are specified from –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV170 SOIC (8) 4.90 mm × 3.91 mm SOT-23 (5) 2.90 mm × 1.60 mm TLV2170 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm TLV4170 SOIC (14) 8.65 mm × 3.91 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.
TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Table of Contents
11.4 Receiving Notification of Documentation Updates 26
12 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (November 2016) to Revision A Page
Table 1. Device Comparison
2±IN 7 V+ 3+IN 6 OUT 4V± 5 NC Not to scale 1OUT 2V± 3+IN 4 ±IN 5 V+ Not to scale TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated
5 Pin Configuration and Functions
TLV170: DBV Package 5-Pin SOT-23 Top View TLV170: D Package 8-Pin SOIC Top View (1) NC indicates no internal connection. Pin Functions: TLV170 PIN I/O DESCRIPTION NAME TLV170 SOT-23 D –IN 4 2 I Negative (inverting) input +IN 3 3 I Positive (noninverting) input NC(1) — 1, 5, 8 — No internal connection (can be left floating) OUT 1 6 O Output V– 2 4 — Negative (lowest) power supply V+ 5 7 — Positive (highest) power supply
2±IN A 7 OUT B 3+IN A 6 ±IN B 4V± 5 +IN B Not to scale TLV170,TLV2170,TLV4170 www.ti.com SBOS782A –NOVEMBER 2016–REVISED MAY 2018 Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated TLV2170: D and DGK Packages 8-Pin SOIC and VSSOP Top View Pin Functions: TLV2170 PIN I/O DESCRIPTION NAME TLV2170 SOIC VSSOP (micro size) –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B V– 4 4 — Negative (lowest) power supply V+ 8 8 — Positive (highest) power supply
2±IN A 13 ±IN D 3+IN A 12 +IN D 4V+ 11 V ± 5+IN B 10 +IN C 6±IN B 9 ±IN C 7OUT B 8 OUT C Not to scale TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated TLV4170: D and PW Packages 14-Pin SOIC and TSSOP Top View Pin Functions: TLV4170 PIN I/O DESCRIPTION NAME SOIC TSSOP –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B –IN C 9 9 I Inverting input, channel C –IN D 13 13 I Inverting input, channel D +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C 10 10 I Noninverting input, channel C +IN D 12 12 I Noninverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C 8 8 O Output, channel C OUT D 14 14 O Output, channel D V– 11 11 — Negative (lowest) power supply V+ 4 4 — Positive (highest) power supply
TLV170,TLV2170,TLV4170 www.ti.com SBOS782A –NOVEMBER 2016–REVISED MAY 2018 Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Short-circuit to ground, one amplifier per package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply voltage, [(V+) – (V−)] 40 VSingle-supply voltage 40 Signal input pin (V−) − 0.5 (V+) + 0.5 Current Signal input pin –10 10 mA Output short-circuit(2) Continuous Temperature Operating, TA –55 150 °CJunction, TJ 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Voltage Supply, VS = (V+) – (V–) 2.7 36 V TA Specified temperature –40 125 °C TA Operating temperature –55 150 °C
TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information: TLV170
THERMAL METRIC(1) TLV170 UNITD (SOIC) DBV (SOT-23)
8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 149.5 245.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 97.9 133.9 °C/W RθJB Junction-to-board thermal resistance 87.7 83.6 °C/W ψJT Junction-to-top characterization parameter 35.5 18.2 °C/W ψJB Junction-to-board characterization parameter 89.5 83.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Thermal Information: TLV2170
THERMAL METRIC(1) TLV2170 UNITD (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 134.3 180 °C/W RθJC(top) Junction-to-case (top) thermal resistance 72.1 55 °C/W RθJB Junction-to-board thermal resistance 60.6 130 °C/W ψJT Junction-to-top characterization parameter 18.2 5.3 °C/W ψJB Junction-to-board characterization parameter 53.8 120 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.6 Thermal Information: TLV4170
THERMAL METRIC(1) TLV4170 UNITD (SOIC) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 93.2 106.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.8 24.4 °C/W RθJB Junction-to-board thermal resistance 49.4 59.3 °C/W ψJT Junction-to-top characterization parameter 13.5 0.6 °C/W ψJB Junction-to-board characterization parameter 42.2 54.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
TLV170,TLV2170,TLV4170 www.ti.com SBOS782A –NOVEMBER 2016–REVISED MAY 2018 Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated (1) The input range can be extended beyond (V+) – 2 V up to V+. See the Typical Characteristics: Table of Graphs and Application and Implementation sections for additional information.
6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VOS Input offset voltage TA = 25°C 0.5 ±2.5 mV dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±2 µV/°C PSRR Power-supply rejection ratio VS = 4 V to 36 V, TA = –40°C to +125°C 90 105 dB Channel separation, dc 5 µV/V INPUT BIAS CURRENT IB Input bias current TA = 25°C ±10 pA TA = –40°C to +125°C ±1 nA IOS Input offset current TA = 25°C ±10 pA TA = –40°C to +125°C ±50 NOISE Input voltage noise f = 0.1 Hz to 10 Hz 2 µVPP en Input voltage noise density f = 100 Hz 27 nV/√Hz f = 1 kHz 22 INPUT VOLTAGE VCM Common-mode voltage range(1) (V–) – 0.1 (V+) – 2 V CMRR Common-mode rejection ratio TA = –40°C to +125°C 100 dB TA = –40°C to +125°C 95 110 INPUT IMPEDANCE Differential 100 || 3 MΩ || pF Common-mode 6 || 3 1012 Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = 36 V, TA = –40°C to +125°C 94 130 dB FREQUENCY RESPONSE GBP Gain bandwidth product 1.2 MHz SR Slew rate G = +1 0.4 V/µs tS Settling time To 0.1%, VS = ±18 V, G = +1, 10-V step 20 µsTo 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step 28 THD+N Total harmonic distortion + noise G = +1, f = 1 kHz, VO = 3 VRMS 0.0002% OUTPUT VO Voltage output swing from rail VRL = 10 kΩ, AOL ≥ 94 dB, ISC Short-circuit current –20 17 mA CLOAD Capacitive load drive See Typical Characteristics: Table of Graphs pF RO Open-loop output resistance f = 1 MHz, IO = 0 A 900 Ω POWER SUPPLY VS Specified voltage range 2.7 36 V IQ Quiescent current per amplifier IO = 0 A, TA = –40°C to +125°C 125 175 µA
6.8 Typical Characteristics: Table of Graphs
Table 2. Characteristic Performance Measurements
6.9 Typical Characteristics
Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage vs Common-Mode Voltage Figure 3. Offset Voltage vs Common-Mode Voltage Figure 4. Input Bias Current vs Temperature Figure 5. Output Voltage Swing vs Output Current Figure 6. CMRR and PSRR vs Frequency
1 V/div
Figure 7. 0.1-Hz to 10-Hz Noise Figure 8. Input Voltage Noise Spectral Density vs Frequency Figure 9. Quiescent Current vs Supply Voltage Figure 10. Open-Loop Gain and Phase vs Frequency Figure 11. Closed-Loop Gain vs Frequency Figure 12. Open-Loop Gain vs Temperature
5 V/div
Figure 13. Open-Loop Output Impedance vs Frequency Figure 14. Small-Signal Overshoot vs Capacitive Load Figure 15. Small-Signal Overshoot vs Capacitive Load Figure 16. No Phase Reversal Figure 17. Small-Signal Step Response (100 mV) Figure 18. Small-Signal Step Response (100 mV)
2 V/div
Figure 19. Large-Signal Step Response Figure 20. Large-Signal Step Response Figure 21. Large-Signal Settling Time Figure 22. Large-Signal Settling Time Figure 23. Short-Circuit Current vs Temperature Figure 24. Maximum Output Voltage vs Frequency
Figure 25. EMIRR IN+ vs Frequency
Input Stage 2nd Stage Output Stage +IN -IN PCH FF Stage OUT Ca Cb TLV170,TLV2170,TLV4170 SBOS782A –NOVEMBER 2016–REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TLVx170 family of op amps provides high overall performance, making the devices ideal for many general- purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire temperature range. In addition, the family offers very good overall performance with high CMRR, PSRR, and AOL.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
operating voltage or temperature are presented in the Typical Characteristics: Table of Graphs section.
7.3.2 Phase-Reversal Protection
voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 26. Figure 26. No Phase Reversal
7.3.3 Electrical Overstress
before and during product assembly. A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. back to the internal power-supply lines, where the diodes meet at an absorption device internal to the op amp. This protection circuitry is intended to remain inactive during normal circuit operation.
current, and any resistance in the input path. supply pins; see Figure 27. Select the Zener voltage so that the diode does not turn on during normal operation. above the safe-operating, supply-voltage level. Figure 27. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
7.3.4 Capacitive Load and Stability
to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. techniques and application circuits. Figure 28. Small-Signal Overshoot vs Capacitive Load Figure 29. Small-Signal Overshoot vs Capacitive Load
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
2 V of the top rail for normal operation. 2 V of the top rail. The typical performance in this range is summarized in Table 3. Table 3. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
7.4.2 Overload Recovery
time. The overload recovery time for the TLVx170 is approximately 2 µs.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
loop gain of the system to ensure the circuit has sufficient phase margin. Figure 30. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
- Supply voltage: 30 V (±15 V)
- Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
- Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
circuit in Figure 30. Not shown in Figure 30 is the open-loop output resistance of the op amp, Ro. 20 dB per decade; see Figure 31. The 1/β curve for a unity-gain buffer is 0 dB.
2 R C
2 R R C
Figure 31. TIPD128 Unity-Gain Amplifier With RISO Compensation Capacitive Load Drive Solution Using an Isolation Resistor precision design. Table 4. Phase Margin versus Overshoot and AC Gain
8.2.3 Application Curve
capacitive loads were determined. The results are shown in Figure 32. Figure 32. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
TLV170,TLV2170,TLV4170 www.ti.com SBOS782A –NOVEMBER 2016–REVISED MAY 2018 Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated
9 Power Supply Recommendations
The TLVx170 is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics: Table of Graphs section. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
- In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than in parallel with the noisy trace.
- Place the external components as close to the device as possible. As illustrated in Figure 34, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 33. Schematic Representation Figure 34. Op Amp Board Layout for a Noninverting Configuration
TLV170,TLV2170,TLV4170 www.ti.com SBOS782A –NOVEMBER 2016–REVISED MAY 2018 Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA-TI™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA- TI™ is a free, fully-functional version of the TINA-TI™ software, preloaded with a library of macromodels in addition to a range of both passive and active models. TINA-TI™ provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI™ offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™ ) or the TINA-TI™ software be installed. Download the free TINA-TI™ software from the TINA-TI™ folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface-mount devices. The evaluation tool uses these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5, and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP adapter EVM can also be used with terminal strips or can be wired directly to existing circuits.
11.1.1.3 Universal Op Amp EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits for a variety of device package types. The evaluation module board design allows many different circuits to be constructed easily and quickly. Five models are offered, with each model intended for a specific package type. PDIP, SOIC, VSSOP, TSSOP, and SOT23 packages are all supported. NOTE These boards are unpopulated, so users must provide their own devices. TI recommends requesting several op amp device samples when ordering the universal op amp EVM.
11.1.1.4 TI Precision Designs
TI precision designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, a complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI precision designs are available online at www.ti.com/ww/en/analog/precision-designs/.
11.1.1.5 WEBENCH® Filter Designer
The WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter designs using a selection of TI op amps and passive components from TI's vendor partners. Available as a web-based tool from the WEBENCH® design center, the WEBENCH® filter designer allows complete multistage active filter solutions to be designed, optimized, and simulated within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
11.3 Related Links
tools and software, and quick access to sample or buy. Table 5. Related Links
11.4 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
solve problems with fellow engineers. contact information for technical support.
11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. DesignSoft is a trademark of DesignSoft, Inc.
11.7 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV170IDBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 14QT TLV170IDBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14QT TLV170IDBVRG4.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R - Call TI Call TI -40 to 125 14QT TLV170IDBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 14QT TLV170IDBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14QT TLV170IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV170 TLV170IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV170 TLV170IDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV170 TLV2170IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU | SN | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 14NV TLV2170IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV2170IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV2170IDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV2170IDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV2170IDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV2170IDRG4.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2170 TLV4170ID Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 125 TLV4170 TLV4170ID.A Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 125 TLV4170 TLV4170IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TLV4170 TLV4170IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TLV4170 TLV4170IDR.B Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TLV4170 TLV4170IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 TLV4170IPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 TLV4170IPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 Addendum-Page 1
www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV4170IPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 TLV4170IPWRG4.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 TLV4170IPWRG4.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV4170 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV170IDBVR SOT-23 DBV 5 3000 208.0 191.0 35.0 TLV170IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV170IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TLV170IDR SOIC D 8 2500 353.0 353.0 32.0 TLV2170IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 TLV2170IDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 TLV2170IDGKT VSSOP DGK 8 250 353.0 353.0 32.0 TLV2170IDR SOIC D 8 2500 353.0 353.0 32.0 TLV2170IDRG4 SOIC D 8 2500 353.0 353.0 32.0 TLV4170IDR SOIC D 14 2500 353.0 353.0 32.0 TLV4170IPWR TSSOP PW 14 2000 353.0 353.0 32.0 TLV4170IPWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TLV4170ID D SOIC 14 50 506.6 8 3940 4.32 TLV4170ID.A D SOIC 14 50 506.6 8 3940 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
0 TYP
1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4) 14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8
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