TLV0834IDG4

TLV0834 TI1 | Alldatasheet

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TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00688-Bit Resolution /C00682.7-V to 3.6-V VCC /C0068Easy Microprocessor Interface or Stand-Alone Operation /C0068Operates Ratiometrically or With VCC Reference /C00684- or 8-Channel Multiplexer Options With Address Logic /C0068Input Range 0 V to VCC With VCC Reference /C0068Remote Operation With Serial Data Link /C0068Inputs and Outputs Are Compatible With TTL and MOS /C0068Conversion Time of 32 ms at f(CLK) = 250 kHz /C0068Functionally Equivalent to the ADC0834 and ADC0838 at 3-V Supply Without the Internal Zener Regulator Network /C0068Total Unadjusted Error . . .±1 LSB

description

These devices are 8-bit successive-approximation analog-to-digital converters, each with an input-configurable multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is readily available from the factory. The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software-configured for single-ended or differential inputs as well as pseudodifferential input assignments. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution. The TLV0834C and TLV0838C are characterized for operation from 0°C to 70°C. The TLV0834I and TLV0838I are characterized for operation from –40°C to 85°C. NC CS CH0 CH1 CH2 CH3 DGTL GND V CC DI CLK SARS DO REF ANLG GND TLV0834 ...D O R N PACKAGE (TOP VIEW) NC CS CH0 CH1 CH2 CH3 DGTL GND NC V CC DI CLK SARS DO REF ANLG GND NC NC – No internal connection TLV0834 . . . PW PACKAGE (TOP VIEW) CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DGTL GND V CC NC CS DI CLK SARS DO SE REF ANLG GND TLV0838 ...P W , D W , O R N PACKAGE (TOP VIEW) AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) SMALL OUTLINE (DW) PLASTIC DIP (N) TSSOP (PW) 0°C to 70°C TLV0834CD TLV0838CDW TLV0834CN TLV0838CN TLV0834CPW TLV0838CPW –40°C to 85°C TLV0834ID TLV0838IDW TLV0834IN TLV0838IN TLV0834IPW TLV0838IPW Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2000, Texas Instruments Incorporated

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

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ODD\\SELECT0 EN MUX Analog STARTSGL\\SELECT1 Circuits To Internal (see Note A) DI CLK CS RD CLK TLC0838 TLC0838 TLC0834 CH7 CH5 CH6 COM CH4 CH3 CH2 CH1 CH0 Comparator SARS CS R Start S CLK CLK Delay Time S R CS DO CS CS D CLK R EOC Register Shift 9-Bit R CLK First LSB Bit 1 Bits 0–7 First MSB Shot One Latch and Logic SAR R CS Bits 0–7 REF Decoder and Ladder EN Flip-Flop functional block diagram NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high. EVEN DIF

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–) polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act differentially with any other channel. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. The common input on the TLV0838 can be used for a pseudodifferential input. In this mode, the voltage on the common input is considered to be the negative differential input for all channel inputs. This voltage can be any reference potential common to all channel inputs. Each channel input can then be selected as the positive differential input. This feature is useful when all analog circuits are biased to a potential other than ground. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is disabled for the duration of the conversion. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low. The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state.

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

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Don’t Care 17 6201267 MSBLSB LSB-First DataMSB-First Data EVENDIF ODD +Sign SGLBit Start MSB MUX Settling Time DI DO CS CLK 21201918141312123456 1 0 1 1 tc Hi-Z Hi-Z TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS CHANNEL NUMBER SGL/DIF ODD/EVEN L L H H L H L H CH0 CH1SELECT BIT 1 L L H H L H L H L L L L H H H H CH2 CH3 TLV0834 H = high level, L = low level, – or + = terminal polarity for the selected input channel

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 sequence of operation (continued) 1SGL ODD Bit SE LSB MSBLSB 765432101267 MSB MUX Settling Time DO LSB Held LSB-First DataMSB-First Data SE Used to Control LSB-First Data Hi-Z Hi-Z tc Don’t Care 765432101267 MSB LSB-First Data MSB-First Data MSB Hi-Z DO SE SARS Hi-Z SELSEL Bit 01EVENDIF DI Bit Start CS Addressing MUX tsu tsu CLK 272625242322212019181716151413121187654321 TLV0838 Sign Bit

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

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TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS SELECTED CHANNEL NUMBER SGL/DIF ODD/EVEN SELECT 0 123 COM SGL/DIF ODD/EVEN 1 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 L L L L + – L L L H +– L L H L +– L L H H +– L H L L – + L H L H –+ L H H L –+ L H H H –+ H L L L + – H L L H +– H L H L +– H L H H +– H H L L + – H H L H +– H H H L +– H H H H + – H = high level, L = low level, – or + = polarity of external input absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC (see clock frequency operating conditions) 2.7 3.3 3.6 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Clock frequency, f(CLK) VCC = 2.7 V 10 250 kHz Clock frequency, f(CLK) VCC = 3.3 V 10 600 kHz Clock duty cycle (see Note 2) 40% 60% Pulse duration, CS high, tw 220 ns Setup time, CS low, SE low, or data valid before CLK↑, tsu 350 ns Hold time, data valid after CLK↑, th 90 ns O perating free air temperature TA C suffix 0 70 °COperating free-air temperature, TA I suffix –40 85 NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the recommended duty-cycle range, the minimum pulse duration (high or low) is 1 ms. electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted) digital section PARAMETER TEST CONDITIONS † C SUFFIX I SUFFIX UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VOH High level output voltage VCC = 3 V, IOH = –360 mA 2.8 2.4 VVOH High-level output voltage VCC = 3 V, IOH = –10 mA 2.9 2.8 V VOL Low-level output voltage VCC = 3 V, IOL = 1.6 mA 0.34 0.4 V IIH High-level input current VIH = 3.6 V 0.005 1 0.005 1 mA IIL Low-level input current VIL = 0 –0.005 –1 –0.005 –1 mA IOH High-level output (source) currentAt VOH , DO = 0 V, TA = 25°C –6.5 –15 –6.5 –15 mA IOL Low-level output (sink) currentA t VOL , DO = VCC , TA = 25°C 8 16 8 16 mA IOZ High-impedance-state output VO = 3.3 V,TA = 25°C 0.01 3 0.01 3 mAIOZ g current (DO or SARS) VO = 0, TA = 25°C –0.01 –3 –0.01 –3 mA C i Input capacitance 5 pF C o Output capacitance 5 pF † All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified). ‡ All typical values are at VCC = 3.3 V, TA = 25°C.

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

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electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted) (continued) analog and converter section PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT –0.05 VIC Common-mode input voltage See Note 3 to VIC g VCC +0.05 On channel VI = 3.3 V 1 II( tdb )Standby input current (see Note 4) Off channel VI = 0 –1 mAII(stdby)Standby input current (see Note 4) On channel VI = 0 –1 mA Off channel VI = 3.3 V 1 ri(REF) Input resistance to REF 1.3 2.4 5.9 kW total device PARAMETER MIN TYP ‡ MAX UNIT ICC Supply current 0.2 0.75 mA † All parameters are measured under open-loop conditions with zero common-mode input voltage. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC . Care must be taken during testing at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of 3.25 V for all variations of temperature and load. 4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is in a high or low steady-state condition. operating characteristics, VCC = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS § MIN TYP MAX UNIT Supply-voltage variation error VCC = 3 V to 3.6 V ± 1/16 ± 1/4 LSB Total unadjusted error (see Note 5) Vref = 3.3 V,TA = MIN to MAX ± 1 LSB Common-mode error Differential mode ± 1/16 ± 1/4 LSB t d Propagation delay time, output data afterMSB-first data C L = 100pF 500 nstpd gy , CLK ↓ (see Note 6) LSB-first data C L = 100pF 200 ns tdi Output disable time DO or SARS after CS↑ C L = 10 pF, R L = 10 kW 80 nstdis O utput disable time, DO or SARS after CS ↑ C L = 100 pF,R L = 2 kW 250 ns tc Conversion time (multiplexer-addressing time not included) 8 clock periods § All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response time.

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NOTE A: CL includes probe and jig capacitance. Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

TLV0834C, TLV0834I, TLV0838C, TLV0838I 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TA – Free-Air Temperature – °C f(CLK) = 250 kHz CS = High VCC = 3.6 V VCC = 3 V 1007550250–25 0.3 0.2 –50 0.1 – Supply Current – mA TLV0831 SUPPLY CURRENT vs FREE-AIR TEMPERATURE CCI VCC = 3.3 V Figure 9 f(CLK) – Clock Frequency – kHz TLV0831 SUPPLY CURRENT vs CLOCK FREQUENCY – Supply Current – mACCI VCC = 3.3 V TA = 25°C 5004003002001000 0.1 0.2 0.3 0.4 0.5 TA – Free-Air Temperature – °C VCC = 3.3 V IOL (DO = 0.4 V) 16.5 15.5 14.5 1007550250–25–50 – Output Current – mA OUTPUT CURRENT vs FREE-AIR TEMPERATURE IO IOL (DO = 3.3 V) –IOH (DO = 0 V) –IOH (DO = 2.4 V) Figure 10

www.ti.com 20-Aug-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV0834CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV0834INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV0834IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0834IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

www.ti.com 20-Aug-2011 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TLV0838CDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV0838CNE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV0838CPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838CPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV0838IPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows:

www.ti.com 20-Aug-2011 Addendum-Page 3 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV0834CDR SOIC D 14 2500 367.0 367.0 38.0 TLV0834CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV0834IDR SOIC D 14 2500 367.0 367.0 38.0 TLV0834IPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV0838CDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV0838CPWR TSSOP PW 20 2000 367.0 367.0 38.0 TLV0838IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLV0838IPWR TSSOP PW 20 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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No TIcomponents areauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersoftheparties have executeda specialagreementspecificallygoverningsuch use. OnlythoseTIcomponents whichTIhas specificallydesignatedas militarygradeor“enhanced plastic”aredesignedand intendedforuse in military/aerospaceapplicationsorenvironments.Buyeracknowledgesand agreesthatany militaryoraerospaceuse ofTIcomponents whichhave not been so designatedissolelyattheBuyer's risk,and thatBuyerissolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIhas specificallydesignatedcertaincomponents whichmeet ISO/TS16949 requirements,mainlyforautomotiveuse.Components which have notbeen so designatedareneitherdesignednorintendedforautomotiveuse;and TIwillnotbe responsibleforany failureofsuch components tomeet such requirements. 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