TLV0832CDR

TLV0831C_14 TI1 | Alldatasheet

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/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C00688-Bit Resolution /C00682.7 V to 3.6 V VCC /C0068Easy Microprocessor Interface or Standalone Operation /C0068Operates Ratiometrically or With VCC Reference /C0068Single Channel or Multiplexed Twin Channels With Single-Ended or Differential Input Options /C0068Input Range 0 V to VCC With VCC Reference /C0068Inputs and Outputs Are Compatible With TTL and MOS /C0068Conversion Time of 32 µs at f(CLK) = 250 kHz /C0068Designed to Be Functionally Equivalent to the National Semiconductor ADC0831 and ADC0832 at 3 V Supply /C0068Total Unadjusted Error . . .± 1 LSB

description

These devices are 8-bit successive-approximation analog-to-digital converters. The TLV0831 has single input channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with standard shift registers or microprocessors. The TLV0832 multiplexer is software configured for single-ended or differential inputs. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution. The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V CC (done internally on the TLV0832). The TLV0831C and TLV0832C are characterized for operation from 0°C to 70°C. The TLV0831I and TLV0832I are characterized for operation from −40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) PLASTIC DIP (P) 0°C to 70°C TLV0831CD TLV0832CD TLV0831CP TLV0832CP −40°C to 85°C TLV0831ID TLV0832ID TLV0831IP TLV0832IP Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CS IN+ IN− GND VCC CLK DO REF TLV0831 ...D O R P PACKAGE (TOP VIEW) CS CH0 CH1 GND VCC /REF CLK DO DI TLV0832 ...D O R P PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  1996, Texas Instruments Incorporated

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram R Start Flip-Flop S CLK CLK Time Delay S R CS DO CS CS D CLK R EOC9-Bit Shift Register CS RCLK First LSB Bit 1 Bits 0−7 First One Shot SAR Logic and Latch REN CS Bits 0−7REF Ladder and Decoder EN Comparator EN Analog MUXCH1/IN− CH0/IN+ SGL/DIF ODD/EVEN StartCLK D Shift Register To Internal Circuits (TLV0832 only) DI CS CLK MSB (TLV0831 only)

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional description The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be assigned a positive (+) or negative (−) polarity. The TLV0831 contains only one differential input channel with fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially, between IN+ and IN−, to the TLV0831 or can be applied to IN+ with IN− grounded as a single ended input. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros. Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor. A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete conversion process. A clock input is then received from the processor. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed by address information. A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input. On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register is disabled for the duration of the conversion. The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state.

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 sequence of operation Don’t Care 17 6201267 MSBLSB LSB-First Data EVENDIF +Sign Bit ODDSGL Start Bit 1765 2 43 MSB DI DO CS tsu CLK 21201918141312123456 1 0 1 1 TLV0832 Hi-Z LSB tconv MSB-First Data MSB Hi-Z DO MUX Settling Time CS CLK 10987654321 tsu tconv TLV0831 Hi-Z MSB-First Data TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE MUX ADDRESS CHANNEL NUMBER SGL/DIF ODD/EVEN CH0 CH1 L H L H L L H H MUX Settling Time H = high level, L = low level, − or + = terminal polarity for the selected input channel (TLV0832 only)

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC (see clock operating conditions) 2.7 3.3 3.6 V High-level input voltage, VIH 2 V Low-level input voltage, VIL 0.8 V Clock frequency, f(CLK) VCC = 2.7 V 250 kHz Clock frequency, f(CLK) VCC = 3.3 V 10 600 kHz Clock duty cycle (see Note 2) 40% 60% Pulse duration, CS high, twH(CS) 220 ns Setup time, CS low or TLV0832 data valid before CLK↑, tsu 350 ns Hold time, TLV0832 data valid after CLK↑, th 90 ns Operating free-air temperature, TA C suffix 0 70 °COperating free-air temperature, TA I suffix −40 85 NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V, f(CLK) = 250 kHz (unless otherwise noted) digital section PARAMETER TEST CONDITIONS † C SUFFIX I SUFFIX UNITPARAMETER TEST CONDITIONS † MIN TYP ‡ MAX MIN TYP ‡ MAX UNIT VOH High-level output voltage VCC = 3 V, I OH = −360 µA 2.8 2.4 VVOH High-level output voltage VCC = 3 V, I OH = −10 µA 2.9 2.8 V VOL Low-level output voltage VCC = 3 V, I OL = 1.6 mA 0.34 0.4 V IIH High-level input current VIH = 3.6 V 0.005 1 0.005 1 µA IIL Low-level input current VIL = 0 −0.005 −1 −0.005 −1 µA IOH High-level output (source) current At VOH , DO= 0 V, TA = 25°C −6.5 −15 −6.5 −15 mA IOL Low-level output (sink) currentAt VOL , DO= 0 V, TA = 25°C 8 −16 8 −16 mA IOZ High-impedance-state outputVO = 3.3 V, T A = 25°C 0.01 3 0.01 3 AIOZ High-impedance-state output current (DO) VO = 0, T A = 25°C −0.01 −3 −0.01 −3 µA C i Input capacitance 5 5 pF C o Output capacitance 5 5 pF † All parameters are measured under open-loop conditions with zero common-mode input voltage. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. analog and converter section PARAMETER TEST CONDITIONS † MIN TYP ‡ MAX UNIT VIC Common-mode input voltage See Note 3 −0.05 to VCC +0.05 V On channel VI = 3.3 V 1 II(stdby)Standby input current (see Note 4) Off channel VI = 0 −1 AII(stdby) Standby input current (see Note 4) On channel VI = 0 −1 µA Off channel VI = 3.3 V 1 ri(REF) Input resistance to REF 1.3 2.4 5.9 kΩ † All parameters are measured under open-loop conditions with zero common-mode input voltage. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. NOTES: 3. When chan nel IN− is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC . Care must be taken during testing at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of 3.25 V for all variations of temperature and load. 4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is in a high or low steady-state conditions. total device PARAMETER MIN TYP ‡ MAX UNIT ICC Supply current TLV0831 0.2 0.75 mAICC Supply current TLV0832 1.5 2.5 mA ‡ All typical values are at VCC = 3.3 V, TA = 25°C.

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operating characteristics VCC = Vref = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT Supply-voltage variation error VCC = 3 V to 3.6 V ±1/16 ±1/4 LSB Total unadjusted error (see Note 5) Vref = 3.3 V, TA = MIN to MAX ±1 LSB Common-mode error Differential mode ±1/16 ±1/4 LSB tpd Propagation delay time, output data after CLK↑ MSB-first data C L = 100 pF 200 500 nstpd output data after CLK↑ (see Note 6) LSB-first data C L = 100 pF 80 200 ns tdis Output disable time, DO after CS↑ C L = 10 pF, RL = 10 kΩ 80 125 nstdis Output disable time, DO after CS↑ C L = 100 pF, RL = 2 kΩ 250 ns tconv Conversion time (multiplexer-addressing time not included) 8 clock periods † All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. 6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response time. LSB-first data applies only to TLV0832.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2 V2 V

Figure 1. TLV0832 Data-Input Timing Figure 2. Data-Output Timing NOTE A: CL includes probe and jig capacitance. Figure 3. Output Disable Time Test Circuit and Voltage Waveforms

/C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0049/C0073 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0067/C0044 /C0084/C0076/C0086/C0048/C0056/C0051/C0050/C0073 /C0051/C0262/C0086/C0079/C0076/C0084 /C0056/C0262/C0066/C0073/C0084 /C0065/C0078/C0065/C0076/C0079/C0071/C0262/C0084/C0079/C0262/C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082/C0083 /C0087/C0073/C0084/C0072 /C0083/C0069/C0082/C0073/C0065/C0076 /C0067/C0079/C0078/C0084/C0082/C0079/C0076 SLAS148 − SEPTEMBER 1996

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS f(CLK) − Clock Frequency − kHzTA − Free-Air Temperature — °C f(CLK) = 250 kHz CS = High VCC = 3.6 V VCC = 3 V 1007550250−25 0.3 0.2 −50 0.1 − Supply Current − mA TLV0831 SUPPLY CURRENT vs FREE-AIR TEMPERATURE TLV0831 SUPPLY CURRENT vs CLOCK FREQUENCY CCI − Supply Current − mACCI VCC = 3.3 V VCC = 3.3 V TA = 25°C 5004003002001000 0.1 0.2 0.3 0.4 0.5 Figure 8 Figure 9 TA − Free-Air Temperature − °C VCC = 3.3 V IOL (DO = 0.4 V) 16.5 15.5 14.5 1007550250−25−50 − Output Current − mA OUTPUT CURRENT vs FREE-AIR TEMPERATURE IO IOL (DO = 3.3 V) −IOH (DO = 0 V) −IOH (DO = 2.4 V) Figure 10

www.ti.com 24-Jan-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TLV0831CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831C TLV0831CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831C TLV0831CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831C TLV0831CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831C TLV0831CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0831CP TLV0831CPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0831CP TLV0831ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831I TLV0831IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831I TLV0831IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831I TLV0831IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0831I TLV0831IP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0831IP TLV0831IPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0831IP TLV0832CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832C TLV0832CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832C TLV0832CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832C TLV0832CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832C TLV0832CP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0832CP

www.ti.com 24-Jan-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TLV0832CPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0832CP TLV0832ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832I TLV0832IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832I TLV0832IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832I TLV0832IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V0832I TLV0832IP ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0832IP TLV0832IPE4 ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type TLV0832IP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 24-Jan-2013 Addendum-Page 3 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV0831CDR SOIC D 8 2500 367.0 367.0 35.0 TLV0831IDR SOIC D 8 2500 367.0 367.0 35.0 TLV0832CDR SOIC D 8 2500 367.0 367.0 35.0 TLV0832IDR SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TLV0832ID TLV0832IP TLV0832CP TLV0832CD TLV0831ID TLV0831IP TLV0831CP TLV0831CD TLV0831CDR TLV0831CPE4 TLV0831IDR TLV0831IDRG4 TLV0831IPE4 TLV0832CDG4 TLV0832CDR TLV0832CDRG4 TLV0832CPE4 TLV0832IDG4 TLV0832IDR TLV0832IDRG4 TLV0832IPE4 TLV0831CDRG4 TLV0831CDG4 TLV0831IDG4