TLS2205

TLS2205 TI | Alldatasheet

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Technical content

0.4-A MOS H-Bridge Power Amplifier – No Crossover Distortion – Precision VCM Control Loop With External Sense Resistor – Internal 8-Bit Control DAC With Four Gain Ranges – Controlled-Velocity Head Retract – Compensation Adjust Terminals for Bandwidth Control – Capability for External Velocity Feedback – Low rDS(on), 2 Total – No External Retract Power Supply Isolation Components Required – Hall- or Back-EMF Commutation Circuitry – 3-Phase Driver With 1.3-A MOS Output – Bipolar or Unipolar Drive Modes – Programmable Frequency-Locked Speed Control Loop – Programmable Start-Up Current – Linear Spindle Current Control – Low rDS(on), 1.3 Total – Sector Data Tachometer Signal Input (Optional) – Speed Sense Tachometer Output – Internal Schottky Diodes for Retract Power Source – Controlled Brake Function SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright 1993, Texas Instruments Incorporated Single-Chip Voice-Coil Motor Driver and Spindle-Motor Driver Precision Dual-Voltage Monitor Operates From Single 5-V Supply LinBiCMOS Technology Low Power Dissipation Internal Overtemperature Shutdown Circuitry Low-Profile 56-Terminal DL Package and 64-Terminal PM Package Available 4-V Reference Buffer System Power-On Reset Monotonic 8-Bit DAC

description

The TLS2205 is a combination voice-coil and spindle-motor driver with voltage monitor integrated circuit. This circuit is designed for small-form-factor, high-performance hard disk drives. The TLS2205 integrates a three-phase brushless dc motor driver with a linear full-bridge voice-coil driver. Additional circuitry is added for power-up and power-down sequencing of the driver amplifiers used for motor speed control. A brake function can be invoked on the spindle motor after the head is in a safe landing zone. External sense resistors are used for precision spindle motor and VCM current monitoring. Automatic head retract is provided for voltage or thermal fault conditions. The TLS2205 operates with only 5 V of supply voltage and has a sleep-mode option for low-power applications. All device functions are controlled from a three-wire serial port. Device packaging is a 56-terminal DL or 64-terminal PM package. Center pins are tied to the die mount tab for improved heat dissipation on both packages. Voice-Coil Motor DriverSpindle-Motor Driver SCLK SDATA SPSZ PORN UV CPOR NC NC AVCC VDD VCMGND VCMA SPNGND SPNGND SPNGND SPNGND VCMB VCMVCC AGND RETOUT RETSET NC RSENP RSENN CMPI CMPO VIVCM VCMREF MTRCLK DVCC AUXIN AUXOUT NC HU HV HW DGND U SPNVCC SPNSNSR2 SPNGND SPNGND SPNGND SPNGND SPNSNSR1 V W CRET REFBUF SPNCOMP CTS VPHASE COMDLY2 COMDLY1 SPNSW CTDRV DL PACKAGE (TOP VIEW) SUBSTRATE GROUND AND HEAT SINK NC –No internal connection LinBiCMOS is a trademark of Texas Instruments Incorporated.

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 752652 1819 HW DGND U U SPNVCC SPNSNSR1 SPNGND SPNGND SPNGND SPNGND SPNSNSR2 V W W CRET REFBUF AVCC NC NC VDD NC NC VCMGND VCMGND VCMGND VCMGND VCMA VCMB VCMVCC AGND RETOUT RETSET 21222324 PM PACKAGE (TOP VIEW) NC AUXIN 63626160596458 CPOR UV PORN SPSZ SDATA SCLK MTRCLK COMDLY1 COMDLY2 VPHASE CTS RSENN CMPI CMPO VIVCM VCMREF CTDRV SPNSW 56555457 2526272829 5352 NC AUXOUT HU 515049 303132 SPNCOMP NC NC HV DV NC NC NC CC RSENP NC –No internal connection

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 functional block diagram 1/2 1/8 Speed Discriminator 8 x 2048 Counts Down Serial Port ID = 0 Port B: Mtr Poles Spin Speed Speed Feedback MUX Up Charge Pump Auxiliary Output MUX Fref Fref Fspn NHphase Fspn#Poles 11 Pclk Ref Spnmode Spnmode Spindle- Control Amps Spindle- Control Logic Hphase NHphase Back-EMF or Hall Commutation VCM Reference 8-Bit DAC VCM Driver Port A: Voltage Monitor Fault Retract Control Fault Upolar Unipolar-Mode Center-Tap Driver VCM Power Amps Fault VCM Current- Sensor Amp 15 V SPNCOMP U V W SPNSNSR1 Comm Gain Control GS1 GS2 GS3 Vdac8 G2-412 2 V AUXIN Vdac Port C: System Control Word SPNSNSR2 VPHASE CTS COMDLY1 COMDLY2 HU HV HW REFBUF VCMREF VCMA VCMB CMPO CMPI RSENP RSENN VIVCM RETOUT RETSET CRET CTDRV MTRCLK SCLK SDATA AUXIN AUXOUT VDD UV CPOR PORN Charge- Pump Voltage Tripler 4 V Phase SCK Padv 20 k 20 k 20 k 20 k 10 k SPSZ AWAKE–Bias Enable AUX1 –MSB Options Control AUX0 –LSB Options Control BEMF GAIN –Gain Switch for Back-EMF Mode BRAKE–Brake Enable VCMENA –Enable VCM/B Outputs SPNMODE–Select Control for SPNCOMP Output COMM–Commutate Spindle Inverter (Start Mode) UPOLAR –Select Spindle Unipolar Run Mode NHALLS–Select Back-EMF Spindle-Commutation Mode START–Spindle Start Mode SPNENA –Enable Spindle Power Amps (x 5) (x 8) SPNMODE SPNSW30 NOTE: Terminal numbers are for the DL package.

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 752654 Terminal Functions TERMINAL I/O DESCRIPTION SUBSYSTEM§ NAME NO.† NO.‡ I/O DESCRIPTION SUBSYSTEM§ AGND 19 14 Analog GND VM AUXIN 54 54 I Spindle-phase commutate input SPN AUXOUT 53 53 O Spindle-system status output SPN AVCC 9 1 I Analog 5-V supply voltage VM CMPI 25 20 I VCM frequency-compensation input VCM CMPO 26 21 O VCM frequency-compensation output VCM COMDLY1 31 26 I Spindle back-EMF commutation delay control input SPN COMDLY2 32 27 O Spindle back-EMF commutation delay control output SPN CPOR 6 62 O Power-on-reset delay capacitor output VM CRET 37 34 O Retract power full-wave-rectifier output VM CTDRV 29 24 O Center-tap pnp drive output SPN CTS 34 29 I Spindle center-tap sense input SPN DGND 48 47 Logic GND SP DVCC 55 55 I Logic power supply voltage SP HU 51 52 I Hall-phase U input SPN HV 50 51 I Hall-phase V input SPN HW 49 48 I Hall-phase W input SPN MTRCLK 56 56 I Spindle-motor reference clock input SPN PORN 4 60 I/O Power-on-reset node, open-drain output/reset input VM REFBUF 36 33 O 4-V reference VCM RETOUT 20 15 O Retract voltage set output VM RETSET 21 16 I Retract voltage set input VM RSENN 24 19 I VCM current-sense negative input VCM RSENP 23 18 I VCM current-sense positive input VCM SCLK 1 57 I Serial input clock SP SDATA 2 58 I/O Serial input/output port SP SPNCOMP 35 30 O Spindle charge-pump filter SPN SPNGND 13, 14, 15, 16, 41, 42, 43, 44 39, 40, 41, 42 Spindle ground SPN SPNSNSR1 40 43 I Spindle-sense-resistor kelvin input SPN SPNSNSR2 45 38 O Spindle-sense-resistor output SPN SPNSW 30 25 O Spindle compensation capacitor switch SPN SPNVCC 46 44 I Spindle-driver supply voltage SPN SPSZ 3 59 I Serial I/O port select. When low, data goes into port. When high, data goes out of port. SP U 47 45, 46 O Spindle-phase U connection SPN UV 5 61 I Undervoltage, power-on-reset voltage sense input VM †56-terminal DL package ‡64-terminal PM package §SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION SUBSYSTEM§ NAME NO.† NO.‡ I/O DESCRIPTION SUBSYSTEM§ V 39 37 O Spindle-phase V connection SPN VCMA 12 11 O VCM driver output A VCM VCMB 17 12 O VCM driver output B VCM VCMGND 11 7, 8, 9, 10 VCM driver supply ground VCM VCMREF 28 23 O VCM voltage reference VCM VCMVCC 18 13 VCM driver supply voltage VCM VDD 10 4 O Charge-pump voltage-tripler output SPN VIVCM 27 22 O VCM current-sense output (VCM = 2 V) VCM VPHASE 33 28 O Spindle-back-EMF-phase voltage SPN W 38 35, 36 O Spindle-phase W connection SPN †56-terminal DL package ‡64-terminal PM package §SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port absolute maximum ratings over operating free-air temperature range (unless otherwise noted)¶ Operating virtual junction temperature, TJ 150 Thermal resistance (DL package):Junction-to-ambient, R JA (see Note 2) 89 Junction-to-case, R JC (see Note 2) 14 Thermal resistance (PM package):Junction-to-ambient, R JA (see Note 2) 71 Junction-to-case, R JC (see Note 2) 14 Operating free-air temperature range 0 C to 70 Storage temperature range –55 C to 125 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250 ¶Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions ” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:1.All voltage values are with respect to ground. 2.The device is mounted on a printed-circuit board with 0.22 square inches of copper connected to the package tabs. DISSIPATION RATING TABLE PACKAGE TA C POWER RATING DERATING FACTOR ABOVE TA = 25 C TA = 70 C POWER RATING DL 1125 mW 9.0 mW/ C 720 mW PM 1125 mW 9.0 mW/ C 720 mW

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 752656 recommended operating conditions MIN NOM MAX UNIT Supply voltage, DVCC, AVCC, SPNVCC, VCMVCC 4.5 5 5.5 V High-level input voltage, V IH SCLK, SDATA, AUXIN, MTRCLK, PORN, 3.5 DVCC+0.3 V Low-level input voltage, V IL ,,,,, HU, HV, HW, SPSZ 1.5 V Setup time, tsu Level change on SDATA or SPSZ before SCLK 25 ns Speed reference clock frequency 1 12 MHz Speed reference clock duty cycle MTRCLK 25% 50% 75% Speed reference clock duration 20.8 41.6 62.5 ns Clock frequency 1 10 MHz Clock duty cycle SCLK 25% 50% 75% Pulse duration, tw 25 50 75 ns Operating free-air temperature, TA 0 70 C Operating virtual junction temperature, T J 0 150 C electrical characteristics over recommended supply voltage range, TA = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output voltage, VOH IO = 5 A 3.5 V Low-level output voltage, VOL IO = 5 A 1.5 V Operating supply current, I CC DVCC AVCC 20 mA Sleep supply current, ICC DVCC, AVCC 3 mA High-level input current, IIH 1 A Low-level input current, I IL –1 A voltage and temperature monitor electrical characteristics over recommended supply voltage range, TA = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power-on-reset voltage 1.21 V Power-on-reset sense bias current UV 100 nA Hysteresis 25 mV Internal power-on-reset threshold voltage, AV CC 4 V Power-on-reset timing voltage CPOR SeeNote4 1.21 V Power-on-reset timing current CPOR See Note 4 A Output voltage PORN IPORN= 1 mA 0.4 0.8 V Output leakage current PORN A Charge-pump voltage-tripler output voltage VDD 12 13 15 V Charge-pump voltage-tripler output voltage load regulation See Note 5 0.25 V/ A Thermal shutdown hysteresis 20 mV Voltage monitor accuracy 10 % Thermal shutdown temperature 160 C NOTES:3.PORN reset timing is time reset = C CPOR (VCPOR/ICPOR). 4.V DD can be used to drive external NMOS switches; however, the effective dc loading should be less than 1

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 voice-coil motor driver electrical characteristics over recommended range of supply voltage, TA = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Total output drain-to-source on-state resistance, 2 rDS(on) VCMA, VCMB 2 3 TotalVCMdrivervoltagedro p IO = 200 mA 0.6 V Total VCM driver voltage drop IO = 400 mA 1.2 V VCM driver voltage drop on retract ICRET = 50 mA, RETSET grounded 1.3 V VCM gain accuracy VCM differential linearity 1.6% Slew rate .05 V/ s Control voltage RETSET 0.7 V Pullup resistance CRET, RETOUT 20 Output voltage 3.88 4 4.12 V Output impedance REFBUF f = 10 kHz 6.1 Source current 7 mA Output voltage VCMREF 1.94 2 2.06 V Clamp voltage CRET See Note 6 9 V NOTE 5:Optional Zener diode may be required on CRET for filtering narrow voltage spikes spindle-motor driver electrical characteristics over recommended supply voltage range, TA = 25 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Total output drain-to-source on-state resistance, rDS(on) U, V, W 1.3 1.6 Source-driver output voltage slew rate 0.07 V/ s Sink-driver output voltage slew rate See Note 7 0.07 V/ s Retract clamp diode forward voltage U, V, W, CRET IRETOUT = 50 mA 0.5 V Center tap driver-output saturation resistance CTDRV See Note 8 150 Speed discriminator count range See Note 9 8 8333 16384 Maximum compensation voltage VCM DAC word = FFhex 4 V Maximum spin compensation voltage RUN MODE 5 V Minimum spin compensation voltage 0.8 V Charge-pump leakage current 3 5 nA Charge-pump output current SPNCOMP A Charge-pump output current matching 1% Spindle-driver start current U, V, W 1.2 A NOTES:6.This slew rate is determined by the percentage of programmed current. 7.CTDRV is an open-drain switch. 8.The typical count (1041) f spindle = 3600 (RPM) at f(MTRCLK) = 1 MHz

0.25 VRDY

Figure 1. Voltage Monitor Circuit Figure 2. Power-On Reset Timing Diagram

landing zone. During a fault condition, the VCM drivers are disabled. Table 1. VCM Gain-Range Scale Truth Table

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 PRINCIPLES OF OPERATION VCM current-loop stability is accomplished using the filter at CMPI and CMPO. This filter has the following transfer function: (Rcmp (Ccmp2+ Cmp1) s + 1) Ccmp2 s (Rcmp Ccmp1 s + 1) where: s is a Laplace operator VCM retract The TLS2205 integrated retract circuit eliminates the need for external power supply isolation devices. The retract mode is triggered by the voltage monitor fault logic signal. The retract power path is coupled from the spindle-motor back-EMF to the RETOUT MOS high-side driver via CRET. After the retract control block has been triggered by a loss of power, the following events occur: 1.The system control logic is reset to the power-up state. All bias is disabled (including V DD); all power outputs are disabled. 2.The retract control circuit locks the VCMB low-side driver on and disables the VCMB high-side driver. 3.The retract control circuit disables the VCMA low- and high-side drivers. 4.RETOUT is enabled, and RETSET is used to control the voltage applied to RETOUT. The spindle back-EMF-mode voltage supplies the energy necessary to retract the VCM (see Figure 3). The energy stored in the capacitor (CV DD) connected to V DD is used to control the RETOUT and VCMB power devices. The value of this capacitor can be calculated based on ~ 2 A of retract-mode discharge current and the time to retract t the VCM. The RETOUT control equation is: VVCMA = Vbe [1 + (Rrset1/Rrset2)] CVDD = 2 A VVCMA where: Vbe is the base-to-emitter junction voltage 0.7 V. Example: Assume: Rrset1= 62 k Rrset2 = 100 k t = 6 ms max Therefore: CVDD = 2 A (5 ms) 0.7 V (1 + 62 k /100 k = 0.009 F 0.01 F t = 0.01 F [0.7 V (1 + 62 k /100 k A = 5.7 ms

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 7526514 PRINCIPLES OF OPERATION back-EMF mode (continued) The transfer function between COMDLY2 and VPHASE is : Vcomdly2 = s (Rcom2 Ccom1) VPHASE [1+s (Rcom1 Ccom1)] [1+ s (Rcom2 Ccom2)] where: s is a Laplace operator The component design procedures include the following: Choose Rcom2 with a value as large as possible to permit small capacitor values. The typical value for Rcom2 is 1 M Calculate Ccom2 so that there is at least 45 of phase shift at the phase frequency where the TLS2205 is switched into the internally commutated mode. The approximate value is 10% of the target frequency. Calculate Rcom1 based on the desired COMDLY2 signal swing at the target frequency. The recommended signal swing is 1.25 V peak. Near the target frequency the integrator function, VCOMDLY2/VPHASE, becomes: VCOMDLY2[Mag] = VPHASE (Rcom1 Ccom2) num motor poles/2) Wmotor VCOMDLY2[Phase] = –90 VPHASE VCOMDLY2 = 0.433 Kb Wmotor sin(Wmotor (Rcom1 Ccom2) num motor poles/2) Wmotor VCOMDLY2 = 0.433 Kb sin(Wmotor (Rcom1 Ccom2) num motor poles/2) The peak value of this function is independent of the frequency. Rcom1 = 0.433 Kb 1.25 Ccom2 Num Motor Poles/2) Choose Ccom1 such that the dc-blocking pole, 1/(Rcom1 Ccom1), occurs at a frequency below the integration pole, 1/(Rcom2 Ccom2). Typically the dc-blocking pole is placed at 1/2 the integration pole. Where: Wmotor = Mechanical frequency of the motor, r/s Kb = Back-EMF constant, V/(r/s) The internal speed-regulation feedback loop then takes control of spindle commutation, and further microprocessor intervention is not required. Figure 5 shows the timing relationships for the spindle-motor-control sequencing in both Hall and back-EMF modes. Internal logic and analog filtering provide the commutation function in the commonly used back-EMF mode. In this mode, VPHASE (the difference between the undriven phase and the center tap voltage) is filtered to generate a signal that determines commutation timing (NHphase).

Figure 5. Spindle-Motor Control Sequencing

8 To VCM

Figure 6. Spindle-Current Control

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17 PRINCIPLES OF OPERATION spindle-speed control The TLS2205 provides a frequency-locked-loop speed-control system. Figure 7 is an illustration of the spindle-speed control loop. This system operates by generating a once-around signal from either Hall or back-EMF state changes. This signal is then divided by either 12 (for 8-pole motor) or 18 (for 12-pole motor) (port B bit 11). This signal is called Fspn. Fspn is a once-around spindle-motor clock. Fspn is compared to a signal that is generated from the MTRCLK (Fref). Fref is generated by dividing the MTRCLK by 16, then dividing again by the value stored in the spindle-reference counter (port B bits 0 –10). The Fref and Fspn signals are compared, and the time domain error is fed to the charge pump every other rotation. The charge-pump output is a speed error signal that is filtered by a PI filter at SPNCOMP. The output of this filter commands the spindle current. The spindle rotation TACH output (Fspn) or the back-EMF commutation clock (NHphase) can be directly measured at AUXOUT. AUXIN can be used to provide an external index signal for motor commutation instead of using the speed feedback circuit. See Table 7 for a description of the spindle-motor operating modes. Spindle rotational speed is calculated from the equation below: fspindle = fMTRCLK/[(16 R) + 1] [Hz] where: R is the value stored in port B bits 0–11 (0 < R < 2047) Spindle-speed regulation 1 / [(8 R) + 1] (%)

1440 Hz @ Fspn = 3600 RPM

Figure 7. Spindle-Control Loop Block Diagram and Timing Waveforms reference counter. Port C is used for system controls.

continuous mode, 8-bit microprocessor format mode, and 16-bit microprocessor format mode. cycle. The SDATA line is the actual serial data input and must be synchronous with the leading edge of SCLK. SPSZ is the serial-port select input and is internally tied low to be synchronous with the leading edge of SCLK. Refer to the TMS320C2x User’s Guide for further details. clock. See Figure 8 for details.

12 Data BitsDevicePort

NOTE:ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data. Figure 8. Serial-Port Burst-Mode Operation

SPSZ line is toggled from high to low every falling edge (16 SCLK cycles). See Figure 9 for details. Figure 9. Serial-Port Continuous-Mode Operation 1.SDATA must change on the leading edge of SCLK. 2.SPSZ must go high after the falling edge of SCLK at the end of byte 1 of the data transmission. 4.SPSZ must stay low until SCLK goes low on the last bit of the second byte of the data transmission. goes high during an invalid bit time, the serial port resets and waits for a valid address. See Figure 10 for details. Figure 10. Serial-Port Microprocessor-Mode Operation NOTE:ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.

1.If ID0 = 0 and ID1 = 0, the TLS2205 is selected (see Table 2) and the rest of the data is processed. 2.PT0 and PT1 determine which port is selected (see Table 3). 3.The 16 bits of data are serially loaded into the serial port register. the spindle motor (see Table 5), and port C controls the device functions (see Table 6). Table 2. Device Select Chip selected 0 0 The TLC2205 serial port is selected. Table 3. Port Selection

Table 4. Port-A Definition (VCM Control)

0 B0 VCM DAC control word LSB

1 B1 VCM DAC control word

2 B2 VCM DAC control word

3 B3 VCM DAC control word

4 B4 VCM DAC control word

5 B5 VCM DAC control word

6 B6 VCM DAC control word

7 B7 VCM DAC control word MSB

8 GR0 VCM gain-control LSB

9 GR1 VCM gain-control MSB

12 PT0 Port-select LSB

13 PT1 Port-select MSB

14 ID0 Device-select LSB

15 ID1 Device-select MSB

Table 5. Port-B Definition (Spindle-Speed Regulator Control Word)

0 R0 Spindle reference-counter LSB 1

1 R1 Spindle reference counter 2

2 R2 Spindle reference counter 4

3 R3 Spindle reference counter 8

4 R4 Spindle reference counter 16

5 R5 Spindle reference counter 32

6 R6 Spindle reference counter 64

7 R7 Spindle reference counter 128

8 R8 Spindle reference counter 256

9 R9 Spindle reference counter 512

10 R10 Spindle reference-counter MSB 1024

11 MTR POLE Spindle-motor pole switch (8 or 12)

Table 6. Port-C Definition (System Control Functions)

0 SPNENA SPN Spindle power-inverter enable

1 START SPN Spindle-operation mode

2 NHALLS SPN No Hall-commutation-mode select

3 UPOLAR SPN Spindle-inverter unipolar select

4 COMM SPN Spindle-inverter advance (no hall mode)

5 SPNMODE SPN Select DAC current-control mode

6 VCMENA VCM VCM power output enable

7 BRAKE SPN Spindle BRAKE enable

8 BEMF GAIN SPN Back-EMF amplifier sense gain

9 AUX0 SYS AUXOUT function select MSB

10 AUX1 SYS AUXOUT function select LSB

11 AWAKE SYS System power enable

12 PT0 SYS Port-select LSB

13 PT1 SYS Port-select MSB

14 ID0 SYS Device-select LSB

15 ID1 SYS Device-select MSB

and power dissipation is maximum. AUX1 is the MSB of the auxiliary logic control functions (see Table 7). AUX0 is the LSB of the auxiliary logic control functions (see Table 7). start the spindle motor in back-EMF mode. implemented after a retract has occurred and the head has reached the head stop. VCMENA enables the VCM output drivers. In the disabled state, the VCM output power amplifier outputs go low. However, the power amplifiers still have dc bias applied and can be enabled in a short period of time.

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 7526524 PRINCIPLES OF OPERATION Port-C system control bit definitions (continued) SPNMODE SPNMODE is used to determine whether the spindle charge pump or DAC is driving the spindle-control amplifiers. When SPNMODE is asserted, the spindle current is controlled by the DAC. COMM The COMM bit is used to commutate the spindle driver in the start mode. For every low-to-high state change, the spindle inverter advances one step. UPOLAR UPOLAR controls the spindle-motor drive mode. When this bit is low, the TLS2205 drives the motor in a standard bipolar mode. When this bit is high, CTDRV is switched low and the internal high-side drivers are disabled. An external pnp transistor can be switched on using CTDRV, and the device operates in the unipolar mode. NHALLS The NHALLS bit controls which commutation mode is used by the spindle-control logic. When this bit is 0, the TLS2205 uses the Hall sense inputs (HU, HV, HW) to directly commutate the spindle motor. When this bit is 1, the TLS2205 switches into the back-EMF commutation mode. The Hall inputs have no meaning in the back-EMF commutation mode. However, the Hall logic inputs determine the motor inverter power-up initial state. The Hall inputs are internally tied low. START This bit controls the spindle-motor driver logic inputs and auxiliary I/O signals (see Table 7). SPNENA The SPNENA bit enables the spindle-motor drivers. The charge-pump control path (SPNCOMP) is not affected by this bit. When this bit is 0, the spindle-motor power drivers are disabled (motor phases U, V, W are Hi-Z) but not powered down. When this bit is 1, the spindle drivers are enabled. AUXIN/AUXOUT functional description Port-C controls (for spindle-motor operation in back-EMF mode) The spindle-motor operation modes are shown in the description section of Table 7. To fully understand this figure, the functional block diagram must be used in conjunction with port C. As an example: 1.To start the drive (START MODE), START (bit 1) = 0, AUX1 (bit 10) = 1, and AUX0 (bit 9) = 1. As a result, Phase is the signal seen on the internal PCLK line, SCK is the signal seen on the internal PADV line, and NHphase is the signal seen at AUXOUT. 2.Once the spindle is spinning at approximately 20% of rated speed, the drive is switched into RUN MODE 0 (START = 0, AUX1 = 0, and AUX0 = 0). As a result, phase is the signal seen on the internal PCLK line and NHphase is the signal seen on the internal PADV line and at AUXOUT. 3.After the spindle reaches operational speed, the drive is switched into RUN MODE 3 (START = 0, AUX1 = 1, AUX0 = 1). As a result, AUXIN is the signal seen on the internal PCLK line, NHphase is the signal seen on the internal PADV line, and Fspn is the signal seen at AUXOUT.

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 25 PRINCIPLES OF OPERATION Table 7. Spindle-Motor Operating Modes 0 0 0 NHphase Phase NHphase RUN MODE0 0 0 1 NHphase AUXIN NHphase RUN MODE1 0 1 0 Fspn Phase NHphase RUN MODE2 0 1 1 Fspn AUXIN NHphase RUN MODE3 1 0 0 Fref AUXIN SCK TEST MODE0 † 1 0 1 Fref AUXIN SCK TEST MODE1 † 1 1 0 Fspn AUXIN SCK TEST MODE2 † 1 1 1 NHphase Phase SCK START MODE †These test modes were developed for internal chip testing. descriptions AUXOUT:The auxiliary logic output multiplexer AUXIN:The auxiliary logic input (can be used to commutate spindle) PCLK:The spindle-speed feedback clock (AUXIN or phase) PADV:The spindle phase-advance clock (back-EMF mode) START:Spindle start mode (from port C, bit 1, 1 = enable) AUX0:Option control (from port C, bit 9) AUX1:Option control (from port C, bit 10) COMM:Commutation via serial port (from port C, bit 4) Fspn:The once-around signal and the frequency of PCLK divided by 12 for an 8 pole motor (bit 11 on port B set low), or divided by 18 for a 12 pole motor (bit 11 on port B set high). Fref:The divided output of the speed-discriminator reference frequency (MTRCLK) Phase:The spindle-control logic output of the spindle even states (see Figure 4, SC 0,2,4) NHphase:No Halls phase is the back-EMF zero-crossing clock Hphase:Halls-phase clock from external Hall sensors SCK:Start clock, AUXIN ORed with COMM (from port C, bit 4) RUN MODE 0:Speed feedback information comes from motor commutation, AUXOUT = NHphase RUN MODE 1:Speed feedback information comes from AUXIN, AUXOUT = NHphase RUN MODE 2:Speed feedback information comes from motor commutation, AUXOUT = Fspn RUN MODE 3:Speed feedback information comes from AUXIN, AUXOUT = Fspn TEST MODE 0:AUXOUT = Fref: Fref = MTRCLK/N; N = value stored in port-B reference counter TEST MODE 1:AUXOUT = Fref: Fref = MTRCLK/(16 N); N = same as above TEST MODE 2:AUXOUT = Fspin: Fspin = AUXIN/12 or 18 depending on number of motor poles (port B, bit 11) START MODE:Spindle commutation is controlled externally via AUXIN

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 7526526

APPLICATION INFORMATION

Lm, Rm C12 1948 55AVCC VCMVCC UV CMPI CMP0 RSENP VCMA VCMB RSENN RETOUT RETSET VCMREF VIVCM HW HV HU REFBUF CPOR VDD VCMGND SPNGND SPNGND SPNGND SPNGND AGND DVCC SPNVCC CRET CTDVR SPNSW SPNCOMP SPNSNSR2 SPNSNSR1 CTS W V U PORN SDATA SPSZ SCLK MTRCLK AUXIN AUXOUT VPHASE COMDLY1 COMDLY2 SPNGND SPNGND SPNGND SPNGND DGND TLS2205 5 V Pin numbers shown are for the DL package; see Table 8 for external component values. VCM C13 Figure 11. Spindle Motor-Driver Application

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 27 45,46 35,36 U V W CTS SPNSNSR1 SPNSNSR2 SPNCOMP SPNSW CTDRV CRET CMPI R10 R2C1 C12 55DVCC SPNVCC PORN SDATA SPSZ SCLK MTRCLK AUXIN AUXOUT VPHASE COMDLY1 COMDLY2 SPNGND SPNGND SPNGND SPNGND DGND AVCC VCMVCC UV HW HV HU REFBUF CPOR VDD VCMGND VCMGND VCMGND VCMGND AGND CMP0 RSENP VCMA VCMB RSENN RETOUT RETSET VCMREF VIVCM 22 Lm, Rm R3R4 TLS2205 5-V VCM SPINDLE-MOTOR DRIVER C11 C10 5 V R7C6 5 V Pin numbers shown are for the PM package; see Table 8 for external component values. C13 Figure 12. Spindle Motor-Driver Application

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 7526528 Table 8. External Components and Approximate Values

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 29 MECHANICAL DATA 4040048/A–07/93 4825 124 A 0.040 (1,02) 0.025 (0,635) TYP PLASTIC SHRINK SMALL-OUTLINE PACKAGEDL/R-PDSO-G PINS DIM 56 0.730 (18,54) (18,29) 0.720 0.630 (16,00) (15,75) 0.6200.370 (9,40)A MIN A MAX (9,65) 0.380 48-PIN SHOWN 0.009 (0,229) 0.005 (0,127) 0.008 (0,203) 0.012 (0,305) 0.420 (10,67) 0.395 (10,03) 0.299 (7,59) 0.291 (7,39) 0.020 (0,51) 0.110 (2,79) 0.095 (2,41) 0.008 (0,203) 0.016 (0,406) (see Note C) NOTES:A.All linear dimensions are in inches (millimeters). B.This drawing is subject to change without notice. C.Leads are within 0.0035 (0,089) radius of true postion at maximum material condition. D.Body dimensions do not include mold flash, protrusion, or gate burr. E.Mold flash, protrusion, or gate burr shall not exceed 0.015 (0,381). F.Lead tips coplanar within 0.004 (0,102). G.Lead length measured from lead top to point 0.010 (0,254) above seating plane.

SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 7526530 MECHANICAL DATA 4040152/A–07/93 0,70 0,30 11,80 12,20 4833 116 Pin # 1 Indicator 10,10 9,90 0,50 TYP 0,00 MIN PLASTIC QUAD FLAT PACKAGEPM/S-PQFP-G64 SQ SQ 7,50 SQ TYP 0,147 0,177 0,14 0,26 1,70 MAX –10 NOTES:A.All linear dimensions are in millimeters. B.This drawing is subject to change without notice. C.Maximum deviation from coplanarity is 0,08 mm. D.Body dimensions do not include mold flash or protrusion.

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