TLS1255

TLS1255 TI1 | Alldatasheet

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Technical content

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Wide Bandwidth ...T y p 100 MHz at −3 dB /C0068Color Saturation Control Features /C0068Digital Level Control (0 V to 4 V) for Contrast, Color, and Brightness /C0068Mixer Function for OSD Applications /C0068Blanking Function for On-Screen Display (OSD) Applications /C0068Fewer Peripheral Components Required /C0068Low-Impedance Output Driver

description

The TLS1255 is a wide-band video preamplifier system intended for high-resolution red-green-blue (RGB) color monitors with color-saturation control features. The saturation of a color refers to the degree of chroma or purity, or the degree of freedom from admixture with white. In addition to the RGB preamplifier function, the TLS1255 provides color-saturation control and gain control at the video system outputs. Each video amplifier (R, G, and B) contains a gain set for adjusting maximum system gain V = 6 dB). The TLS1255 provides a digital level-operated contrast, brightness, color, and gain adjustment. The video-output stages from TLS1255 directly drive CRT power amplifiers. The system has been designed to operate from a 12-V supply with all digital level controls operating over a 0-V to 4-V range to make the interface to serial digital buses possible. The TLS1255 also contains a blanking circuit that clamps the video output voltage to within 0.2 V of ground. The mixer circuit required for the OSD application is also integrated into the TLS1255, which makes the design of video boards and other applications easier. The TLS1255 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. R_OSD_IN G_OSD_IN B_OSD_IN R_VIDEO_IN R_CLAMP_CAP G_VIDEO_IN GND G_CLAMP_CAP B_VIDEO_IN B_CLAMP_CAP VCC1 CONTRAST COLOR CLAMP_GATE OSD_ADJUST R_GAIN_ADJUST R_CLAMP(+) R_VIDEO_OUT G_GAIN_ADJUST V CC2 G_VIDEO_OUT G_CLAMP(+) B_VIDEO_OUT B_GAIN_ADJUST GND BLANKING OSD_BLANKING B_CLAMP(+) N PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  1996, Texas Instruments Incorporated

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TLS1255Y chip information This chip, when properly assembled, displays characteristics similar to the TLS1255. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. NO BACKSIDE METALIZATION 32 1 2 8 2 7 2 6 171615141312 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All VCC terminals must be externally wired together to prevent internal damage during VCC power-on/-off cycles. 2. For operation above 25°C free-air temperature, derate linearly to 1.52 W at the rate of 19 mW/°C.

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 and VCC2 11 12 13 V High-level input voltage range, CLAMP GATE, VIH Clamp comparators off 2.4 5 V Low-level input voltage range, CLAMP GATE, VIL Clamp comparators on 0 0.8 V High-level input voltage range, BLANKING, VIH Blanking circuit inactive 2.4 5 V Low-level input voltage range, BLANKING, VIL Blanking circuit active 0 0.8 V High-level input voltage range, OSD BLANKING, VIH OSD Blanking circuit inactive 2.4 5 V Low-level input voltage range, OSD BLANKING, VIL OSD Blanking circuit active 0 0.8 V Operating free-air temperature, TA 0 70 °C electrical characteristics at 25°C free-air temperature range, CLAMP GATE = COLOR = 0 V; R,G,B CLAMP(+) = 2 V; BLANKING = OSD BLANKING = 4 V; CONTRAST = R, G, B GAIN ADJUST = 4 V; VCC1 = VCC2 = 12 V (unless otherwise noted) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ICC Supply current VCC1 + VCC2 110 130 mA Vref Video input reference voltage Measure R,G,B VIDEO_IN voltage 1.6 1.8 2.1 V IIL CLAMP GATE low input current CLAMP GATE = 0 V −0.5 −8 µA IIH CLAMP GATE high input current CLAMP GATE = 12 V 0.005 1 µA Clamp-capacitor charge currentIK(chg) R,G,B CLAMP CAP = 0 V 850 µA Clamp-capacitor discharge currentIK(dschg) R,G,B CLAMP CAP = 5 V −850 µA VOL Low-level output voltage R,G,B CLAMP CAP = 0 V 0.2 0.6 V VOH High-level output voltage R,G,B CLAMP CAP = 5 V 6.7 7.6 V Video output blanked voltage VO(BLANK) BLANKING = 0 V; R,G,B CLAMP(+) = 3 V 0.2 0.35 V High-level output voltage, OSDVO(OSD BLANK) OSD BLANKING = 0 V, VO(PP)(OSD) = 4 V 0.8 V Output voltage difference VODIFF Between any two channels 50 mV Spot-killer voltage VSPOT VCC adjusted to active 8.2 10.3 V

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operating characteristics at 25°C free-air temperature, CLAMP GATE = COLOR = 0 V; R,G,B CLAMP(+) = 2 V, BLANKING = OSD BLANKING = 4 V; CONTRAST = R,G,B GAIN ADJUST = 4 V; VCC1 = VCC2 = 12 V (unless otherwise noted) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN TYP MAX UNIT AV(max)(CONTRAST) Maximum voltage amplificationAVMAX(cont) CONTRAST = 4 V, COLOR = 0 V, VI(PP) = 700 mV

7.6 V/V

AV(max)(CONTRAST) Maximum voltage amplification AVMAX(cont) CONTRAST = 4 V, COLOR = 4 V, VI(PP) = 700 mV tr(video) Rise time, video output Tr(video) VO(PP) = 4 V 3.5 ns tf(video) Fall time, video output Tf(video) VO(PP) = 4 V 3.5 ns tr(BLANK) Rise time, blank output Tr(BLANK) BLANKING = 0 V, Blanking output VI(PP) = 1 V 7 ns tf(BLANK) Fall time, blank output Tf(BLANK) BLANKING = 0 V, Blanking output VO(PP) = 1 V 7 ns tr(OSD_BLANK) Rise time, OSD blank output Tr(OSD BLANK) OSD_BLANKING = 0 V; OSD_ADJUST = 0 V 7 ns tf(OSD_BLANK) Fall time, OSD blank output Tf(OSD BLANK) OSD_BLANKING = 0 V; OSD_ADJUST = 0 V 7 ns tr(OSD_MIXER) Rise time, OSD mixer Tr(OSD MIXER) OSD_BLANKING = 0 V; VO(PP)(OSD) = 4 V 7 ns tf(OSD_MIXER) Fall time, OSD mixer Tf(OSD MIXER) OSD_BLANKING = 0 V; VO(PP)(OSD) = 4 V 7 ns tpd Propagation delay, Trprop(OSD) OSD_BLANKING = 0 V; VO(PP)(OSD) = 4 V 15 ns tpd Propagation delay, video to OSD MIXER Tfprop(OSD) OSD_BLANKING = 0 V; VO(PP)(OSD) = 4 V 15 ns BW Bandwidth, amplifier bw (−3dB) VO(PP) = 4 V, CLAMP+ = 2 V 100 MHz

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

28R_OSD_IN G_OSD_IN B_OSD_IN R_VIDEO_IN R_CLAMP_CAP G_VIDEO_IN GND G_CLAMP_CAP B_VIDEO_IN B_CLAMP_CAP VCC1 CONTRAST COLOR CLAMP GATE OSD_ADJUST R_GAIN_ADJUST R_CLAMP(+) R_VIDEO_OUT G_GAIN_ADJUST VCC2 G_VIDEO_OUT G_CLAMP(+) B_VIDEO_OUT B_GAIN_ADJUST GND BLANKING OSD BLANKING B_CLAMP(+) 0.1 µF 4.7 µF75 Ω 0.1 µF 4.7 µF75 Ω 0.1 µF0.1 µF 4.7 µF75 Ω 0.1 µF 0.1 µF 4.7 µF0.1 µF 0.1 µF 0.1 µF 0.1 µF 390 Ω 4 V To Blue Cascade Driver 0.1 µF 390 Ω To Green Cascade Driver 0.1 µF 4.7 µF 390 Ω 4 V To Red Cascade Driver 0.1 µF 4 V 0.1 µF

12 VG_VIDEO_IN

R_VIDEO_IN B_VIDEO_IN 12 V 47 µF † Minimum pulse width = 300 ns Figure 1. Application and Test Circuit

/C0084/C0076/C0083/C0049/C0050/C0053/C0053 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 /C0087/C0073/C0084/C0072 /C0079/C0078/C0262/C0083/C0067/C0082/C0069/C0069/C0078 /C0068/C0073/C0083/C0080/C0076/C0065/C0089 /C0040/C0079/C0083/C0068/C0041 /C0077/C0073/C0088/C0069/C0082 SLVS142 − DECEMBER 1996

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.560 (14,22) 0.520 (13,21) 0.610 (15,49) 0.590 (14,99) 524840 0.125 (3,18) MIN 2.390 (60,71) (62,23)(53,09) (51,82) 2.040 2.090 2.450 2.650 (67,31) (65,79) 2.590 0.010 (0,25) NOM 4040053/B 04/95 A 0.060 (1,52) TYP 322824 1.230 (31,24) (32,26) (36,83) (35,81) 1.410 1.4501.270 PINS ** DIM 0.015 (0,38) 0.021 (0,53) A MIN A MAX 1.650 (41,91) (40,89) 1.610 0.020 (0,51) MIN 0.200 (5,08) MAX 0.100 (2,54) M0.010 (0,25) 0°−/C0257 15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-011 D. Falls within JEDEC MS-015 (32 pin only)

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