TLS1233 TI | Alldatasheet
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Technical content
/C0084/C0076/C0083/C0049/C0050/C0051/C0051 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 SLVS126C − JULY 1995 − REVISED JUNE 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Wide Bandwidth ...T y p 100 MHz at −3 dB /C0068Three Channels /C00680 V to 4 V, Digital Level-Contrast Control /C00680 V to 4 V, Digital Level-Gain Adjust Control /C006820-Pin Plastic DIP for Small PCB Area Required /C0068Fewer Peripheral Components Required Than for LM1203 Applications /C0068Independent CLAMP(+) Adjustment to Each Channel
description
The TLS1233 is a 100-MHz wide-band video preamplifier system intended for mid-to-high-resolution RGB (red-green-blue) color monitors. Each video amplifier (R, G, and B) contains a gain set for adjusting maximum system gain (A V = 7.8 V/V). The TLS1233 provides digital level-operated contrast, brightness, and gain adjustment control. All the control inputs offer high input impedance and an operation range from 0 V to 4 V for easy interface to the serial digital buses. Provided in a 20-pin plastic dual-in-line package (DIP), the TLS1233 integrates most of the external components required to accommodate the video system. The TLS1233 operates from a 12-V supply and contains an internal input bias voltage. Also, the TLS1233 contains the feedback resistor required between output and CLAMP(−) for dc level holding. The device is characterized for operation from 0°C to 70°C. functional block diagram Contrast Control VCC2 R VIDEO OUT R CLAMP(+) G VIDEO OUT G CLAMP(+) B VIDEO OUT B CLAMP(+) R VIDEO IN R CLAMP CAP R GAIN ADJUST G VIDEO IN G CLAMP CAP G GAIN ADJUST B VIDEO IN B CLAMP CAP B GAIN ADJUST CONTRAST CLAMP GATE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. R CLAMP(+) VCC1 R VIDEO IN R CLAMP CAP G VIDEO IN GND G CLAMP CAP B VIDEO IN B CLAMP CAP CONTRAST G CLAMP(+) B CLAMP(+) R VIDEO OUT R GAIN ADJUST VCC2 G VIDEO OUT G GAIN ADJUST B VIDEO OUT B GAIN ADJUST CLAMP GATE N PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright 1996, Texas Instruments Incorporated
/C0084/C0076/C0083/C0049/C0050/C0051/C0051 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 SLVS126C − JULY 1995 − REVISED JUNE 1996
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TLS1233Y chip information This chip, when properly assembled, displays characteristics similar to the TLS1233. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. 2 1 20 19 1312111098 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All VCC terminals must be externally wired together to prevent internal damage during VCC power-on/-off cycles. 2. For operation above 25°C free-air temperature, derate linearly from 1.87 W (TA = 25°C) to 1.2 W (TA = 70°C). This equates to a derating factor of 15 mW/°C.
/C0084/C0076/C0083/C0049/C0050/C0051/C0051 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 SLVS126C − JULY 1995 − REVISED JUNE 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC1 and VCC2 11 12 13 V High-level input voltage range, CLAMP GATE, VIH Clamp comparators off 2.4 5 V Low-level input voltage range, CLAMP GATE, VIL Clamp comparators on 0 0.8 V Operating free-air temperature, TA 0 70 °C electrical characteristics at 25°C free-air temperature range, CLAMP GATE = 0 V, CLAMP(+) = 2 V, CONTRAST = R,G,B GAIN ADJUST = 4 V, VCC1 =VCC2 = 12 V (see Figure 2) (unless otherwise noted) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ICC Supply current VCC1 + VCC2 84 94 mA Vref Video input reference voltage Measure R/G/B video input 2.1 2.3 2.5 V II Contrast and R,G,B GAIN ADJUST input current Measure CONTRAST, R/G/B GAIN ADJUST −0.5 -10 µA IIL Clamp gate low input current CLAMP GATE = 0 V −0.5 −2.4 µA IIH Clamp gate high input current CLAMP GATE = 12 V 0.005 1 µA Clamp capacitor charge current IK(chg) R,G,B CLAMP CAP = 0 V 1 mA Clamp capacitor discharge currentIK(dschg) R,G,B CLAMP CAP = 5 V −1 mA VOL Low-level output voltage R,G,B CLAMP CAP = 0 V 0.3 V VOH High-level output voltage R,G,B CLAMP CAP = 5 V 7.8 V VO(diff) Output voltage difference VO(diff) Between any two channels ±0.5 ±50 mV operating characteristics at 25°C free-air temperature, CLAMP GATE = 0 V, CLAMP(+) = 4 V, CONTRAST = R,G,B GAIN ADJUST = 4 V, fI = 10 kHz, VCC1 = VCC2 = 12 V (unless otherwise noted) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN TYP MAX UNIT AV(max) Maximum voltage amplificationAVMAX CONTRAST = 4 V, VIPP = 700 mV 7.8 V/V AV(mid) Midrange voltage amplificationAVMID CONTRAST = 2 V, VIPP = 700 mV 2 V/V Contrast voltage for minimum amplification VCONT-LOW VI(PP) = 1 V, See Note 3 1 V Amplification match at AV(max) AVmax(diff) CONTRAST = 4 V, See Note 4 ±0.2 dB Amplification match at AV(mid) AVmid(diff) CONTRAST = 2 V, See Note 3 ±0.2 dB Amplification match at AV(low) AVlow(diff) CONTRAST = V CONT-LOW , See Note 3 and 4 ±0.2 dB THD Total harmonic distortion CONTRAST = 1 V, VIPP = 1 V 0.5 % BW Amplifier bandwidth BW(−3 dB) CONTRAST = 4 V, See Notes 5 And 7 100 MHz Crosstalk attenuation ax CONTRAST = 4 V, See Note 6 f = 10 kHz, 60 dB Crosstalk attenuation a x CONTRAST = 4 V, f = 10 MHz, See Notes 6 or 7 40 dB Pulse test for rise time tr CONTRAST = 4 V, CLAMP(+) = 2 V, 3 ns Pulse test for fall time tf CONTRAST = 4 V, VO(PP) = 4 V CLAMP(+) = 2 V, See Notes 5 and 7 4 ns NOTES: 3. Determine VCONT-LOW for −40 dB attenuation of output. Reference to AV(max). 4. Measure gain difference between any two amplifiers, VI(PP) = 1 V. 5. Adjust input frequency from 10 kHz (AV(max) reference level) to the −3-dB corner frequency (f −3 dB). VI(PP) = 700 mV. 6. VI(PP) = 700 mV at f = 10 kHz to any amplifier. Measure output levels of the other two undriven amplifiers relative to driven amplifier. 7. A special text fixture without a socket and a double-sided full-ground-plane PC board are required.
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0 V to 4 V
Figure 1. Test Circuit
/C0084/C0076/C0083/C0049/C0050/C0051/C0051 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 SLVS126C − JULY 1995 − REVISED JUNE 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
R CLAMP(+) G CLAMP(+) 0.1 µF VCC1 B CLAMP(+) 0.1 µF10 µF R VIDEO IN R VIDEO OUT 0.1 µF 0.1 µF 10 µF75 Ω 390 Ω R CLAMP CAP R GAIN ADJUST 0.1 µF G VIDEO IN VCC2 0.1 µF 10 µF75 Ω 390 Ω 0.1 µF 10 µF GND G VIDEO OUT 0.1 µF G CLAMP CAP G GAIN ADJUST 0.1 µF B VIDEO IN B VIDEO OUT 0.1 µF 10 µF75 Ω 390 Ω 0.1 µF B CLAMP CAP B GAIN ADJUST 0.1 µF CONTRAST CLAMP GATE 0.1 µF To Red Cascade Driver 12 V To Green Cascade Driver To Blue Cascade Driver CLAMP GATE 12 V R Video In G Video In B Video In CONTRAST 4 V 4 V 4 V 4 V 4 V 4 V 4 V † Minimum pulse width: 300 ns 100 Ω100 Ω Figure 2. Application Circuit
/C0084/C0076/C0083/C0049/C0050/C0051/C0051 /C0086/C0073/C0068/C0069/C0079 /C0080/C0082/C0069/C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082 /C0083/C0089/C0083/C0084/C0069/C0077 SLVS126C − JULY 1995 − REVISED JUNE 1996
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE 0.975 (24,77) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) Seating Plane 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 0.070 (1,78) MAX A 0.035 (0,89) MAX 0.020 (0,51) MIN 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25)
16 PIN SHOWN
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLS1233N Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TLS1233N TLS1233N.A Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 TLS1233N (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TLS1233N N PDIP 20 20 506 13.97 11230 4.32 TLS1233N.A N PDIP 20 20 506 13.97 11230 4.32 Pack Materials-Page 1
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