TLK1501_12 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 32
Technical content
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Hot Plug Protection /C00680.6 to 1.5 Gigabits Per Second (Gbps) Serializer/Deserializer /C0068High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD ) /C00682.5 V Power Supply for Low Power Operation /C0068Programmable Voltage Output Swing on Serial Output /C0068Interfaces to Backplane, Copper Cables, or Optical Converters /C0068Rated for Industrial Temperature Range /C0068On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization /C0068On-Chip PLL Provides Clock Synthesis From Low-Speed Reference /C0068Receiver Differential Input Thresholds 200 mV Minimum /C0068Typical Power: 250 mW /C0068Loss of Signal (LOS) Detection /C0068Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link
description
The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency). The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board. Copyright 2000 − 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued) The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface. The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state. The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock. To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501. The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data. The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from −40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA PowerPAD QUAD FLATPACK (PQFP) −40°C to 85°C TLK1501IRCP −40°C to 85°C TLK1501IRCPR
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VDD RXD3 RXD4 RXD5 RXD6 GND RXD7 RX_CLK RXD8 RXD9 V DD RXD10 RXD11 RXD12 RXD13 GND VDD TXD3 TXD4 TXD5 GND TXD6 TXD7 GTX_CLK V DD TXD8 TXD9 TXD10 GND TXD11 TXD12 TXD13 RXD1 DINRXP 63 62 61 60 5964 58 TXD0 GNDA DOUTTXP DOUTTXN GNDA RREF PRBSEN TESTEN GND RX_ER/PRBS_PASS TXD15 TX_EN LOOPEN TX_ER DD ENABLE LCKREFN 56 55 5457 53 52 TXD14 DINRXN GNDA 51 50 49 RX_DV/LOS RXD15 RXD14 RXD0 RXD2 TXD2 TXD1 GND RCP PACKAGE (TOP VIEW)V DDAV DDAV 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16 Bit
Figure 1. TLK1501 Block Diagram
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL TYPE DESCRIPTIONNAME NO. TYPE DESCRIPTION DINRXN DINRXP I Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a copper or an optical I/F module. DOUTTXN DOUTTXP O Serial transmit outputs (Hi-Z on power up). DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. During power-on reset these terminals are high impedance. ENABLE 24 I Device enable (w/pullup). When this terminal is held low, the device is placed in power-down mode. Only the signal detect circuit on the serial receive pair is active. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation. GND 5, 13, 18, 28, 33, 43 Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers. GNDA 52, 58, Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX. GTX_CLK 8 I Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter interface signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 30 MHz to 75 MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization. LCKREFN 25 I Lock to reference (w/pullup). When LCKREFN is low, the receiver clock is frequency locked to GTX_CLK. This places the device in a transmit only mode since the receiver is not tracking the data. When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS are in a high-impedance state. When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive valid codes from the synchronization state machine before the transmitter is enabled. LOOPEN 21 I Loop enable (w/pulldown). When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBSEN 26 I PRBS test enable (w/pulldown). When asserted high results of pseudorandom bit stream (PRBS) tests can be monitored on the RX_ER/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid PRBS is being received. RREF 56 I Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other side of the resistor is connected to analog VDD . The resistor is used to provide an accurate current reference to the transmitter circuitry. RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 O Receive data bus (Hi-Z on power up). These outputs carry 16-bit parallel data output from the transceiver to the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 13. These terminals are in high-impedance state during power-on reset.
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued) TERMINAL TYPE DESCRIPTIONNAME NO. TYPE DESCRIPTION RX_CLK 41 O Recovered clock (low on power up). Output clock that is synchronized to RXD, RX_ER, RX_DV/LOS. RX_CLK is the recovered serial data rate clock divided by 20. RX_CLK is held low during power-on reset. RX_ER/ PRBS_PASS 29 O Receive error (Hi-Z on power up). When RX_ER and RX_DV/LOS are asserted, indicates that an error was detected somewhere in the frame presently being output on the receive data bus. When RX_ER is asserted and RX_DV/LOS is deasserted, indicates that carrier extension data is being presented. RX_ER is in high-impedance state during power-on reset. When PRBSEN= low (deasserted), this terminal is used to indicate receive error (RX_ER). When PRBSEN = high (asserted), this terminal indicates status of the PRBS test results (High=pass). RX_DV/ LOS 30 O Receive data valid. RX_DV/LOS is output by the transceiver to indicate that recovered and decoded data is being output on the receive data bus. RX_DV/LOS is asserted continously from the first recovered word of the frame through the final recovered word and is deasserted prior to the first rising edge of RX_CLK that follows the final word. RX_DV/LOS is in high-impedance state during power-on reset. If, during normal operation, the differential signal amplitude on the serial receive pins is below 200 mV, RX_DV/LOS is asserted high along with RX_ER and the receive data bus to indicate a loss of signal condition. If the device is in power-down mode, RX_DV/LOS is the output of the signal detect circuit and is asserted low when a loss of signal condition is detected. TESTEN 27 I Test mode enable (w/pulldown). This terminal should be left unconnected or tied low. TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 I Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the transceiver on the rising edge of GTX_CLK as shown in Figure 10. TX_EN 20 I Transmit enable (w/pulldown). TX_EN in combination with TX_ER indicates the protocol device is presenting data on the transmit data bus for transmission. TX_EN must be asserted high with the first word of the preamble and remain asserted while all words to be transmitted are presented on the transmit data bus(TXD). TX_EN must be negated prior to the first rising edge of GTX_CLK following the final word of a frame. TX_ER 22 I Transmit error coding (w/pulldown). When TX_ER and TX_EN are high, indicates that the transceiver generates an error somewhere in the frame presently being transferred. When TX_ER is asserted and TX_EN is deasserted, indicates the protocol device is presenting carrier extension data. When TX_ER is deasserted with TX_EN asserted, indicates that normal data is being presented. VDD 1, 9, 23, 38, Digital logic power. Provides power for all digital circuitry and digital I/O buffers. VDDA 55, 57 Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter
The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the GTX_CLK. valid on the rising edge of the GTX_CLK when the TX_EN is asserted high and the TX_ER is deasserted low. in Figure 2. Detailed timing information can be found in the electrical characteristics table. Figure 2. Transmit Timing Waveform
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly. timing relationship between the transmit data bus, the GTX_CLK and serial transmit terminals. Figure 3. Transmitter Latency and decodes the data such that the user reads and writes actual 16-bit data. error propagation are transmitted as two 10-bit K-codes. Table 1. Transmit Data Controls
comma character is converted to two 10-bit wide code. to a BERT (bit error rate tester), the receiver of another TLK1501, or can be looped back to the receive input. captured and checked for errors by a BERT. to Figure 15 and Figure 16 for termination details. decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock. in Figure 4. Detailed timing information can be found in the switching characteristics table. Figure 4. Receive Timing Waveform
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
the recovered word clock (RX_CLK), and the receive data bus. Figure 5. Receiver Latency converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data. pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. (RX_CLK) and the output is valid on the rising edge of the RX_CLK. synchronization and initialization).
by either a D5.6 (C5) or D16.2 (50) code are output on the RXD terminals. Table 2. Receive Status Signals does not signal an error condition. low. In the power-down condition, the signal detection circuit draws less than 5 mW.
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4 Consecutive Valid Code Words Received
3 Invalid Code
1 Invalid Code
3 Consecutive Valid IDLEs or Carrier Extends,
1 Valid Data or Error Propagation
Figure 6. Initialization and Synchronization State Diagram the link-acquisition state (ACQ). Figure 7. Transmit Side Timing Diagram
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The reference clock (GTX_CLK) is an external input clock that synchronizes the transmitter interface. The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data on both its rising and falling edge, providing a serial data rate that is 20 times the reference clock. operating frequency range The TLK1501 is optimized for operation at a serial data rate of 1.2 Gbps. The TLK1501 may operate at a serial data rate between 0.6 Gbps to 1.5 Gbps. The GTX_CLK must be within ±100 PPM of the desired parallel data rate clock. testability The TLK1501 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled so that an quiescent current test can be performed. The PRBS function allows for a BIST (built-in self-test). loopback testing The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling this terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loopback testing.) built-in self-test (BIST) The TLK1501 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry running at full speed can be realized. The successful completion of the BIST is reported on the RX_ER/PRBS_PASS terminal. power-on reset Upon application of minimum valid power, the TLK1501 generates a power-on reset. During the power-on reset the RXD, RX_ER, and RX_DV/LOS signal terminals to go to a high-impedance state. The RX_CLK is held low. The length of the power-on reset cycle is dependent upon the REFCLK frequency, but is less than 1 ms.
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE TA ≤25/C0095C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25/C0095C TA = 70/C0095C POWER RATING RCP64 § 5.25 W 46.58 mW//C0095C 2.89 W RCP64 ¶ 3.17 W 23.70 mW//C0095C 1.74 W RCP64 # 2.01 W 13.19 mW//C0095C 1.11 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 2 oz. Trace and copper pad with solder. ¶ 2 oz. Trace and copper pad without solder. # Standard JEDEC High-K board. For more information, refer to TI application note PowerPAD Thermally Enhanced Package, TI literature number SLMA002. electrical characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Supply voltage, VDD 2.3 2.5 2.7 V Supply current, ICC VDD = 2.5 V, Frequency = 0.6 Gbps, PRBS pattern 70 mASupply current, ICC VDD = 2.5 V, Frequency = 1.5 Gbps, PRBS pattern 100 mA VDD = 2.5 V, Frequency = 0.6 Gbps, PRBS pattern 175 mW Power dissipation, PD VDD = 2.5 V, Frequency = 1.5 Gbps, PRBS pattern 250 mWPower dissipation, PD VDD = 2.5 V, Frequency = 1.5 Gbps, worst case pattern|| 350 mW Shutdown current Enable = 0, VDDA + VDD terminals = max 2 mA PLL startup lock time VDD ,VDDA = 2.3V, EN ↑ to PLL acquire 0.1 0.4 ms Data acquisition time 1024 bits Operating free-air temperature, TA −40 85 °C ||Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. reference clock (GTX_CLK) timing requirements over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency Minimum data rate Typ−0.01% 30 Typ+0.01% MHz Frequency Maximum data rate Typ−0.01% 75 Typ+0.01% MHz Frequency tolerance −100 ppm Duty cycle 40% 50% 60% Jitter Peak-to-peak 40 ps
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 10. TTL Data Input Valid Levels for ac Measurements
Figure 11. TTL Data Output Valid Levels for ac Measurements
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
† UI is the time interval of one serialized bit. Figure 12. Differential and Common-Mode Output Voltage Definitions
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION PARAMETER TEST CONDITION MIN TYP MAX UNIT Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 21.47 R θJA Junction-to-free-air thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 42.20 °C/W Board-mounted, no air flow, JEDEC test board 75.83 Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 0.38 R θJC Junction-to-case thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 0.38 °C/W Board-mounted, no air flow, JEDEC test board 7.8
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RXD6 GND RXD7 RX_CLK RXD8 RXD9 VDD RXD10 RXD11 RXD12 RXD13 GND TXD3 TXD4 TXD5 GND TXD6 TXD7 GTX_CLK VDD TXD8 TXD9 TXD10 GND TXD11 TXD12 TXD13 RXD1 DINRXP 63 62 61 60 5964 58 TXD0 GNDA DOUTTXP DOUTTXN GNDA DDA RREF PRBSEN TESTEN GND R X_ER/PRBS_PASS TXD15 TX_EN LOOPEN TX_ER V ENABLE LCKREFN 56 55 5457 53 52 TXD14 DINRXN GNDA 51 50 49 RX_DV/LOS RXD15 RXD14 RXD0 RXD2 TXD2 TXD1GND RREF 0.01 µF R t Vt R tR tR t 1 nF − 10 nF 5 Ω at 100 MHz Vt0.01 µF0.01 µF VDD VDDA 0.01 µF 200 Ω 810 Ω Recommended use of 0.01 µF Capacitor per VDD terminal 1 nF − 10 nF VDD VDD RXD3 RXD4 RXD5 DD V DDAV 0.01 µF 1 nF − 10 nF 1 nF − 10 nF Figure 13. External Component Interconnection
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended values of external resistors (1% tolerance) PARAMETER TEST CONDITIONS RECOMMENDED UNIT R (t), Termination resistor 50 Ω environment 50 ΩR (t), Termination resistor 75 Ω environment 75 Ω R (REF), Reference resistor 50 Ω environment 200 ΩR (REF), Reference resistor 75 Ω environment 300 Ω RREF − Resistor Reference − Ω 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 100 150 200 250 300 VOLTAGE vs RESISTOR REFERENCE VODP at 75 Ω VODD at 50 Ω VODD at 75 Ω VODP at 50 Ω VODP or VODD − V Figure 14. Differential Transmitter Voltage I/O directly coupled mode and Figure 16 for high-speed I/O ac-coupled mode.
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V(term) TXP DataData Preemphasis = 21 mA (See Note A) De-Emphasis = 19 mA TRANSMITTER MEDIA RECEIVER V(term) V(term) = VDD Transmission Line Transmission Line NOTE A: This assumes RREF = 200 Ω and termination resistance = 50 Ω. See Figure 14 and section choosing RREF resistor values for more information. Figure 15. High-Speed I/O Directly-Coupled Mode
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 200 Ω 820 Ω DataData Preemphasis = 21 mA (See Note A) De-Emphasis = 19 mA TRANSMITTER MEDIA RECEIVER 0.01 µF 0.01 µF R t R t R t V(term) V(term) V(term) Transmission Line Transmission Line NOTE A: This assumes RREF = 200 Ω and termination resistance = 50 Ω. See Figure 14 and section choosing RREF resistor values for more information. Figure 16. High-Speed I/O AC-Coupled Mode
/C0084/C0076/C0075/C0049/C0053/C0048/C0049 /C0048/C0046/C0054 /C0084/C0079 /C0049/C0046/C0053 /C0071/C0066/C0080/C0083 /C0084/C0082/C0065/C0078/C0083/C0067/C0069/C0073/C0086/C0069/C0082 SLLS428F − JUNE 2000 − REVISED JANUARY 2004
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The TLK1501 is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD to connection etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keep-out area for the 64-pin PFP PowerPAD package is 8 mm X 8 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com. Figure 17. Example of a Thermal Land the exposed PowerPAD using standard reflow soldering techniques. information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLK1501IRCP ACTIVE HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1501IRCPG4 ACTIVE HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1501IRCPR ACTIVE HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1501IRCPRG4 ACTIVE HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-Sep-2007 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK1501IRCPR HVQFP RCP 64 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2
Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,enhancements,improvementsand other changes toitssemiconductorproductsand servicesperJESD46C and todiscontinueany productorserviceperJESD48B. Buyersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.All semiconductorproducts(alsoreferredtohereinas “components”)aresoldsubjecttoTI’s termsand conditionsofsalesuppliedatthetime oforderacknowledgment. TIwarrantsperformanceofitscomponents tothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI’s terms and conditionsofsaleofsemiconductorproducts.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessary tosupportthiswarranty.Exceptwhere mandated by applicablelaw,testingofallparametersofeach component isnotnecessarily performed. TIassumes no liabilityforapplicationsassistanceorthedesignofBuyers’products.Buyersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithBuyers’productsand applications,Buyersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany patentright,copyright,mask work right,or otherintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIcomponents orservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensetouse such productsorservicesora warrantyor endorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofsignificantportionsofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalteration and isaccompaniedby allassociatedwarranties,conditions,limitations,and notices.TIisnotresponsibleorliableforsuch altered documentation.Informationofthirdpartiesmay be subjecttoadditionalrestrictions. ResaleofTIcomponents orserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatcomponent orservice voidsallexpressand any impliedwarrantiesfortheassociatedTIcomponent orserviceand isan unfairand deceptivebusinesspractice. TIisnotresponsibleorliableforany such statements. Buyeracknowledgesand agreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryand safety-relatedrequirements concerningitsproducts,and any use ofTIcomponents initsapplications,notwithstandingany applications-relatedinformationorsupport thatmay be providedby TI.Buyerrepresentsand agreesthatithas allthenecessaryexpertisetocreateand implementsafeguardswhich anticipatedangerousconsequencesoffailures,monitorfailuresand theirconsequences,lessenthelikelihoodoffailuresthatmightcause harm and takeappropriateremedialactions.BuyerwillfullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofany TIcomponents insafety-criticalapplications. Insome cases,TIcomponents may be promotedspecificallytofacilitatesafety-relatedapplications.Withsuch components,TI’s goalisto helpenablecustomerstodesignand createtheirown end-productsolutionsthatmeet applicablefunctionalsafetystandardsand requirements.Nonetheless,such components aresubjecttotheseterms. No TIcomponents areauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersoftheparties have executeda specialagreementspecificallygoverningsuch use. OnlythoseTIcomponents whichTIhas specificallydesignatedas militarygradeor“enhanced plastic”aredesignedand intendedforuse in military/aerospaceapplicationsorenvironments.Buyeracknowledgesand agreesthatany militaryoraerospaceuse ofTIcomponents whichhave not been so designatedissolelyattheBuyer's risk,and thatBuyerissolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIhas specificallydesignatedcertaincomponents whichmeet ISO/TS16949 requirements,mainlyforautomotiveuse.Components which have notbeen so designatedareneitherdesignednorintendedforautomotiveuse;and TIwillnotbe responsibleforany failureofsuch components tomeet such requirements. Products Applications Audio www.ti.com/audio Automotiveand Transportationwww.ti.com/automotive Amplifiers amplifier.ti.com Communicationsand Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP ® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energyand Lighting www.ti.com/energy Clocksand Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com OMAP MobileProcessors www.ti.com/omap TIE2E Community e2e.ti.com WirelessConnectivity www.ti.com/wirelessconnectivity MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2012,Texas InstrumentsIncorporated