TLK1211RCP TI | Alldatasheet

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www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 ETHERNETTRANSCEIVERS Check forSamples: TLK1211RCP 1FEATURES • Advanced 0.25-μm CMOS Technology

  • No ExternalFilterCapacitorsRequired 2• 0.6-Gbpsto1.3-GbpsSerializer/Deserializer
  • Comprehensive SuiteofBuilt-InTestability• Low Power Consumption <250 mW (typ)at 1.25Gbps • IEEE 1149.1JTAG Support
  • FastRelock Times Less Than 256 ns (Typ) • 2.5-VSupply VoltageforLowest Power SuitableforEPON/GEPON Applications Operation
  • LVPECL Compatible DifferentialI/Oon High • 3.3-VToleranton LVTTL Inputs Speed Interface • Hot Plug Protection
  • SingleMonolithicPLL Design • 64-PinVQFP With ThermallyEnhanced
  • Support For 10-BitInterfaceor Reduced Package (PowerPAD ™) Interface5-BitDDR (DoubleData Rate) • CPRI Data Rate Compatible (614Mbps, Clocking 1.22Gbps)
  • ReceiverDifferentialInputThresholds200 mV • IndustrialTemperature Range Minimum Supported:–40°C to85°C
  • IEEE 802.3GigabitEthernetCompliant
  • ANSI X3.230-1994(FC-PH)FibreChannel Compliant

DESCRIPTION

The TLK1211RCP gigabitethernettransceiverprovidesforultrahigh-speed,full-duplex,point-to-pointdata transmissions.Thisdeviceisbased on thetimingrequirementsofthe10-bitinterfacespecificationby theIEEE 802.3 gigabitethernetspecificationand isalsocompliantwiththe ANSI X3.230-1994(FC-PH) fibrechannel standard.The devicesupportsdataratesfrom0.6Gbps to1.3Gbps. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerPAD isa trademarkofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. DESCRIPTION CONTINUED The primaryapplicationof the transceiveris to providebuildingblocksforpoint-to-pointbaseband data transmissionover controlledimpedance media of 50 Ω. The transmissionmedia can be printed-circuitboard traces,coppercables,or fiber-opticalmedia.The ultimaterateand distanceofdatatransferisdependentupon theattenuationcharacteristicsofthemedia and thenoisecouplingtotheenvironment. The transceiverperformsthedataserialization,deserialization,and clockextractionfunctionsfora physicallayer interfacedevice.The transceiveroperatesat1.25Gbps (typical),providingup to1 Gbps ofdatabandwidthover a copperoropticalmedia interface. The transceiversupportsboththedefined10-bitinterface(TBI)and a reduced5-bitinterfaceutilizingdoubledata rate(DDR) clocking.IntheTBI mode theserializer/deserializer(SERDES) accepts10-bitwide 8b/10bparallel encoded data bytes.The paralleldata bytesare serializedand transmitteddifferentiallyat PECL compatible voltagelevels.The SERDES extractsclockinformationfrom theinputserialstreamand deserializesthedata, outputtinga parallel10-bitdatabyte. IntheDDR mode theparallelinterfaceaccepts5-bitwide 8b/10bencoded dataalignedon boththerisingand fallingedges ofthereferenceclock.The dataisclockedmost significantbitfirst(bits0–4 ofthe8b/10bencoded data)on the risingedge of the clockand the leastsignificantbits(bits5–9 of the 8b/10b encoded data)are clockedon thefallingedge oftheclock. The transceiverprovidesa comprehensiveseriesofbuilt-intestsforself-testpurposesincludingloopbackand pseudorandom binarysequence (PRBS) generationand verification.An IEEE 1149.1 JTAG portis also supported. The transceiverishoused ina high-performance,thermallyenhanced,64-pinVQFP PowerPAD package.Use of thePowerPAD package does notrequireany specialconsiderationsexcepttonotethatthePowerPAD, whichis an exposed die pad on the bottom of the device,is a metallicthermaland electricalconductor.Itis recommended thatthedevicePowerPAD be solderedtothethermallandon theboard. The transceiverischaracterizedforoperationfrom–40°C to85°C. power-efficient,dissipatinglessthan250 mW typicalpower when operatingat1.25Gbps. The transceiverisdesignedtobe hotplugcapable.A power-onresetcauses RBC0, RBC1, theparalleloutput signalterminals,TXP, and TXN tobe heldina high-impedancestate. DifferencesBetween TLK1211RCP and TNETE2201 The TLK1211RCP transceiveristhe functionalequivalentof the TNETE2201. There are severaldifferences between thedevicesas notedbelow.See Figure12 intheApplicationInformationsectionforan example ofa typicalapplicationcircuit.

  • The VCC is2.5V fortheTLK1211RCP vs 3.3V forTNETE2201.
  • The PLL filtercapacitorson terminals16, 17, 48, and 49 of the TNETE2201 are no longerrequired.The TLK1211RCP uses theseterminalstoprovideadded testcapabilities.The capacitors,ifpresent,do notaffect theoperationofthedevice.
  • No pulldownresistorsarerequiredon theTXP/TXN outputs.
  • TLK1211RCP has fasterre-locktimecompared totheTLK1201A and TNETE2201B.

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2:1 MUX PRBS Generator

10 Bit

RegistersTD(0-9) PRBSEN LOOPEN Parallel to Serial Phase Generator Clock REFCLK Control Logic MODESEL ENABLE TESTEN Interpolator and Clock ExtractionPRBS Verification Serial to Parallel and Comma Detect Clock RBC1 RBC0 SYNC/PASS RD(0-9) SYNCEN RBCMODE JTAG Control Register JTMS JTRSTN JTDI TCK JTDO 2:1 MUX 2:1 MUX Clock Data TXP TXN RXP RXN LOS TLK1211RCP www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 Table1.AVAILABLE OPTIONS (1) PACKAGE TA PLASTIC QUAD FLAT PACK (RCP) –40°C to85°C TLK1211RCP (1) Forthemost currentpackage and orderinginformation,see the Package OptionAddendum attheend ofthisdocument,orsee the TIwebsiteatwww.ti.com. BLOCK DIAGRAM TerminalFunctions TERMINAL I/O DESCRIPTION NAME NO. SIGNAL MODESEL 15 I Mode select.Thisterminalselectsbetween the10-bitinterfaceand a reduced5-bitDDR P/D(1) interface.When low,the10-bitinterface(TBI)isselected.When pulledhigh,the5-bitDDR mode isselected.The defaultmode istheTBI. LOS 26 O Loss ofsignal.Indicatesa lossofsignalon thehigh-speeddifferentialinputsRXP and RXN. IfthemagnitudeofRXP-RXN > 150 mV, thenLOS = 1 whichisa validinputsignal. IfthemagnitudeofRXP-RXN > 50 mV and < 150 mV, thenLOS isundefined. IfthemagnitudeofRXP-RXN < 50 mV, thenLOS = 0 whichisa lossofsignal. Note:Above LOS conditionsarespecifiedonlyforInputCommon Mode Voltage(RXP+RXN)/2 ≥ 1.25V (1) P/D = Internalpulldown Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TLK1211RCP

SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com TerminalFunctions(continued) TERMINAL I/O DESCRIPTION NAME NO. RBCMODE 32 I Receiveclockmode select.When RBCMODE and MODESEL arelow,half-rateclocksareoutput P/D(1) on RBC0 and RBC1. When MODESEL islowand RBCMODE ishigh,a fullbaud-rateclockis outputon RBC0 and RBC1 isheldlow.When MODESEL ishigh,RBCMODE isignoredand a full baud-rateclockisoutputon RBC0 and RBC1 isheldlow. RBC0 31 O Receivebyteclock.RBC0 and RBC1 arerecoveredclocksused forsynchronizingthe10-bit RBC1 30 outputdataon RD0 –RD9. The operationoftheseclocksisdependentupon thereceiveclock mode selected. Inthehalf-ratemode, the10-bitoutputdatawords arevalidon therisingedges ofRBC0 and RBC1. These clocksareadjustedtohalf-wordboundariesinconjunctionwithsynchronous detect.The clocksarealwaysexpanded duringdatarealignmentand neversliveredortruncated. RBC0 registersbytes1 and 3 ofreceiveddata.RBC1 registersbytes0 and 2 ofreceiveddata. Inthenormalratemode, onlyRBC0 isvalidand operatesat1/10ththeserialdatarate.Data is alignedtotherisingedge. IntheDDR mode, onlyRBC0 isvalidand operatesat1/10ththeserialdatarate.Data isaligned on boththerisingand fallingedges. RD0 –RD9 45,44, O Receivedata.When inTBI mode (MODESEL = low),theseoutputscarry10-bitparalleldata 43,41, outputfromthetransceivertotheprotocollayer.The dataisreferencedtoterminalsRBC0 and 40,39, RBC1, dependingon thereceiveclockmode selected.RD0 isthefirstbitreceived.When inthe 38,36, DDR mode (MODESEL = high),onlyRD0 –RD4 arevalid.RD5 –RD9 areheldlow.The 5-bit 35,34 paralleldataisclockedoutofthetransceiveron therisingedge ofRBC0. REFCLK 22 I Referenceclock.REFCLK isan externalinputclockthatsynchronizesthereceiverand transmitterinterface(60MHz to130 MHz). The transmitteruses thisclocktoregistertheinput data(TD0–TD9) forserialization.IntheTBI mode thatdataisregisteredon therisingedge of REFCLK. IntheDDR mode, thedataisregisteredon boththerisingand fallingedges ofREFCLK withthe most significantbitsalignedon therisingedge ofREFCLK. RXP 54 PECL I Differentialinputreceive.RXP and RXN togetherarethedifferentialserialinputinterfacefroma RXN 52 copperoran opticalI/Fmodule. SYNCEN 24 I Synchronousfunctionenable.When SYNCEN ishigh,theinternalsynchronizationfunctionis P/U(2) activated.When thisfunctionisactivated,thetransceiverdetectstheK28.5comma character (0011111negativebeginningdisparity)intheserialdatastreamand realignsdataon byte boundariesifrequired.When SYNCEN islow,serialinputdataisunframedinRD0 –RD9. SYNC/PASS 47 O Synchronousdetect.The SYNC outputisassertedhighupon detectionofthecomma patternin theserialdatapath.SYNC pulsesareoutputonlywhen SYNCEN isactivated(assertedhigh).In PRBS testmode (PRBSEN = high),SYNC/PASS outputsthestatusofthePRBS testresults (high= pass). TD0 –TD9 2-4,6-9, I Transmitdata.When intheTBI mode (MODESEL = low)theseinputscarry10-bitparalleldata 11-13 outputfroma protocoldevicetothetransceiverforserializationand transmission.This10-bit paralleldataisclockedintothetransceiveron therisingedge ofREFCLK and transmittedas a serialstreamwithTD0 sentas thefirstbit. When intheDDR mode (MODESEL = high)onlyTD0 –TD4 arevalid.The 5-bitparalleldatais clockedintothetransceiveron therisingand fallingedge ofREFCLK and transmittedas a serial streamwithTD0 sentas thefirstbit. TXP 62 PECL Differentialoutputtransmit.TXP and TXN aredifferentialserialoutputsthatinterfacetoa copper TXN 61 O oran opticalI/Fmodule.TXP and TXN areputina high-impedancestatewhen LOOPEN ishigh and areactivewhen LOOPEN islow. TEST ENABLE 28 I When thisterminalislow,thedeviceisdisabledforIddqtesting.RD0 –RD9, RBCn, TXP, and P/U(2) TXN arehighimpedance.The pullupand pulldownresistorson any inputaredisabled.When ENABLE ishigh,thedeviceoperatesnormally. JTDI 48 I Testdatainput.IEEE1149.1(JTAG) P/U(2) JTDO 27 O Testdataoutput.IEEE1149.1(JTAG) JTMS 55 I Testmode select.IEEE1149.1(JTAG) P/U(2) JTRSTN 56 I Resetsignal.IEEE1149.1(JTAG) P/U(2) (2) P/U = Internalpullup

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www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 TerminalFunctions(continued) TERMINAL I/O DESCRIPTION NAME NO. LOOPEN 19 I Loop enable.When LOOPEN ishigh(active),theinternalloop-backpathisactivated.The P/D(3) transmittedserialdataisdirectlyroutedtotheinputsofthereceiver.Thisprovidesa self-test capabilityinconjunctionwiththeprotocoldevice.The TXP and TXN outputsareheldina high-impedancestateduringtheloop-backtest.LOOPEN isheldlowduringstandardoperational statewithexternalserialoutputsand inputsactive. PRBSEN 16 I PRBS enable.When PRBSEN ishigh,thePRBS generationcircuitryisenabled.The PRBS P/D(3) verificationcircuitinthereceivesideisalsoenabled.A PRBS signalcan be fedtothereceive inputsand checkedforerrors,thatarereportedby theSYNC/PASS terminalindicatinglow. TCK 49 I Testclock.IEEE1149.1(JTAG) TESTEN 17 I Manufacturingtestterminal P/D(3) POWER VDD 5,10, Supply Digitallogicpower.Providespower foralldigitalcircuitryand digitalI/Obuffers. 20,23, 29,37, 42,50, VDDA 53,57, Supply Analogpower.VDDA providespower forthehigh-speedanalogcircuits,receiver,and transmitter 59,60 VDDPLL 18 Supply PLL power.Providespower forthePLL circuitry.Thisterminalrequiresadditionalfiltering. GROUND GND 1,14, Ground Digitallogicground.Providesa groundforthelogiccircuitsand digitalI/Obuffers. 21,25, 33,46 GNDA 51,58 Ground Analogground.GNDA providesa groundforthehigh-speedanalogcircuitsRX and TX. GNDPLL 64 Ground PLL ground.Providesa groundforthePLL circuitry. (3) P/D = Internalpulldown DETAILED DESCRIPTION Data Transmission Thisdevicesupportsboththedefined10-bitinterface(TBI)and a reduced5-bitinterfaceutilizingDDR clocking. When MODESEL islow,theTBI mode isselected.When MODESEL ishigh,theDDR mode isselected. In the TBI mode, the transmitterportionregistersincoming10-bitwide data words (8b/10bencoded data, TD0 –TD9) on therisingedge ofREFCLK. The REFCLK isalsoused by theserializer,whichmultipliestheclock by a factorof 10, providinga signalthatisfed to the shiftregister.The 8b/10b encoded data istransmitted sequentiallybits0 through9 overthedifferentialhigh-speedI/Ochannel. IntheDDR mode, thetransmitteraccepts5-bitwide 8b/10bencoded dataon pinsTD0 –TD4. Inthismode, data isalignedtoboththerisingand fallingedges ofREFCLK. The dataisthenformed intoa 10-bitwide word and senttotheserializer.The risingedge REFCLK clocksinbits0–4,and thefallingedge ofREFCLK clocksinbits 5–9.Bit0 isthefirstbittransmitted. TransmissionLatency Data transmissionlatencyisdefinedas thedelayfromtheinitial10-bitword loadtotheserialtransmissionofbit 9. The minimum latencyinTBI mode is20 bittimes.The maximum latencyinTBI mode is22 bittimes.The minimum latencyinDDR mode is30 bittimes,and maximum latencyinDDR mode is32 bittimes. Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TLK1211RCP

TXP, TXN TD(0−9) REFCLK td(Tx latency) 10-Bit Code b9b8b7 b0 b1 b2 b3 Measured 10-Bits td(S) td(S) td(H) td(H) RBC0 RBC1 SYNC RD(0-9) TLK1211RCP SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com Figure1. TransmitterLatency FullRate Mode Data Reception The receiverportiondeserializesthedifferentialserialdata.The serialdataisretimedbased on an interpolated clockgeneratedfrom the referenceclock.The serialdata isthen alignedto the 10-bitword boundariesand presentedtotheprotocolcontrolleralongwithreceivebyteclocks(RBC0 and RBC1). ReceiverClock SelectMode There aretwo modes ofoperationfortheparallelbus:1)the10-bit(TBI)mode and 2)5-bit(DDR) mode. When in TBI mode, thereare two user-selectableclockmodes thatare controlledby the RBCMODE terminal:1) full-rateclockon RBC0 and 2) half-rateclockson RBC0 and RBC1. When inthe DDR mode, onlya full-rate clockisavailableon RBC0; see Table2. Table2.Mode Selection RECEIVE BYTEMODESEL RBCMODE MODE CLOCK 0 0 TBI half-rate 30–65 MHz 0 1 TBI full-rate 60–130 MHz 1 0 DDR 60–130 MHz 1 1 DDR 60–130 MHz Inthehalf-ratemode, two receivebyteclocks(RBC0 and RBC1) are 180 degreesoutofphase and operateat one-halfthe data rate.The clocksare generatedby dividingdown the recoveredclock.The receiveddata is outputwithrespectto the two receivebyteclocks(RBC0 and RBC1) allowinga protocoldeviceto clockthe parallelbytesusingtheRBC0 and RBC1 risingedges.The outputstotheprotocoldevice,byte0 ofthereceived dataisvalidon therisingedge ofRBC1. See thetimingdiagramshown inFigure2. Figure2. Synchronous Timing CharacteristicsWaveforms (TBIHalf-RateMode) Inthenormal-ratemode, onlyRBC0 isused and operatesatfulldatarate(thatis,1.25-Gbpsdatarateproduces a 125-MHz clock).The receiveddata isoutputwithrespectto the risingedge of RBC0. RBC1 islow inthis mode. See thetimingdiagramshown inFigure3.

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td(H)td(S) RBC0 SYNC RD(0-9) K28.5 DXX.X td(S) td(H) td(S) td(H) Bits 0-4 Bits 5-9 RBC0 SYNC RD(0-4) TLK1211RCP www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 Figure3. Synchronous Timing CharacteristicsWaveforms (TBIFull-RateMode) Inthedoubledataratemode, thereceiverpresentsthedataon boththerisingand fallingedges ofRBC0. RBC1 islow impedance.The dataisclockedbit0 first,and alignedtotherisingedge ofRBC0. See thetimingdiagram shown inFigure4. Figure4. Synchronous Timing CharacteristicsWaveforms (DDR Mode) The receiverclockinterpolatorcan locktotheincomingdatawithouttheneed fora lock-to-referencepreset.The receivedserialdatarate(RXP and RXN) isatthesame baud rateas thetransmitteddatastream,±0.02% (200 PPM) forproperoperation(seetherecommended operatingtables). ReceiverWord Alignment This deviceuses the IEEE 802.3 gigabitethernetdefined10-bitK28.5 character(comma character)word alignmentscheme. The followingsectionsexplainhow thisscheme worksand how itrealignsitself. Comma Characteron Expected Boundary This deviceprovides10-bitK28.5 characterrecognitionand word alignment.The 10-bitword alignmentis enabledby forcingthe SYNCEN terminalhigh.Thisenablesthe functionthatexamines and compares serial inputdatatothe7-bitsynchronizationpattern.The K28.5 characterisdefinedby 8-bit/10-bitcodingscheme as a patternconsistingof 0011111010 (a negativenumber beginningwithdisparity)withthe 7 MSBs (0011111), referredtoas thecomma character.The K28.5 characterwas implementedspecificallyforaligningdatawords. As longas the K28.5 characterfallswithinthe expected10-bitboundary,the received10-bitdata isproperly alignedand datarealignmentisnotrequired.Figure2 shows thetimingcharacteristicsofRBC0, RBC1, SYNC, and RD0 –RD9 whilesynchronized.(Note:theK28.5characterisvalidon therisingedge ofRBC1.) Comma CharacterNot on Expected Boundary Ifsynchronizationisenabledand a K28.5 characterstraddlesthe expected10-bitword boundary,then word realignmentisnecessary.Realignmentorshiftingthe10-bitword boundarytruncatesthecharacterfollowingthe misalignedK28.5,butthefollowingK28.5 and allsubsequentdataisalignedproperlyas shown inFigure5.The RBC0 and RBC1 pulsewidthsarestretchedorstalledintheircurrentstateduringrealignment.Withthisdesign, themaximum stretchthatoccursis20 bittimes.Thisoccursduringa worstcase scenariowhen theK28.5 is alignedtothefallingedge ofRBC1 insteadoftherisingedge.Figure5 shows thetimingcharacteristicsofthe datarealignment. Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TLK1211RCP

31 Bit

Misaligned K28.5 Misalignment Corrected INPUT DA TA RBC0 RBC1 RD(0-9) SYNC Corrupt Data

30 Bit

Times (Max) RXP , RXN RD(0−9) RBC0 10-Bit Code td(Rx latency) 10-Bit Code b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 TLK1211RCP SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com Figure5. Word Realignment Timing CharacteristicsWaveforms Systems thatdo notrequireframeddatamay disablebytealignmentby tyingSYNCEN low. When a SYNC characterisdetected,theSYNC signalisbroughthighand isalignedwiththeK28.5 character. The durationoftheSYNC pulseisequaltothedurationofthedatawhen inTBI mode. When inDDR mode the SYNC pulseispresentfortheentireRBC0 period. Data ReceptionLatency The serial-to-paralleldatalatencyisthetimefromwhen thefirstbitarrivesatthereceiveruntilitisoutputinthe alignedparallelword withRD0 receivedas firstbit.The minimum latencyinTBI mode is18 bittimes,and the maximum latencyis24 bittimes.The minimum latencyinDDR mode is17 bittimesand maximum latencyis23 bittimes. Figure6. ReceiverLatency -TBI Normal Mode Shown Loss ofSignalDetection Thisdevicehas a loss-of-signal(LOS) detectioncircuitforconditionswhere theincomingsignalno longerhas sufficientvoltageleveltokeep theclockrecoverycircuitinlock.The LOS isintendedtobe an indicationofgross signalerrorconditions,such as a detachedcableorno signalbeingtransmitted,and notan indicationofsignal codinghealth.Under a PRBS serialinputpattern,LOS ishighforsignalamplitudesgreaterthan150 mV. The LOS islowforallamplitudesbelow50 mV. Between 50 mV and 150 mV, LOS isundetermined.

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www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 Testability The loopbackfunctionprovidesforat-speedtestingofthetransmit/receiveportionsofthecircuitry.The enable functionallowsforallcircuitryto be disabledso thatan Iddq testcan be performed.The PRBS functionalso allowsfora BIST (built-inselftest).The terminalsetting,TESTEN high,enablesthe testmode. The terminal TESTEN has an internalpulldownresistor,so itdefaultsto normal operation.The TESTEN isonlyused for factorytesting,and isnotintendedforend-usercontrol. Loopback Testing The transceivercan providea self-testfunctionby enabling(settingLOOPEN tohighlevel)theinternalloopback path.Enablingthisfunctioncauses serialtransmitteddata to be routedinternallyto the receiver.The parallel dataoutputcan be compared totheparallelinputdataforfunctionalverification.The externaldifferentialoutput isheldina high-impedancestateduringtheloopbacktesting. Enable Function When heldlow,ENABLE disablesallquiescentpower inboth the analogand digitalcircuitry.Thisallowsan ultralow-poweridlestatewhen thelinkisnotactive. PRBS Function Thisdevicehas a built-in27–1 PRBS function.When the PRBSEN controlbitissethigh,the PRBS testis enabled.A PRBS isgeneratedand fedintothe10-bitparalleltransmitterinputbus.Data fromthenormalparallel inputsourceisignoredduringPRBS testmode. The PRBS patternisthenfedthroughthetransmitcircuitryas if itwere normaldataand sentouttothetransmitter.The outputcan be senttoa biterrorratetester(BERT) orto the receiverof anotherTLK1211RCP. Since the PRBS is not reallyrandom and is reallya predetermined sequence of1s and 0s,thedatacan be capturedand checked forerrorsby a BERT. Thisdevicealsohas a built-inBERT functionon thereceiversidethatisenabledby PRBSEN. Itcan receivea PRBS patternand check forerrors,and then reportsthe errorsby forcingthe SYNC/PASS terminallow.When PRBS is enabled, RBCMODE isignored.MODESEL must be low forthe PRBS verifierto functioncorrectly.The PRBS testing supportstwo modes (normaland latched),which are controlledby theSYNCEN input.When SYNCEN islow, theresultofthePRBS biterrorratetestispassed totheSYNC/PASS terminal.When SYNCEN ishightheresult of the PRBS verificationislatchedon the SYNC/PASS output(thatis,a singlefailureforcesSYNC/PASS to remainlow). JTAG The TLK1211 supportsan IEEE1149.1 JTAG functionwhilemaintainingcompatibilitywiththeindustrystandard 64 pinQFP package footprint.Inthisway, theTLK1211 installedon a board layoutthatwas designedforthe industrystandardfootprintsuch as fortheTNETE2201B. (Providedthesupplyvoltagecan be programmed from theolder3.3V to2.5V.)The JTAG pinson theTLK1211 arechosen toeitherbe on the‘vender-unique’ pinsof theindustrystandardfootprint,or are on pinsthatwere previouslypower or ground.The TRSTN pinhas been placedon pin56,whichisa groundon theindustrystandardfootprint.Inthisway, a TLK1211 installedontothe olderfootprinthas theJTAG tapcontrollerheldinreset,and thusdisabled.IftheJTAG functionisdesired,then the5 JTAG pinsTRSTN, TMS, TCK, TDI,and TDO can be used intheusualmanner fora JTAG function.Ifthe JTAG functionisnotdesired,thenconnectingTRSTN toground isrecommended. TMS and TDI have internal pullupresistors,and can thusbe leftunconnectedifnotused.TDO isan outputand shouldbe leftunconnected ifJTAG isnotused.TCK does nothave an internalpullup,and can be tiedtoGND orPWR ifnotused,butwith TRSTN low,thisinputisnotused,and thuscan be leftunconnected. Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TLK1211RCP

SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) TLK1211RCP Supplyvoltage,VDD (see(2)) –0.3V to3 V InputvoltagerangeatTTL terminals,VI –0.5V to4 V Inputvoltagerangeatany otherterminal –0.3V toVDD +0.3V Storagetemperature,Tstg –65°C to150°C Electrostaticdischarge CDM: 1 kV,HBM:4 kV Characterizedfree-airoperatingtemperaturerange TLK1211RCP –40°C to85°C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings” may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions” isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevalues,exceptdifferentialI/Obus voltages,arewithrespecttonetworkgroundterminal. DISSIPATION RATING TABLE TA ≤25°C OPERATING FACTOR (1) TA = 70°CPACKAGE POWER RATING ABOVE TA = 25°C POWER RATING RCP64 (2) 5.25W 46.58mW/ °C 2.89W RCP64 (3) 3.17W 23.70mW/ °C 1.74W RCP64 (4) 2.01W 13.19mW/ °C 1.11W (1) Thisistheinverseofthetraditionaljunction-to-ambientthermalresistance(RθJA). (2) 2 oz.Traceand copperpad withsolder (3) 2 oz.Traceand copperpad withoutsolder (4) StandardJEDEC high-Kboard Table3.Thermal Characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT Board-mounted,no airflow,highconductivityTI recommended testboard,chipsolderedorgreasedto 21.47 thermalland Junction-to-free-airthermalR θJA Board-mounted,no airflow,highconductivityTI °C/Wresistance recommended testboardwiththermallandbutno solderor 42.2 greasethermalconnectiontothermalland Board-mounted,no airflow,JEDEC testboard 75.83 Board-mounted,no airflow,highconductivityTI recommended testboard,chipsolderedorgreasedto 0.38 thermalland Junction-to-case-thermalR θJC Board-mounted,no airflow,highconductivityTI °C/Wresistance recommended testboardwiththermallandbutno solderor 0.38 greasethermalconnectiontothermalland Board-mounted,no airflow,JEDEC testboard 7.8

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www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltage,VDD ,VDD(A) 2.3 2.5 2.7 V Totalsupplycurrent,IDD ,IDD(A) Frequency= 1.25Gbps, PRBS pattern 95 113 mA Totalpower dissipation,PD Frequency= 1.25Gbps, PRBS pattern 238 305 mW Totalshutdowncurrent,IDD ,IDD(A) Enable= 0,VDD(A),VDD = 2.7V 1 mA Startuplocktime,PLL VDD ,VDD(A) = 2.5V,EN ↑ toPLL acquire 500 μs Operatingfree-airtemperature,TA TLK1211RCP -40 85 °C REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency Minimum datarate TLK1211RCP TYP –0.01% 60 TYP+0.01% MHz Frequency Maximum datarate TYP –0.01% 130 TYP+0.01% Accuracy 100 100 ppm Dutycycle 40% 50% 60% Jitter Random plusdeterministic 40 ps TTL ELECTRICAL CHARACTERISTICS overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-leveloutputvoltage IOH = –400 μA VDD –0.2 2.3 V VOL Low-leveloutputvoltage IOL = 1 mA GND 0.25 0.5 V VIH High-levelinputvoltage 1.7 3.6 V VIL Low-levelinputvoltage 0.8 V IIH High-levelInputcurrent VDD = 2.3V,VIN = 2 V 40 μA IIL Low-levelInputcurrent VDD = 2.3V,VIN = 0.4V –40 μA C IN Inputcapacitance 4 pF Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TLK1211RCP

80% 50% 20% tr tr tf tf 80% 50% 20% ∼ V ∼ V ∼ V ∼ V 80% 20% 0 V ∼ 1V ∼ −1V TX+ TX− VOD TLK1211RCP SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com TRANSMITTER/RECEIVER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) VOD VOD = |TxD-TxN| R t= 50Ω 600 800 1100 mV V(cm) Transmitcommon mode voltagerange R t= 50Ω 1000 1250 1400 mV Receiverinputvoltagerequirement, 200 1600 mVVID = |RxP -RxN| Receivercommon mode voltagerange,(RxP 1000 1250 2250 mV+ RxN)/2 Ilkg(R) Receiverinputleakagecurrent -350 350 μA C I Receiverinputcapacitance 2 pF Differentialoutputjitter,Random + deterministic,PRBS pattern, 0.24 UI R ω = 125 MHz t(TJ) Serialdatatotaljitter(peak-to-peak) Differentialoutputjitter,Random + deterministic,PRBS pattern, 0.2 UI R ω = 106.25MHz Differentialoutputjitter,PRBS pattern,t(DJ) Serialdatadeterministicjitter(peak-to-peak) 0.10 UIR ω = 125 MHz R L = 50 Ω,C L = 5 pF,See Figure8tr,tf Differentialsignalrise,falltime(20% to80%) 100 250 psand Figure7 Differentialinputjitter,Random +Serialdatajittertoleranceminimum required 0.25 UIdeterministic,R ω = 125 MHzeye opening,(perIEEE-802.3specificationat Receiverdataacquisitionlocktimefrom 500 μspowerup .75UI jitterclosurewithrandom data 256 ns@ 1.25GbpsData re-locktimefromapplicationofvalid inputdatastream .20UI jitterclosurewith01010..data 128 ns@ 1.25Gbps TBI modes See Figure1 20 22 td(Tx latency) Tx latency UI DDR mode 30 32 TBI modes See Figure6 18 24 DDR mode 17 23 TBI mode 600–620 Mbps 18 21 td(Rx latency) Rx latency UI DDR mode 600–620 Mbps 17 22 TBI mode 1228.8Mbps 19 23 DDR mode 1228.8Mbps 18 23 (1) UI = serialbittime Figure7. Differentialand Common-Mode Output VoltageDefinitions

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50 Ω 50 Ω tr tf CLOCK 80% 50% 20% tr tf 2 V 0.8 V DATA 1.4 V TLK1211RCP www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 Figure8. TransmitterTestSetup LVTTL OUTPUT SWITCHING CHARACTERISTICS overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr(RBC) Clockrisetime 0.3 1.5 ns tf(RBC) Clockfalltime 0.3 1.580% to20% outputvoltage,C = 5 pF (see Figure9)tr Data risetime 0.3 1.5 ns tf Data falltime 0.3 1.5 Data setuptime(RD0–RD9),Datatsu(D1) TBI normalmode, (seeFigure3) 2.5 nsvalidpriortoRBC0 rising Data holdtime(RD0–RD9),Data validth(D1) TBI normalmode, (seeFigure3) 2 nsafterRBC0 rising tsu(D2) Data setuptime(RD0–RD4) DDR mode, R ω = 125 MHz, (seeFigure4) 2 ns th(D2) Data holdtime(RD0–RD4) DDR mode, R ω = 125 MHz, (seeFigure4) 0.8 ns tsu(D3) Data setuptime(RD0–RD9) TBI half-ratemode, R ω = 125 MHz, (seeFigure2) 2.5 ns th(D3) Data holdtime(RD0–RD9) TBI half-ratemode, R ω = 125 MHz, (seeFigure2) 1.5 ns Figure9. TTL Data I/OValidLevelsforAC Measurement TRANSMITTER TIMING REQUIREMENTS overrecommended operatingconditions(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tsu(D4) Data setuptime(TD0–TD9) 1.6 TBI modes ns th(D4) Data holdtime(TD0–TD9) 0.8 tsu(D5) Data setuptime(TD0–TD9) 0.7 DDR modes ns th(D5) Data holdtime(TD0–TD9) 0.5 tr,tf TD[0,9]datariseand falltime See Figure9 2 ns Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TLK1211RCP

5 kΩ 7.5 kΩ RXP RXN GND 5 kΩ 7.5 kΩ VDD ZO ZO ZO ZOTXP TXN Transmitter Media Receiver VDD GND 5 kΩ 7.5 kΩ RXP RXN GND 5 kΩ 7.5 kΩ VDD ZO ZO ZO ZOTXP TXN Transmitter Media Receiver TLK1211RCP SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com

APPLICATION INFORMATION

The PCS maps GMII signalsinto10-bitcode groupsand viceversa,usingan 8b/10bblockcodingscheme. The PCS uses the transmissioncode to improvethe transmissioncharacteristicsof informationto be transferred acrossthelink.The encodingdefinedby thetransmissioncode ensuresthatsufficienttransitionsarepresentin thePHY bitstreamtomake clockrecoverypossibleinthereceiver.Such encodingalsogreatlyincreasesthe likelihoodof detectingany singleor multiplebiterrorsthatmay occur duringtransmissionand receptionof information.The 8b/10btransmissioncode specifiedforuse has a high-transitiondensity,isrun lengthlimited, and isdc-balanced.The transitiondensityofthe8b/10bsymbols range from 3 to8 transitionsper symbol.The definitionof the 8b/10b transmissioncode isspecifiedinIEEE 802.3 gigabitethernetand ANSI X3.230-1994 (FC-PH),clause11. The 8b/10btransmissioncode uses letternotationdescribingthebitsofan unencoded informationoctet.The bit notationof A,B,C,D,E,F,G,Hforan unencoded informationoctetis used in the descriptionof the 8b/10b transmissioncode-groups,where A is the LSB. Each validcode group has been given a name using the followingconvention:/Dx.y/forthe 256 validdata code-groupsand /Kx.y/forthe specialcontrolcode-groups, where y isthedecimalvalueofbitsEDCBA and x isthedecimalvalueofbitsHGF (notedas K<HGF.EDCBA >). Thus,an octetvalueofFE representinga code-groupvalueofK30.7 would be representedinbitnotationas 111 11110. Figure10. High-Speed I/ODirectly-CoupledMode Figure11. High-Speed I/OAC-Coupled Mode

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2.5□V VDDPLL GNDPLL 5 Ω at□100□MHz 2.5□V

62 Controlled Impedance

Transmission□LineTXP

61 Controlled□Impedance

Transmission□LineTXN

54 Controlled□Impedance

Transmission□LineRXP

52 Controlled□Impedance

Transmission□LineRXN Rt Rt 50 Ω 50 Ω TLK1211 0.01 µF TLK1211RCP www.ti.com SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 Figure12. TypicalApplicationCircuit(AC mode) DESIGNING WITH PowerPAD The TLK1211RCP ishoused in a high-performance,thermallyenhanced, 64-pinVQFP (RCP64) PowerPAD package.Use of the PowerPAD package does not requireany specialconsiderationsexceptto note thatthe PowerPAD, which isan exposed die pad on the bottom of the device,isa metallicthermaland electrical conductor.Therefore,ifnotimplementingPowerPAD PCB features,theuse ofsoldermasks (orotherassembly techniques)may be requiredtopreventany inadvertentshortingby theexposed PowerPAD ofconnectionetches orviasunderthepackage.Itisstronglyrecommended thatthePowerPAD be solderedtothethermalland.The recommended convention,however,istonotrunany etchesorsignalviasunderthedevice,buttohave onlya grounded thermalland as explainedbelow.Althoughthe actualsizeof the exposed die pad may vary,the minimum sizerequiredforthekeepoutareaforthe64-pinPFP PowerPAD package is8 mm × 8 mm. Itis recommended thattherebe a thermalland,which is an area of solder-tinned-copper,underneaththe PowerPAD package.The thermallandvariesinsizedependingon thePowerPAD package beingused,thePCB construction,and theamount ofheatthatneeds tobe removed.Inaddition,thethermallandmay or may not containnumerous thermalviasdependingon PCB construction. Copyright© 2006–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TLK1211RCP

SLLS658D –SEPTEMBER 2006–REVISED APRIL 2011 www.ti.com Other requirementsforthermallands and thermalviasare detailedin the TI applicationnote PowerPAD ThermallyEnhanced Package ApplicationReport,TIliteraturenumber SLMA002 ,availableviatheTIWeb pages beginningatURL: http://www.ti.com. Figure13. Example ofa Thermal Land For the TLK1211RCP, thisthermallandmust be grounded to the low-impedanceground planeof the device. This improves not only thermalperformance but also the electricalgroundingof the device.Itis also recommended thatthedevicegroundterminallandingpads be connecteddirectlytothegroundedthermalland. The landsizemust be as largeas possiblewithoutshortingdevicesignalterminals.The thermallandmay be solderedtotheexposed PowerPAD usingstandardreflowsolderingtechniques. Whilethethermallandmay be electricallyfloatedand configuredtoremove heattoan externalheatsink,itis recommended thatthe thermalland be connectedto the low-impedanceground plane forthe device.More informationmay be obtainedfromtheTIapplicationnotePHY Layout,TIliteraturenumber SLLA020 .

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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLK1211RCP Active Production HVQFP (RCP) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TLK1211RCP TLK1211RCP.A Active Production HVQFP (RCP) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TLK1211RCP TLK1211RCP1G4 Active Production HVQFP (RCP) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TLK1211RCP TLK1211RCP1G4.A Active Production HVQFP (RCP) | 64 160 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 TLK1211RCP (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) TLK1211RCP RCP HVQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13 TLK1211RCP.A RCP HVQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13 TLK1211RCP1G4 RCP HVQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13 TLK1211RCP1G4.A RCP HVQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13 Pack Materials-Page 1

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