TLK1201IRCP

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TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00680.6-Gbps to 1.3-Gbps Serializer/Deserializer /C0068Low Power Consumption <200 mW at 1.25 Gbps /C0068LVPECL Compatible Differential I/O on High Speed Interface /C0068Single Monolithic PLL Design /C0068Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking /C0068Receiver Differential Input Thresholds 200 mV Minimum /C0068IEEE 802.3 Gigabit Ethernet Compliant /C0068ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant /C0068Advanced 0.25-µm CMOS Technology /C0068No External Filter Capacitors Required /C0068Comprehensive Suite of Built-In Testability /C0068IEEE 1149.1 JTAG Support /C00682.5-V Supply Voltage for Lowest Power Operation /C00683.3-V Tolerant on LVTTL Inputs /C0068Hot Plug Protection /C006864-Pin VQFP With Thermally Enhanced Package (PowerPAD™) /C0068CPRI Data Rate Compatible (614 Mbps and

1.22 Gbps)

/C0068Industrial Temperature Range Supported: −40°C to 85°C 17 18 19 JTDI SYNC/PASS GND RD0 RD1 RD2 VDD RD3 RD4 RD5 RD6 VDD RD7 RD8 RD9 GND GND TD0 TD1 TD2 VDD TD3 TD4 TD5 TD6 VDD TD7 TD8 TD9 GND MODESEL PRBSEN 21 22 23 24 VDD RXP 63 62 61 60 5964 58 TXP TXN VDDA VDDA GNDA VDDA JTRSTN LOS JTDO ENABLE VDD LOOPEN VDD GND REFCLK VDD SYNCEN GND 56 55 5457 25 26 27 28 29 53 52 TESTEN VDDA RXN 51 50 49 30 31 32 RBC1 RBC0 RBCMODE GNDA JTMS TCK GNDPL L VDDVDDPLL

description

The TLK1201 gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps. Copyright © 2001 − 2007, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.

TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007

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description (continued) The primary application of this device is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK1201I performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface. The TLK1201I supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first, (bits 0 − 4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5 − 9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The device provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The TLK1201I is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device’s PowerPAD be soldered to the thermal land on the board. The TLK1201I is characterized for operation from −0°C to 70°C (TLK1201), or −40°C to 85°C (TLK1201I). power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The TLK1201I is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state. differences between TLK1201/TLK1201I and TNETE2201 The TLK1201/TLK1201I is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See Figure 12 in the Application Information section for an example of a typical application circuit. /C0068The VCC is 2.5 V for the TLK1201 vs 3.3 V for TNETE2201. /C0068The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The TLK1201 uses these pins to provide added test capabilities. The capacitors, if present, do not affect the operation of the device. /C0068No pulldown resistors are required on the TXP/TXN outputs. AVAILABLE OPTIONS PACKAGE TA PLASTIC QUAD FLAT PACK (RCP) TAPE and REEL OPTION −0°C to 70°C TLK1201RCP TLK1201RCPR −40°C to 85°C TLK1201IRCP TLK1201IRCPR

TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 block diagram 2:1 MUX PRBS Generator

10 Bit

RegistersTD(0−9) PRBSEN LOOPEN Parallel to Serial Phase Generator Clock REFCLK Control Logic MODESEL ENABLE TESTEN Interpolator and Clock ExtractionPRBS Verification Serial to Parallel and Comma Detect Clock RBC1 RBC0 SYNC/PASS RD(0−9) SYNCEN RBCMODE JTAG Control Register JTMS JTRSTN JTDI TCK JTDO 2:1 MUX 2:1 MUX Clock Data TXP TXN RXP RXN LOS Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION SIGNAL MODESEL 15 I P/D† Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI. LOS 26 O Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If magnitude of RXP−RXN > 150 mV, LOS = 1, valid input signal If magnitude of RXP−RXN < 150 mV and > 50 mV, LOS is undefined If magnitude of RXP−RXN < 50 mV, LOS = 0, loss of signal RBCMODE 32 I P/D† Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low. † P/D = Internal pulldown

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Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION SIGNAL (continued) RBC0 RBC1 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data on RD0−RD9. The operation of these clocks is dependent upon the receive clock mode selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned to both the rising and falling edges. RD0−RD9 45, 44, 43, 41, 40, 39, 38, 36, 35, O Receive data. When in TBI mode (MODESEL = low) these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the DDR mode (MODESEL = high) only RD0−RD4 are valid. RD5−RD9 are held low. The 5-bit parallel data is clocked out of the transceiver on the rising edge of RBC0. REFCLK 22 I Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0−TD9) for serialization. In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned to the rising edge of REFCLK. RXP RXN PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module. SYNCEN 24 I P/U‡ Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated. When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 − RD9. SYNC/PASS 47 O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode (PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results (high=pass). TD0−TD9 2−4, 6−9, 11−13 I Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. When in the DDR mode (MODESEL = high) only TD0−TD4 are valid. The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. TXP TXN PECL O Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. TEST ENABLE 28 I P/U‡ When this terminal is low, the device is disabled for Iddq testing. RD0 − RD9, RBCn, TXP, and TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the device operates normally. JTDI 48 I P/U‡ Test data input. IEEE1149.1 (JTAG) JTDO 27 O Test data output. IEEE1149.1 (JTAG) JTMS 55 I P/U‡ Test mode select. IEEE1149.1 (JTAG) † P/D = Internal pulldown ‡ P/U = Internal pullup

TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION TEST (continued) JTRSTN 56 I P/U‡ Reset signal. IEEE1149.1 (JTAG) LOOPEN 19 I P/D† Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBSEN 16 I P/D† PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low. TCK 49 I Test clock. IEEE1149.1 (JTAG) TESTEN 17 I P/D† Manufacturing test terminal POWER VDD 5, 10, 20, 23, 29, 37, 42, 50, 63 Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers. VDDA 53, 57, 59, Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter VDDPLL 18 Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering. GROUND GND 1, 14, 21, 25, 33, 46 Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers. GNDA 51, 58 Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX. GNDPLL 64 Ground PLL ground. Provides a ground for the PLL circuitry. † P/D = Internal pulldown ‡ P/U = Internal pullup detailed description data transmission This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected. In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data, TD0−TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted sequentially bit 0 through 9 over the differential high-speed I/O channel. In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0−TD4. In this mode, data is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent to the serializer. The rising edge REFCLK clocks in bit 0−4, and the falling edge of REFCLK clocks in bits 5−9. (Bit 0 is the first bit transmitted).

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minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times. Figure 1. Transmitter Latency Full Rate Mode presented to the protocol controller along with receive byte clocks (RBC0, RBC1). clock is available on RBC0; see Table 1. Table 1. Mode Selection data is valid on the rising edge of RBC1. See the timing diagram shown in Figure 2.

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alignment scheme. The following sections explain how this scheme works and how it realigns itself. referred to as the comma character. The K28.5 character was implemented specifically for aligning data words. and RD0−RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1). Figure 5. The RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. characteristics of the data realignment.

31 Bit

30 Bit

Figure 5. Word Realignment Timing Characteristics Waveforms Systems that do not require framed data may disable byte alignment by tying SYNCEN low. When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character. SYNC pulse is present for the entire RBC0 period.

Figure 6. Receiver Latency − TBI Normal Mode Shown LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined. factory testing, and is not intended for end-user control. is held in a high-impedance state during the loopback testing. ultralow-power idle state when the link is not active.

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING RCP64§ 5.25 W 46.58 mW/°C 2.89 W RCP64¶ 3.17 W 23.70 mW/°C 1.74 W RCP64# 2.01 W 13.19 mW/°C 1.11 W ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). § 2 oz. Trace and copper pad with solder ¶ 2 oz. Trace and copper pad without solder # Standard JEDEC high-K board NOTE: For more information, see the TI application note PowerPAD Thermally Enhanced thermal characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 21.47 RθJA Junction-to-free-air thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 42.2 °C/W Board-mounted, no air flow, JEDEC test board 75.83 Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 0.38 RθJC Junction-to-case-thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 0.38 °C/W Board-mounted, no air flow, JEDEC test board 7.8

TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD, VDD(A) 2.3 2.5 2.7 V Total supply current, IDD, IDD(A) Frequency = 1.25 Gbps, PRBS pattern 90 mA Total power dissipation P Frequency = 1.25 Gbps, PRBS pattern 250 mW Total power dissipation, PD Frequency = 1.25 Gbps, Worst case † 245 mW Total shutdown current, IDD, IDD(A) Enable = 0, V DD(A), VDD = 2.7 V 50 µA Startup lock time, PLL VDD, VDD(A) = 2.5 V, EN↑ to PLL acquire 500 µs Operating free air temperature T TLK1201 0 70 °COperating free-air temperature, TA TLK1201I −40 85 † The worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. reference clock (REFCLK) timing requirements over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency Minimum data rate TLK1201 TYP−0.01% 60 TYP+0.01% Frequency Minimum data rate TLK1201I TYP−0.01% 60 TYP+0.01% MHz Frequency Maximum data rate TYP−0.01% 130 TYP+0.01% MHz Accuracy −100 100 ppm Duty cycle 40% 50% 60% Jitter, peak-to-peak 20 kHz to 10 MHz 40 ps TTL electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = −400 µA VDD−0.2 2.3 V VOL Low-level output voltage IOL = 1 mA GND 0.25 0.5 V VIH High-level input voltage 1.7 3.6 V VIL Low-level input voltage 0.8 V IIH High-level Input current VDD = 2.3 V, V IN = 2 V 40 µA IIL Low-level Input current VDD = 2.3 V, V IN = 0.4 V −40 µA CIN Input capacitance 4 pF

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transmitter/receiver characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT† VO |TxD TxN| Rt = 50 Ω 600 850 1100 mVVOD = |TxD−TxN| Rt = 75 Ω 800 1050 1200 mV V Transmit common mode voltage range Rt = 50 Ω 1100 1250 1400 mVV(cm) Transmit common mode voltage range Rt = 75 Ω 1100 1250 1400 mV Receiver input voltage requirement, VID = |RxP − RxN| 200 1600 mV Receiver common mode voltage range, (RxP + RxN)/2 1000 1250 2250 mV Ilkg(R) Receiver input leakage current −350 350 µA CI Receiver input capacitance 2 pF t Serial data total jitter (peak to peak) Differential output jitter, Random + deterministic, PRBS pattern, Rω = 125 MHz 0.24 UI t(TJ) Serial data total jitter (peak-to-peak) Differential output jitter, Random + deterministic, PRBS pattern, Rω = 106.25 MHz 0.2 UI t(DJ) Serial data deterministic jitter (peak-to-peak) Differential output jitter, PRBS pattern, Rω = 125 MHz 0.12 UI tr, tf Differential signal rise, fall time (20% to 80%) RL = 50 Ω, CL = 5 pF , See Figure 7 and Figure 8 100 250 ps Serial data jitter tolerance minimum required eye Differential input jitter, Random + deterministic, R ω = 125 MHz 0.25 UI Serial data jitter tolerance minimum required eye opening, (per IEEE-802.3 specification) Differential input jitter, random + determinisitc, PRBS pattern at zero crossing 0.3 UI Receiver data acquisition lock time from powerup 500 µs Data relock time from loss of synchronization 1024 Bit times t Tx latency TBI modes See Figure 1 19 20 UItd(Tx latency) Tx latency DDR mode 29 30 UI TBI modes See Figure 6 20 31 DDR mode 27 34 t Rx latency TBI mode 600 − 620 Mbps 24 28 UItd(Rx latency) Rx latency DDR mode 600 − 620 Mbps 27 31 UI TBI mode 1222.8 Mbps 25 29 DDR mode 1222.8 Mbps 27 33 † UI = serial bit time

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APPLICATION INFORMATION

The PCS maps GMII signals into 10-bit code groups and vice versa, using an 8b/10b block coding scheme. The PCS uses the transmission code to improve the transmission characteristics of information to be transferred across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. The 8b/10b transmission code specified for use has a high-transition density, is run length limited, and is dc-balanced. The transition density of the 8b/10b symbols range from 3 to 8 transitions per symbol. The definition of the 8b/10b transmission code is specified in IEEE 802.3 gigabit ethernet and ANSI X3.230-1994 (FC−PH), clause 11.

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TD0−TD9 REFCLK PRBSEN SYNCEN SYNC/PASS47 RD0−RD9 RBC0−RBC1 ENABLE TCK JTMS JTDI JTRSTN JTDO27 LOS26 RBCMODE LOOPEN MODESEL Host Protocol Device JTAG Controller VDD VDDA 2.5 V VDDPLL GNDPLL 5 Ω at 100 MHz 2.5 V

62 Controlled Impedance

61 Controlled Impedance

54 Controlled Impedance

52 Controlled Impedance

Rt 50 Ω 50 Ω TLK1201I TLK1201II 0.01 µF Figure 12. Typical Application Circuit (AC mode) vary, the minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.

TLK1201RCP, TLK1201IRCP ETHERNET TRANSCEIVERS SLLS506E − AUGUST 2001 − REVISED MAY 2007 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 designing with PowerPAD (continued) It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report , TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com Figure 13. Example of a Thermal Land PowerPAD using standard reflow soldering techniques. information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLK1201IRCP NRND HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1201IRCPG4 NRND HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1201RCP NRND HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK1201RCPG4 NRND HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 15-May-2007 Addendum-Page 1

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