TLK1201AIRCP

TLK1201ARCP_16 TI1 | Alldatasheet

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www.ti.com Advanced 0.25- μ m CMOS Technology 0.6-Gbps to 1.3-Gbps Serializer/Deserializer No External Filter Capacitors Required Low Power Consumption <200 mW at 1.25 Comprehensive Suite of Built-In Testability Gbps IEEE 1149.1 JTAG Support LVPECL Compatible Differential I/O on High 2.5-V Supply Voltage for Lowest Power Speed Interface Operation Single Monolithic PLL Design 3.3-V Tolerant on LVTTL Inputs Support For 10-Bit Interface or Reduced Hot Plug Protection Interface 5-Bit DDR (Double Data Rate) 64-Pin VQFP With Thermally Enhanced Clocking Package PowerPAD Receiver Differential Input Thresholds 200 mV CPRI Data Rate Compatible (614 Mbps, 1.22 Minimum Gbps) IEEE 802.3 Gigabit Ethernet Compliant Industrial Temperature Range Supported: ANSI X3.230-1994 (FC-PH) Fibre Channel C to C Compliant The TLK1201A/TLK1201AI gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps. The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of Ω or Ω The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2004 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to Gbps of data bandwidth over a copper or optical media interface. The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits of the 8b/10b encoded data) are clocked on the falling edge of the clock. The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board. The transceiver is characterized for operation from C to C (TLK1201A) or C to C (TLK1201AI). The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state. The TLK1201A/TLK1201AI transceiver is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See Figure in the Application Information section for an example of a typical application circuit. The V CC is 2.5 V for the TLK1201A vs 3.3 V for TNETE2201. The PLL filter capacitors on terminals 16, 17, 48, and of the TNETE2201 are no longer required. The TLK1201A uses these terminals to provide added test capabilities. The capacitors, if present, do not affect the operation of the device. No pulldown resistors are required on the TXP/TXN outputs. AVAILABLE OPTIONS PACKAGE (1) T A PLASTIC QUAD FLAT PACK (RCP) C to C TLK1201ARCP C to C TLK1201AIRCP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com BLOCK DIAGRAM 2:1 MUX PRBS Generator

10 Bit

RegistersTD(0-9) PRBSEN LOOPEN Parallel to Serial Phase Generator Clock REFCLK Control Logic MODESEL ENABLE TESTEN Interpolator and Clock ExtractionPRBS Verification Serial to Parallel and Comma Detect Clock RBC1 RBC0 SYNC/PASS RD(0-9) SYNCEN RBCMODE JTAG Control Register JTMS JTRSTN JTDI TCK JTDO 2:1 MUX 2:1 MUX Clock Data TXP TXN RXP RXN LOS TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Terminal Functions TERMINAL I/O NO. SIGNAL MODESEL I Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR P/D (1) interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI. LOS O Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If the magnitude of RXP-RXN 150 mV, then LOS which is a valid input signal. If the magnitude of RXP-RXN mV and 150 mV, then LOS is undefined. If the magnitude of RXP-RXN mV, then LOS which is a loss of signal. RBCMODE I Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output P/D (1) on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low. RBC0 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit RBC1 output data on RD0 RD9. The operation of these clocks is dependent upon the receive clock mode selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes and of received data. RBC1 registers bytes and of received data. In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned on both the rising and falling edges. (1) P/D Internal pulldown Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Terminal Functions (continued) TERMINAL I/O NO. RD0 RD9 45, 44, O Receive data. When in TBI mode (MODESEL low), these outputs carry 10-bit parallel data 43, 41, output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and 40, 39, RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the 38, 36, DDR mode (MODESEL high), only RD0 RD4 are valid. RD5 RD9 are held low. The 5-bit 35, parallel data is clocked out of the transceiver on the rising edge of RBC0. REFCLK I Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0 TD9) for serialization. In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned on the rising edge of REFCLK. RXP PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a RXN copper or an optical I/F module. SYNCEN I Synchronous function enable. When SYNCEN is high, the internal synchronization function is P/U (2) activated. When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 RD9. SYNC/PASS O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode (PRBSEN high), SYNC/PASS outputs the status of the PRBS test results (high pass). TD0 TD9 2-4, 6-9, I Transmit data. When in the TBI mode (MODESEL low) these inputs carry 10-bit parallel data 11-13 output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. When in the DDR mode (MODESEL high) only TD0 TD4 are valid. The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. TXP PECL Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper TXN O or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. TEST ENABLE I When this terminal is low, the device is disabled for Iddq testing. RD0 RD9, RBCn, TXP, and P/U (3) TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the device operates normally. JTDI I Test data input. IEEE1149.1 (JTAG) P/U (3) JTDO O Test data output. IEEE1149.1 (JTAG) JTMS I Test mode select. IEEE1149.1 (JTAG) P/U (3) JTRSTN I Reset signal. IEEE1149.1 (JTAG) P/U (3) LOOPEN I Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The P/D (4) transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBSEN I PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS P/D (4) verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low. TCK I Test clock. IEEE1149.1 (JTAG) TESTEN I Manufacturing test terminal P/D (4) (2) P/U Internal pullup (3) P/U Internal pullup (4) P/D Internal pulldown Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com DETAILED TXP, TXN TD(0−9) REFCLK td(Tx latency) 10-Bit Code b9b8b7 b0 b1 b2 b3 Measured 10-Bits TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Terminal Functions (continued) TERMINAL I/O NO. POWER VDD 10, Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers. 20, 23, 29, 37, 42, 50, VDDA 53, 57, Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter 59, VDDPLL Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering. GROUND GND 14, Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers. 21,25, 33, GNDA 51, Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX. GNDPLL Ground PLL ground. Provides a ground for the PLL circuitry. This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected. In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data, TD0 TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted sequentially bits through over the differential high-speed I/O channel. In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0 TD4. In this mode, data is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent to the serializer. The rising edge REFCLK clocks in bits and the falling edge of REFCLK clocks in bits Bit is the first bit transmitted. Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit The minimum latency in TBI mode is bit times. The maximum latency in TBI mode is bit times. The minimum latency in DDR mode is bit times, and maximum latency in DDR mode is bit times. Figure Transmitter Latency Full Rate Mode Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com Data Reception Receiver Clock Select Mode td(S) td(S) td(H) td(H) RBC0 RBC1 SYNC RD(0-9) td(H)td(S) RBC0 SYNC RD(0-9) TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with receive byte clocks (RBC0 and RBC1). There are two modes of operation for the parallel bus: the 10-bit (TBI) mode and 5-bit (DDR) mode. When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: full-rate clock on RBC0 and half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate clock is available on RBC0; see Table Table Mode Selection RECEIVE BYTE CLOCK MODESEL RBCMODE MODE TLK1201A TLK1201AI TBI half-rate MHz MHz TBI full-rate 130 MHz 130 MHz DDR 130 MHz 130 MHz DDR 130 MHz 130 MHz In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte of the received data is valid on the rising edge of RBC1. See the timing diagram shown in Figure Figure Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode) In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode. See the timing diagram shown in Figure Figure Synchronous Timing Characteristics Waveforms (TBI Full-Rate Mode) In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1 is low impedance. The data is clocked bit first, and aligned to the rising edge of RBC0. See the timing diagram shown in Figure Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com K28.5 DXX.X td(S) td(H) td(S) td(H) Bits 0-4 Bits 5-9 RBC0 SYNC RD(0-4) Receiver Word Alignment Comma Character on Expected Boundary Comma Character Not on Expected Boundary TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Figure Synchronous Timing Characteristics Waveforms (DDR Mode) The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, 0.02% (200 PPM) for proper operation (see the recommended operating tables). This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word alignment scheme. The following sections explain how this scheme works and how it realigns itself. This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial input data to the 7-bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme as a pattern consisting of 0011111010 negative number beginning with disparity) with the MSBs (0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning data words. As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly aligned and data realignment is not required. Figure shows the timing characteristics of RBC0, RBC1, SYNC, and RD0 RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1.) If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure The RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design, the maximum stretch that occurs is bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge. Figure shows the timing characteristics of the data realignment. Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

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31 Bit

Misaligned K28.5 Misalignment Corrected INPUT DA TA RBC0 RBC1 RD(0-9) SYNC Corrupt Data

30 Bit

Times (Max) Data Reception Latency RXP , RXN RD(0−9) RBC0 10-Bit Code td(Rx latency) 10-Bit Code b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 Loss of Signal Detection TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Figure Word Realignment Timing Characteristics Waveforms Systems that do not require framed data may disable byte alignment by tying SYNCEN low. When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character. The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the SYNC pulse is present for the entire RBC0 period. The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is bit times, and the maximum latency is bit times. The minimum latency in DDR mode is bit times and maximum latency is bit times. Figure Receiver Latency TBI Normal Mode Shown This device has a loss-of-signal (LOS) detection circuit for conditions where the incoming signal no longer has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV. The LOS is low for all amplitudes below mV. Between mV and 150 mV, LOS is undetermined. Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com Testability Loopback Testing Enable Function PRBS Function JTAG TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also allows for a BIST (built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for factory testing, and is not intended for end-user control. The transceiver can provide a self-test function by enabling (setting LOOPEN to high level) the internal loopback path. Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. The external differential output is held in a high-impedance state during the loopback testing. When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an ultralow-power idle state when the link is not active. This device has a built-in PRBS function. When the PRBSEN control bit is set high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to the receiver of another TLK1201AI. Since the PRBS is not really random and is really a predetermined sequence of and 0s, the data can be captured and checked for errors by a BERT. This device also has a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. When PRBS is enabled, RBCMODE is ignored. MODESEL must be low for the PRBS verifier to function correctly. The PRBS testing supports two modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS verification is latched on the SYNC/PASS output (that is, a single failure forces SYNC/PASS to remain low). The TLK1201A supports an IEEE1149.1 JTAG function while maintaining compatibility with the industry standard pin QFP package footprint. In this way, the TLK1201A installed on a board layout that was designed for the industry standard footprint such as for the TNETE2201B. (Provided the supply voltage can be programmed from the older 3.3 V to 2.5 V.) The JTAG pins on the TLK1201A are chosen to either be on the vender-unique pins of the industry standard footprint, or are on pins that were previously power or ground. The TRSTN pin has been placed on pin 56, which is a ground on the industry standard footprint. In this way, a TLK1201A installed onto the older footprint has the JTAG tap controller held in reset, and thus disabled. If the JTAG function is desired, then the JTAG pins TRSTN, TMS, TCK, TDI, and TDO can be used in the usual manner for a JTAG function. If the JTAG function is not desired, then connecting TRSTN to ground is recommended. TMS and TDI have internal pullup resistors, and can thus be left unconnected if not used. TDO is an output and should be left unconnected if JTAG is not used. TCK does not have an internal pullup, and can be tied to GND or PWR if not used, but with TRSTN low, this input is not used, and thus can be left unconnected. Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) DISSIPATION RATING TABLE TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 over operating free-air temperature range (unless otherwise noted) TLK1201A/TLK1201AI Supply voltage, V DD (see (2) 0.3 V to V Input voltage range at TTL terminals, V I 0.5 V to V Input voltage range at any other terminal 0.3 V to V DD +0.3 V Storage temperature, T stg C to 150 C Electrostatic discharge CDM: kV, HBM:2 kV TLK1201A C to C Characterized free-air operating temperature range TLK1201AI C to C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. T A C OPERATING FACTOR (1) T A C PACKAGE POWER RATING ABOVE T A C POWER RATING RCP64 (2) 5.25 W 46.58 mW/ C 2.89 W RCP64 (3) 3.17 W 23.70 mW/ C 1.74 W RCP64 (4) 2.01 W 13.19 mW/ C 1.11 W (1) This is the inverse of the traditional junction-to-ambient thermal resistance Θ JA (2) oz. Trace and copper pad with solder (3) oz. Trace and copper pad without solder (4) Standard JEDEC high-K board Thermal Characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to 21.47 thermal land Junction-to-free-air thermal R Θ JA Board-mounted, no air flow, high conductivity TI C/W resistance recommended test board with thermal land but no solder or 42.2 grease thermal connection to thermal land Board-mounted, no air flow, JEDEC test board 75.83 Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to 0.38 thermal land Junction-to-case-thermal R Θ JC Board-mounted, no air flow, high conductivity TI C/W resistance recommended test board with thermal land but no solder or 0.38 grease thermal connection to thermal land Board-mounted, no air flow, JEDEC test board 7.8 Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com RECOMMENDED OPERATING CONDITIONS REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS TTL ELECTRICAL CHARACTERISTICS TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 MIN NOM MAX UNIT Supply voltage, V DD V DD(A) 2.3 2.5 2.7 V Total supply current, I DD I DD(A) Frequency 1.25 Gbps, PRBS pattern mA Frequency 1.25 Gbps, PRBS pattern 250 mW Total power dissipation, P D Frequency 1.25 Gbps, worst case (1) 245 mW Total shutdown current, I DD I DD(A) Enable V DD(A) V DD 2.7 V μ A Startup lock time, PLL V DD V DD(A) 2.5 EN to PLL acquire 500 μ s TLK1201A Operating free-air temperature, T A C TLK1201AI -40 (1) The worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TLK1201A TYP 0.01% TYP+0.01% Frequency Minimum data rate TLK1201AI TYP 0.01% TYP+0.01% MHz Frequency Maximum data rate TYP 0.01% 130 TYP+0.01% Accuracy 100 100 ppm Duty cycle 40% 50% 60% Jitter Random plus deterministic ps over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH High-level output voltage I OH 400 μ A V DD 0.2 2.3 V V OL Low-level output voltage I OL mA GND 0.25 0.5 V V IH High-level input voltage 1.7 3.6 V V IL Low-level input voltage 0.8 V I IH High-level Input current V DD 2.3 V IN V μ A I IL Low-level Input current V DD 2.3 V IN 0.4 V μ A C IN Input capacitance pF Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com TRANSMITTER/RECEIVER CHARACTERISTICS 80% 50% 20% tr tr tf tf 80% 50% 20% ∼ V ∼ V ∼ V ∼ V 80% 20% 0 V ∼ 1V ∼ −1V TX+ TX− VOD TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) R t Ω 600 850 1100 V OD |TxD-TxN| mV R t Ω 800 1050 1200 R t Ω V (cm) Transmit common mode voltage range 1100 1250 1400 mV R t Ω Receiver input voltage requirement, 200 1600 mV V ID |RxP RxN| Receiver common mode voltage range, (RxP 1000 1250 2250 mV RxN)/2 I lkg(R) Receiver input leakage current -350 350 μ A C I Receiver input capacitance pF Differential output jitter, Random deterministic, PRBS pattern, 0.24 UI R ω 125 MHz t (TJ) Serial data total jitter (peak-to-peak) Differential output jitter, Random deterministic, PRBS pattern, 0.2 UI R ω 106.25 MHz Differential output jitter, PRBS pattern, t (DJ) Serial data deterministic jitter (peak-to-peak) 0.10 UI R ω 125 MHz t r t f Differential signal rise, fall time (20% to 80%) R L Ω C L pF, See Figure 100 250 ps Differential input jitter, Random 0.25 UI deterministic, R ω 125 MHz Serial data jitter tolerance minimum required Differential input jitter, random eye opening, (per IEEE-802.3 specification) determinisitc, PRBS pattern at zero 0.3 UI crossing Receiver data acquisition lock time from 500 μ s powerup Data relock time from loss of synchronization 1024 Bit times TBI modes See Figure t d(Tx latency) Tx latency UI DDR mode TBI modes See Figure DDR mode TBI mode 600 620 Mbps t d(Rx latency) Rx latency UI DDR mode 600 620 Mbps TBI mode 1228.8 Mbps DDR mode 1228.8 Mbps (1) UI serial bit time Figure Differential and Common-Mode Output Voltage Definitions Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com C L 5 pF C L 5 pF 50 Ω 50 Ω LVTTL OUTPUT SWITCHING CHARACTERISTICS tr tf CLOCK 80% 50% 20% tr tf 2 V 0.8 V DATA 1.4 V TRANSMITTER TIMING REQUIREMENTS TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Figure Transmitter Test Setup over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t r(RBC) Clock rise time 0.3 1.5 ns t f(RBC) Clock fall time 0.3 1.5 80% to 20% output voltage, C pF (see Figure t r Data rise time 0.3 1.5 ns t f Data fall time 0.3 1.5 TBI normal mode, (see Figure R ω 125 MHz 2.5 Data setup time (RD0 RD9), Data t su(D1) ns valid prior to RBC0 rising TBI normal mode, (see Figure R ω 61.44 MHz TBI normal mode, (see Figure R ω 125 MHz Data hold time (RD0 RD9), Data valid t h(D1) ns after RBC0 rising TBI normal mode, (see Figure R ω 61.44 MHz t su(D2) Data setup time (RD0 RD4) DDR mode, R ω 125 MHz, (see Figure ns t h(D2) Data hold time (RD0 RD4) DDR mode, R ω 125 MHz, (see Figure 0.8 ns t su(D3) Data setup time (RD0 RD9) TBI half-rate mode, R ω 125 MHz, (see Figure 2.5 ns t h(D3) Data hold time (RD0 RD9) TBI half-rate mode, R ω 125 MHz, (see Figure 1.5 ns Figure TTL Data I/O Valid Levels for AC Measurement over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t su(D4) Data setup time (TD0 TD9) 1.6 TBI modes ns t h(D4) Data hold time (TD0 TD9) 0.8 t su(D5) Data setup time (TD0 TD9) 0.7 DDR modes ns t h(D5) Data hold time (TD0 TD9) 0.5 t r t f TD[0,9] data rise and fall time See Figure ns Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com APPLICATION INFORMATION 8B/10B TRANSMISSION CODE VDD GND 5 kΩ 7.5 kΩ RXP RXN GND 5 kΩ 7.5 kΩ VDD ZO ZO ZO ZOTXP TXN Transmitter Media Receiver VDD GND 5 kΩ 7.5 kΩ RXP RXN GND 5 kΩ 7.5 kΩ VDD ZO ZO ZO ZOTXP TXN Transmitter Media Receiver TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 The PCS maps GMII signals into 10-bit code groups and vice versa, using an 8b/10b block coding scheme. The PCS uses the transmission code to improve the transmission characteristics of information to be transferred across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. The 8b/10b transmission code specified for use has a high-transition density, is run length limited, and is dc-balanced. The transition density of the 8b/10b symbols range from to transitions per symbol. The definition of the 8b/10b transmission code is specified in IEEE 802.3 gigabit ethernet and ANSI X3.230-1994 (FC-PH), clause 11. The 8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the code-groups, where A is the LSB. Each valid code group has been given a name using the following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups, where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K <HGF.EDCBA >). Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111 11110. Figure 10. High-Speed I/O Directly-Coupled Mode Figure 11. High-Speed I/O AC-Coupled Mode Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com GND GNDA TESTEN TD0-TD9 REFCLK PRBSEN SYNCEN SYNC/PASS47 RD0-RD9 RBC0-RBC1 ENABLE TCK JTMS JTDI JTRSTN JTDO27 LOS26 RBCMODE LOOPEN MODESEL Host Protocol Device JTAG Controller VDD VDDA 2.5 V VDDPLL GNDPLL 5 Ω at 100 MHz 2.5 V

62 Controlled Impedance

61 Controlled Impedance

54 Controlled Impedance

52 Controlled Impedance

R t 50 Ω 50 Ω TLK1201AI TLK1201AII 0.01 µF DESIGNING WITH PowerPAD TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Figure 12. Typical Application Circuit (AC Mode) The TLK1201A/TLK1201AI is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 64-pin PFP PowerPAD package is mm נ mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Copyright 2004 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com TLK1201ARCP TLK1201AIRCP ETHERNET TRANSCEIVERS SLLS580D FEBRUARY 2004 REVISED SEPTEMBER 2007 Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report TI literature number SLMA002 available via the TI Web pages beginning at URL: http://www.ti.com Figure 13. Example of a Thermal Land For the TLK1201AI, this thermal land must be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size must be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout TI literature number SLLA020 Submit Documentation Feedback Copyright 2004 2007, Texas Instruments Incorporated Product Folder Link(s): TLK1201ARCP TLK1201AIRCP

www.ti.com 11-Aug-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLK1201AIRCP LIFEBUY HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TLK1201AI TLK1201AIRCPG4 LIFEBUY HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TLK1201AI TLK1201AIRCPR LIFEBUY HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TLK1201AI TLK1201AIRCPRG4 LIFEBUY HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TLK1201AI TLK1201ARCP LIFEBUY HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TLK1201A TLK1201ARCPG4 LIFEBUY HVQFP RCP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TLK1201A TLK1201ARCPR LIFEBUY HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TLK1201A TLK1201ARCPRG4 LIFEBUY HVQFP RCP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TLK1201A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 11-Aug-2016 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK1201AIRCPR HVQFP RCP 64 1000 367.0 367.0 45.0 TLK1201ARCPR HVQFP RCP 64 1000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2

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