TLK100

TLK100_11 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 88

Technical content

Media Access□Controller MII 10/100□Mb/s TLK100 25-MHz Clock Source Status LEDs RJ-45 10BASE-T or 100BASE-TX B0312-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 IndustrialTemp,SinglePort10/100Mb/sEthernetPhysicalLayerTransceiver Check forSamples: TLK100

1 Introduction

1.1 Features

• Temperature From –40°C to85°C • Bus I/OProtection-±16kV JEDEC HBM
• Low Power Consumption, < 200mW Typical • IEEE 802.3uPCS, 100BASE-TX Transceivers
• Cable Diagnostics • Enables IEEE1588 Time-Stamping
• Error-FreeOperationup to200 Meters Under • IEEE 1149.1JTAG TypicalConditions • IntegratedANSI X3.263Compliant TP-PMD
• 3.3VMAC Interface PhysicalSublayerwithAdaptiveEqualization and BaselineWander Compensation• Auto-MDIX for10/100Mb/s
• Programmable LED Support Link,10/100Mb/s• Energy DetectionMode Mode, Activity,and CollisionDetect• 25 MHz Clock Out
• 10/100Mb/s Packet BIST (BuiltinSelfTest)• MIISerialManagement Interface(MDC and
• 48-pinTQFP Package (7mm) × (7mm)MDIO)
• IEEE 802.3uMII 1.2 Applications• IEEE 802.3uAuto-Negotiationand Parallel Detection • IndustrialControlsand FactoryAutomation
• IEEE 802.3uENDEC, 10BASE-T • GeneralEmbedded ApplicationsTransceiversand Filters

1.3 GeneralDescription

The TLK100 isa single-portEthernetPHY for10BaseT and 100Base TX signaling.Itintegratesallthe physical-layerfunctionsneeded totransmitand receivedataon standardtwisted-paircables.Thisdevice supportsthe standardMedia IndependentInterface(MII)fordirectconnectionto a Media Access Controller(MAC). The TLK100 isdesignedforpower-supplyflexibility,and can operatewitha single3.3V power supplyor withcombinationsof3.3V,1.8V,and 1.1Vpower suppliesforreducedpower operation. The TLK100 uses mixed-signalprocessingtoperformequalization,datarecovery,and errorcorrectionto achieverobustoperationoverCAT 5 twisted-pairwiring.Itnotonlymeets therequirementsofIEEE 802.3, butmaintainshighmarginsintermsofcross-talkand aliennoise.

1.4 System Diagram

Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas of publicationdate. Copyright© 2009,Texas InstrumentsIncorporatedProducts conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

TX_CLK TXD[3:0] TX_EN MDIO MDC COL CRS/CRS_DV RX_ER RX_DV RXD[3:0] RX_CLK TX_DATA RX_CLK Reference ClockTD± RD± LEDs MII Interface Auto-MDIX DAC ADC JT AG MII Serial Management TX_CLK RX_DATA 10BASE-T and 100BASE-TX 10BASE-T and 100BASE-TX Transmit Block Receive Block MII Registers Auto-Negotiation State□Machine Clock Generation Boundary Scan LED Drivers B0313-01 Cable Diagnostics BIST TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Figure1-1.TLK100 FunctionalBlock Diagram

2 Introduction Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

MII_TXD _0 MII _TXD_1 MII _TXD_2 MII _TXD_3 MII_RX _CLK MII _CRS / LED_CFG MII_TX _EN MII_TX_CLK MII_COL / PHY AD0 MII_RX_D V MII_R XD_0 / P HYA D1 MII_R XD_1 / P HYA D2 MII_R XD_2 / P HYA D3 MII_R XD_3 / P HYA D4 MDC MDIO LED _A C T / AN _EN LED _SP EED / AN_1 LED _LINK / AN _0 PWRDNN/INT RESETN JT AG_TCK JT AG_TDI JT AG _TMS JT AG_ TDO JT AG_TRSTN XO MII_RX_ER R / MDIX_EN TD- TD+ RD- RD+ VA11_PFBOUT V18_PFBOUT VA11_PFBIN1 VA11_PFBIN2 V18_PFBIN1 V18_PFBIN2 VDD33_ VA1 1 VDD1 1 VDD33_IO VDD33_IO VDD33_V18 VDD33_VD1 1 XI TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

1.5 Pin Layout

Figure1-2.TLK100 PIN DIAGRAM, TOP VIEW Copyright© 2009,Texas InstrumentsIncorporated Introduction 3 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

4 Contents Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

2 Pin Descriptions

The TLK100 pinsare classifiedintothefollowinginterfacecategories(eachinterfaceisdescribedinthe sectionsthatfollow):

• SerialManagement Interface
• MAC Data Interface
• ClockInterface
• LED Interface
• JTAG Interface
• Resetand Power Down
• Configuration(Jumper)Options
• 10/100Mb/s PMD Interface
• SpecialConnectPins
• Power and Ground pins Note:Configurationpinoption.See Section2.7forJumper Definitions. The definitionsbelowdefinethefunctionalityofeach pin. Type:I Input Type:O Output Type:I/O Input/Output Type:OD Open Drain Type:PD, PU InternalPulldown/Pullup Type:S ConfigurationPin(Allconfigurationpinshave weak internalpullupsorpulldowns.If a differentdefaultvalueisneeded,thenuse an external2.2kΩ resistor.See Section2.7fordetails.)

2.1 SerialManagement Interface

NAME NO. MANAGEMENT DATA CLOCK: Clocksignalforthemanagement datainput/output(MDIO) interface.The MDC 32 I maximum MDC rateis25 MHz; thereisno minimum MDC rate.MDC isnot requiredtobe synchronoustothe MII_TX_CLK ortheMII_RX_CLK. MANAGEMENT DATA I/O:Bidirectionalcommand /datasignalsynchronizedtoMDC. EitherthelocalMDIO 33 I/O controllerortheTLK100 may drivetheMDIO signal.Thispinrequiresa pull-upresistorwithvalue1.5kΩ. Copyright© 2009,Texas InstrumentsIncorporated PinDescriptions 5 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

2.2 MAC Data Interface

NAME NO. MIITRANSMIT CLOCK: :MIITransmitClockprovides25MHz or2.5MHz referenceMII_TX_CLK 19 O, PD clockdependingon thespeed. MIITRANSMIT ENABLE: MII_TX_EN ispresentedon therisingedge ofthe MII_TX_EN 18 I,PD MII_TX_CLK .Itindicatesthepresenceofvaliddatainputson MII_TXD[3:0].Itisan activehighsignal. MII_TXD_0 13 MII_TXD_1 14 MIITRANSMIT DATA: The transmitdatanibblereceivedfromtheMAC thatisIS,I,PDMII_TXD_2 15 synchronoustotherisingedge oftheMII_TX_CLK. MII_TXD_3 16 MIIRECEIVE CLOCK: MIIreceiveclockprovidesa 25MHz or2.5MHz referenceclock,MII_RX_CLK 23 O dependingon thespeed,thatisderivedfromthereceiveddatastream. MIIRECEIVE DATA VALID: Thispinindicatesvaliddataispresenton theMII_RX_DV 30 S,O, PD correspondingMII_RXD[3:0]. MIIRECEIVE ERROR :Thispinindicatesthatan errorsymbolhas been detectedwithinMII_RX_ERR/MDIX_EN 31 S,O, PU a receivedpacket. MII_RXD_0/PHYAD1 25 MIIRECEIVE DATA: Symbols receivedon thecablearedecoded and presentedonMII_RXD_1/PHYAD2 26 S,O, PD thesepinssynchronoustoMII_RX_CLK. They containvaliddatawhen MII_RX_DV isMII_RXD_2/PHYAD3 27 asserted.MII_RXD_3/PHYAD4 28 MII_CRS/LED_CFG 22 S,O, PU MIICARRIER SENSE: Thispinisassertedhighwhen thereceivemedium isnon-idle. MIICOLLISION DETECT: InFullDuplexMode thispinisalwayslow.In MII_COL/PHYAD0 24 S,O, PU 10BASE-T/100BASE-TX half-duplexmodes, thispinisassertedHIGH onlywhen both thetransmitand receivemedia arenon-idle.

2.3 Clock Interface

NAME NO. CRYSTAL/OSCILLATOR INPUT: Referenceclock.25MHz ±50 ppm tolerancecrystalreferenceor XI 39 I oscillatorinput.The TLK100 supportseitheran externalcrystalresonatorconnectedacrosspinsXIand XO, oran externalCMOS-leveloscillatorsourceconnectedtopinXIonly. CRYSTAL OUTPUT: ReferenceClockoutput.XO pinisused forcrystalonly.Thispinshouldbe leftXO 37 O floatingwhen an oscillatorinputisconnectedtoXI. 25 MHz CLOCK OUTPUT: InMIImode, thispinprovidesa 25 MHz clockoutputtothesystem.This CLK25OUT 12 O allowsotherdevicestouse thereferenceclockfromtheTLK100 withoutrequiringadditionalclock sources.

2.4 LED Interface

(See Table3-3forLED Mode Selection) PIN TYPE DESCRIPTION NAME NO. ThispinindicatesthestatusofthelinkinMode 1.When thelinkisgood theLED willbe ON. In LED_LINK/AN_0 36 S,O, PU Mode 2 and Mode 3,thispinindicatestransmitand receiveactivityinadditiontothestatusofthe Link.The LED isON when Linkisgood.Itwillblinkwhen thetransmitterorreceiverisactive. Thispinindicatesthespeed ofthelink.ItisON when thelinkspeed is100 Mb/s and OFF when itLED_SPEED/AN_1 35 S,O, PU is10 Mb/s. Inmode 1 thispinindicatesifthereisany activityon thelink.ItisON (pulse)when activityis LED_ACT/AN_EN 34 S,O, PU presenton eitherTransmitorReceivechannel.InMode 3,thisLED outputmay be programmed to indicateFull-duplexstatus.

6 PinDescriptions Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

2.5 JTAG Interface

NAME NO. JTAG_TCK 44 I,PU Thispinisthetestclock.Thispinhas a weak internalpullup. JTAG_TDI 45 I,PU Thispinisthetestdatainput.Thispinhas a weak internalpullup. JTAG_TDO 47 O Thispinisthetestdataoutput. JTAG_TMS 46 I,PU Thispinselectsthetestmode. Thispinhas a weak internalpullup. JTAG_TRST Thispinisan activelowasynchronoustestreset.Thispinhas a weak internalpullup.48 I,PUN

2.6 Reset and Power Down

NAME NO. Thispinisan activeLow resetinputthatinitializesorre-initializesalltheinternalregistersofthe RESETN 43 I,PU TLK100. Assertingthispinlowforatleast1 μs willforcea resetprocesstooccur.Alljumper optionsarereinitializedas well. Registeraccessisrequiredforthispintobe configuredeitheras power down oras an interrupt. The defaultfunctionofthispinispower down. When thispinisconfiguredfora power down function,an activelowsignalon thispinwillputthe PWRDNN/INT 42 I,OD, PU deviceispower down mode. When thispinisconfiguredas an interruptpinthenthispinisassertedlowwhen an interrupt conditionoccurs.The pinhas an open-drainoutputwitha weak internalpull-up.Some applicationsmay requirean externalpull-upresistor. Copyright© 2009,Texas InstrumentsIncorporated PinDescriptions 7 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

2.7 Jumper Options

Jumper optionisan elegantway toconfiguretheTLK100 intospecificmodes ofoperation.Some ofthe functionalpinsare used as jumperoptions.The logicstatesofthesepinsare sampled duringresetand areused toconfigurethedeviceintospecificmodes ofoperation.Below tableshows thepinsused forthe jumperoptionand itsdescription.The functionalpinname isindicatedinparentheses. A 2.2kΩ resistorshouldbe used forpull-downorpull-uptochange thedefaultjumperoption.Ifthedefault optionisrequired,thenthereisno need forexternalpull-uporpulldown resistors.Sincethesepinsmay have alternatefunctionsafterresetisdeasserted,theyshouldnotbe connecteddirectlytoVCC orGND. PIN TYPE NAME NO. DESCRIPTION PHYAD0 (MII_COL) 24 The TLK100 providesfivePHY addresspins,thestatesofwhicharelatchedintoanPHYAD1 (MII_RXD_0) 25 internalregisteratsystemhardwarereset.The TLK100 supportsPHY AddressjumperingPHYAD2 (MII_RXD_1) 26 S,O, PD values0 (<00000>)through31 (<11111>).AllPHYAD[4:0]pinshave weak internalPHYAD3 (MII_RXD_2) 27 pull-downresistors.PHYAD4 (MII_RXD_3) 28 AN_EN: When high,thisputsthepartintoadvertisedAuto-Negotiationmode withthe capabilitysetby AN_0 and AN_1 pins.When low,thisputsthepartintoForcedMode with thecapabilitysetby AN_0 and AN_1 pins. AN_0 / AN_1: These inputpinscontrolthe forcedor advertisedoperatingmode of the TLK100 accordingtothefollowingtable.The valueon thesepinsissetby connectingthe inputpinstoGND (0)orVCC (1)through2.2kΩ resistors.These pinsshouldNEVER be connecteddirectlytoGND orVCC. The statusof these pins are latchedintothe Basic Mode ControlRegisterand the Auto_NegotiationAdvertisementRegisterduringHardware-Reset. The defaultis111 sincethesepinshave internalpull-ups. AN_EN AN_1 AN_0 Forced ModeAN_EN (LED_ACT) 34 AN_1 (LED_SPEED) 35 S,O, PU 0 0 0 10BASE-T, Half-Duplex AN_0 (LED_LINK) 36 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN_1 AN_0 AdvertisedMode 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 10BASE-TX, Half/Full-Duplex 10BASE-T, Half-Duplex1 1 0 100BASE-TX, Half-Duplex 10BASE-T, Half/Full-Duplex1 1 1 100BASE-TX, Half/Full-Duplex ThisjumperingoptionalongwithLEDCR registerbitdeterminesthemode ofoperationof LED_CFG (MII_CRS) 22 S,O, PU theLED pins.DefaultisMode 1.Allmodes arealsoconfigurableviaregisteraccess.See thetableintheLED InterfaceSection. ThisjumperingoptionsetstheAuto-MDIX mode. By defaultitenablesMDIX. An externalMDIX_EN (MII_RX_ERR) 31 S,O, PU pull-downwilldisableAuto-MDIX mode.

8 PinDescriptions Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 2.8 10 Mb/s and 100 Mb/s PMD Interface PIN TYPE DESCRIPTION NAME NO. Differentialcommon drivertransmitoutput(PMD OutputPair).These differentialoutputsareautomatically configuredtoeither10BASE-T or100BASE-TX signaling. TD –,TD+ 8,9 I/O InAuto-MDIX mode ofoperation,thispaircan be used as theReceiveInputpair.These pinsrequire1.8V or3.3Vbiasforoperation. Differentialreceiveinput(PMD InputPair).These differentialinputsareautomaticallyconfiguredtoaccept either100BASE-TX or10BASE-T signaling. RD –,RD+ 5,6 I/O InAuto-MDIX mode ofoperation,thispaircan be used as theTransmitOutputpair.These pinsrequire 1.8Vor3.3Vbiasforoperation.

2.9 Power and Bias Connections

NAME NO. RBIAS 3 I BiasResistorConnection.Use a 4.99kΩ 1% resistorconnectedfromRBIAS toGND. 1.8VPower Feedback Output.A 1μF capacitor(ceramicpreferred),shouldbe placedclosetotheV18_PFBOUT 40 O V18_PFBOUT. Insinglesupplyoperation,connectthispinshouldbe connectedtoV18_PFBIN1 and V18_PFBIN2 (pin 2 and pin4).See Figure2-1forproperplacementpin. Inmultiplesupplyoperation,when supplying1.8Vfromexternalsupply,thispinshouldbe connected togetherwithVDD33_V18 (pin41),V18_PFBIN1 and V18_PFBIN2 (pin2 and pin4)tothe1.8Vexternal supplysource.See Figure2-2forproperplacementpin. 1.1VAnalogPower Feedback Output.A 1 μF capacitor(Ceramicpreferred),shouldbe placedclosetoVA11_PFBOUT 10 O theVA11_PFBOUT. Insinglesupplyoperationthispinshouldbe connectedtoVA11_PFBIN1 and V11_PFBIN2 (pin1 and pin7).See Figure2-1forproperplacementpin. Inmultiplesupplyoperation,when supplying1.1Vfromexternalsupply,thispinshouldbe connected togetherwithVDD33_VA11 (pin11),V11_PFBIN1 and V11_PFBIN2 (pin1 and pin7)to1.1Vexternal supplysource.See Figure2-3forproperplacementpin. 1.8VPower Feedback Input.These pinsarefedwithpower fromV18_PFBOUT (pin40)insinglesupplyV18_PFBIN1 2 operation. I 1.8Vfromexternalsourceinmultiplesupplyoperation.A small1μF capacitorshouldbe connectedcloseV18_PFBIN2 4 toeach pin. 1.1VAnalogPower Feedback Input.These pinsarefedwithpower from:VA11_PFBOUT (pin10)inVA11_PFBIN1 1 singlesupplyoperation. I 1.1Vfromexternalsourceinmultiplesupplyoperation.A smallcapacitorof0.1μF shouldbe connectedVA11_PFBIN2 7 closetoeach pin. VDD11 20 O 1.1VCore Power Output.A capacitorof1μF (Ceramicpreferred),shouldbe placedclosetotheVDD11 VDD33_IO P I/O3.3VSupply Externalsupplyinputto1.1Vanalogregulator VDD33_VA11 11 P Thispinshouldbe connectedto3.3Vor2.5Vexternalsupply,insinglesupplyoperation. Inmultiplesupplyoperationthispinshouldbe connectedtoexternal1.1Vsupplysource. Externalsupplyinputto1.8Vregulator VDD33_V18 41 P Insinglesupplyoperation,thispinshouldbe connectedtoa 3.3Vor2.5Vexternalsupply.Inmultiple supplyoperationthispinshouldbe connectedtoan external1.8Vsupplysource. Externalsupplyinputto1.1VCore regulator VDD33_VD11 21 P Thispinshouldbe connectedto3.3Vor2.5Vexternalsupply,insinglesupplyoperation. Inmultiplesupplyoperationthispinshouldbe connectedtoexternal1.1Vsupplysource. VSS 38 P Ground pinforOscillator GNDPAD 49 P Ground Pad Copyright© 2009,Texas InstrumentsIncorporated PinDescriptions 9 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

1 : 1 1 : 1 T 1 RJ 45 3.3V Supply TLK100

11 VDD33_V A1 1

10 V A1 1_PFBOUT

1 V A1 1_PFBIN1

V A1 1_PFBIN2

21 VDD33_VD1 1

20 VDD1 1

17VDD33_IO 29VDD33_IO 5RD– RD– RD+ RD+ 49.9/c87

1.0 F/c109

TD– TD– 9TD+ TD+ VDD33_V18 V18_PFBOUT V18_PFBIN1 V18_PFBIN2 49.9/c87 49.9/c87 49.9/c87

0.1 F/c109

0.1 F/c1090.1 F/c109 3.3V Supply 3.3V Supply 0.1 F/c1091.0 F/c109 3.3V Supply 3.3V Supply TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

2.10 Power Supply Configuration

The TLK100 providesbest-in-classflexibilityofpower supplies.

• Singlesupplyoperation– Ifa single3.3Vpower supplyisdesired,theTLK100 willsense thepresence ofthesupplyand configuretheinternalvoltageregulatorstoprovideallnecessarysupplyvoltages.To operateinthismode, connecttheTLK100 supplypinsaccordingtothefollowingscheme: Figure2-1.Power Scheme forSingleSupply Operation
• MultipleSupplyoperation– When additional1.8Vand/or1.1Vexternalpower railsareavailable,the TLK100 can be configuredinvariousways as giveninTable2-1.Thisgivesthehighestflexibilityfor theuserand enablessignificantreductioninpower consumption.When usingmultipleexternal supplies,theinternalregulatorsmust be disabledby appropriatedeviceconnections. – When an external1.8Vrailisavailable– Connecttheexternal1.8VtoallfollowingTLK100 pinsto enableproperoperation:V18_PFBOUT (pin40),V18_PFBIN1 (pin2),V18_PFBIN2 (pin4)and VDD33_V18 (pin41).Inaddition,connectthe1.8Vrailtothetransformercentertaptofurther reducethetransmissionpower,as shown inFigure2-2:

10 PinDescriptions Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

(RD– ) RD – Pin 6 (RD+) RD + 1.8V Supply Pin 8 (TD – ) TD – Pin 9 (TD +) TD + 1 :1 1 :1 T 1 RJ45 Pin 41 (VDD33_ V 18) Pin 40 (V 18_ PFBOUT ) Pin 2 (V 18_ PFBIN ) Pin 4 (V 18_ PFBIN2 ) 1 .8 V Supply TLK100 49.9/c87 49.9/c87 49.9/c87 49.9/c87

0.1 F*/c109

1.8V Supply 1.8V Supply 1.1 V Supply TLK100 Pin□11 (VDD33_VA11) Pin□10 (VA11_PFBOUT) Pin□1 (VA11_PFBIN1) Pin□7 (VA11_PFBIN2) Pin□21 (VDD33_VA11) Pin□20 (VDD11) TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Figure2-2.Power Scheme forOperationWith External1.8VSupply – External1.1Vrail– When external1.1Vrailisavailable– Connecttheexternal1.1Vtothefollowing pins:VA11_PFBOUT (pin10),VDD11 (pin20),VA11_PFBIN1 (pin1),VA11_PFBIN2 (pin7), VDD33_VA11 (pin11)and VDD33_VD11 (pin21)as shown inFigure2-3: Figure2-3.Power Scheme forOperationWith External1.1VSupply

• Lowest-poweroperation– When 1.1Vand 1.8Vsuppliesarealreadyavailableinadditionto3.3V, designerscan takeadvantageofthelowest-powerconfigurationoftheTLK100. By supplyingexternal 1.8and 1.1Vas explainedabove,alltheinternalregulatorsarepowered down and thedeviceisfully drivenby theexternalsuppliesgivingthelowestpower operation. Copyright© 2009,Texas InstrumentsIncorporated PinDescriptions 11 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Other power supply options– Because the TLK100 incorporatesindependentvoltageregulators, designersmay takeadvantageofseveraloptionalconfigurations,dependingon availablepower supplies. See Table2-1fortheseoptions. Table2-1.Power Supply Options Mode Regulator RegulatorsVoltageSource VoltageSource VoltageSource VoltageSource(ON/OFF) (ON/OFF) SingleSupply 3.3Vfrom 3.3Vfrom 3.3Vfrom 3.3VfromON ONOperation externalsupply externalsupply externalsupply externalsupply 3.3Vfrom 3.3Vfrom 3.3Vfrom 2.5VfromON ONexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 3.3Vfrom 3.3Vfrom 1.1VfromON OFFexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 3.3Vfrom 2.5Vfrom 3.3VfromON ONexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 3.3Vfrom 2.5Vfrom 2.5VfromON ONexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 3.3Vfrom 2.5Vfrom 1.1VfromON OFFexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 1.8Vfrom 1.8Vfrom 3.3VfromOFF ONexternalsupply externalsupply externalsupply externalsupply 3.3Vfrom 1.8Vfrom 1.8Vfrom 2.5VfromOFF ONexternalsupply externalsupply externalsupply externalsupply LowestPower 3.3Vfrom 1.8Vfrom 1.8Vfrom 1.1VfromOFF OFFConsumption externalsupply externalsupply externalsupply externalsupply When operatingwithmultiplesupplies,itisrecommended thatthe3.3V supplyramps up atleast200ms beforethe1.8Vand 1.1Vsuppliesramp up.

12 PinDescriptions Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

3 Configuration

This sectionincludesinformationon the variousconfigurationoptionsavailablewiththe TLK100. The configurationoptionsdescribedbelowinclude:

• Auto-Negotiation
• Auto-MDIX
• PHY Address
• LED Interface
• Loopback Functionality
• BIST
• CableDiagnostics

3.1 Auto-Negotiation

The TLK100 devicecan auto-negotiateto operatein10BASE-T or 100BASE-TX. IfAuto-Negotiationis enabled,thentheTLK100 devicenegotiateswiththelinkpartnertodeterminethespeed and duplexwith which to operate.Ifthe linkpartnerisunableto Auto-Negotiate,the TLK100 devicewould go intothe paralleldetectmode todeterminethespeed ofthelinkpartner.Under paralleldetectmode, theduplex mode isfixedathalf-duplex. The TLK100 supportsfourdifferentEthernetprotocols(10 Mb/s HalfDuplex,10 Mb/s FullDuplex,100 Mb/s HalfDuplex,and 100 Mb/s FullDuplex),so the inclusionof Auto-Negotiationensures thatthe highestperformanceprotocolwillbe selectedbased on the advertisedabilityof the LinkPartner.The Auto-NegotiationfunctionwithintheTLK100 can be controlledeitherby internalregisteraccessorby the use oftheAN_EN, AN_1 and AN_0 pins. The stateofAN_EN, AN_0 and AN_1 pinsdetermineswhethertheTLK100 isforcedintoa specificmode or Auto-Negotiationwilladvertisea specificability(orsetofabilities)as giveninTable2-1.These pins allowconfigurationoptionstobe selectedwithoutrequiringinternalregisteraccess.The stateofAN_EN, AN_0 and AN_1, upon power-up/reset,determinesthestateofbits[8:5]oftheANAR register(0x04h). Table3-1.Auto-NegotiationModes AN_EN AN_1 AN_0 Forced Mode 0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN_1 AN_0 AdvertisedMode 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 10BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T, HalfDuplex 100BASE-TX, HalfDuplex 1 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex Copyright© 2009,Texas InstrumentsIncorporated Configuration 13 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com The Auto-Negotiationfunctioncan alsobe controlledby internalregisteraccessusingregistersas defined by theIEEE 802.3uspecification.For furtherdetailregardingAuto-Negotiation,see Clause28 oftheIEEE 802.3uspecification.

3.2 Auto-MDIX

The TLK100 deviceautomaticallydetermineswhetherornotitneeds tocrossoverbetween pairsso that an externalcrossovercable is not required.Ifthe TLK100 device interoperateswith a device that implementsMDI/MDIX crossover,a random algorithmas describedin IEEE 802.3 determineswhich deviceperformsthecrossover. Auto-MDIX isenabledby defaultand can be configuredviajumperor viaPHYCR (0x10h)register,bits [6:5]. The crossovercan be manuallyforcedthroughbit5 ofPHYCR (0x10h)register.NeitherAuto-Negotiation norAuto-MDIX isrequiredtobe enabledinforcingcrossoveroftheMDI pairs. Auto-MDIX can be used in the forced100BT mode but not in the forcedMDIX mode. As in modern networksallthenodes are 100BT, havingtheAuto-MDIX workingintheforced100BT mode willresolve thelinkfasterwithouttheneed forthelongAuto-Negotiation.

14 Configuration Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

2.2□k/c87 VCC PHYAD4□=□0 PHYAD3□=□0 PHYAD2□=□0 PHYAD1□=□1 PHYAD0□=□1 B0314-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

3.3 PHY Address

The 5 PHY address inputspins are shared withthe MII_RXD[3:0]pins and COL pin as shown in Table3-2. Table3-2.PHY Address Mapping PIN # PHYAD FUNCTION RXD FUNCTION

24 PHYAD0 MII_COL

25 PHYAD1 MII_RXD_0

26 PHYAD2 MII_RXD_1

27 PHYAD3 MII_RXD_2

28 PHYAD4 MII_RXD_3

Each TLK100 or portsharingan MDIO bus ina system must have a uniquephysicaladdress.With 5 addressinputpins,theTLK100 can supportPHY Addressvalues0 (<00000>)through31 (<11111>).The address-pinstatesare latchedintoan internalregisteratdevicepower-upand hardwarereset.Because allthePHYAD[4:0] pinshave weak internalpull-downresistors,thedefaultsettingforthePHY addressis 00000 (0x00h). See Figure3-1 foran example of a PHYAD connectionto externalcomponents.In thisexample,the PHYAD configurationresultsinaddress00010 (0x02h). Figure3-1.PHYAD ConfigurationExample Copyright© 2009,Texas InstrumentsIncorporated Configuration 15 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

LED_LINKLED_SPEEDLED_ACT/COL 470 /c87 470 /c87470 /c87 VCC B0315-01 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

3.4 LED Interface

The TLK100 supportsthreeconfigurableLightEmittingDiode (LED) pins.The devicesupportsthreeLED configurations:Link,Speed, and Activity.Functionsare multiplexedamong the LEDs intothreemodes. The LEDs can be controlledby configurationpinand/orinternalregisterbits.Bits6:5oftheLED Direct Controlregister(LEDCR) selectstheLED mode as describedinTable3-3. Table3-3.LED Mode Select LED_CFG[1] LED_CFG[0]Mode LED_LINK LED_SPEED LED_ACT(bit6) (bit5)or (pin22) ON forGood Link ON in100 Mb/s ON PulseforActivity1 don'tcare 1 OFF forNo Link OFF in10 Mb/s OFF forNo Activity ON forGood Link ON in100 Mb/s None2 0 0 BLINK forActivity OFF in10 Mb/s ON forGood Link ON in100 Mb/s ON forFullDuplex3 1 0 BLINK forActivity OFF in10 Mb/s OFF forHalfDuplex The LED_LINK pininMode 1 indicatesthelinkstatusoftheport.ItisOFF when no LINK ispresent.In Mode 2 and Mode 3 itisON toindicateLinkisgood and BLINK toindicateactivityispresenton either transmitor receivechannel.The blinkrateisdecidedby thebits9:8oftheLEDCR register(0x18).The defaultblinkrateis5Hz. The LED_SPEED pinindicates10 or100 Mb/s datarateoftheport.ThisLED isON when thedeviceis operatingin100 Mb/s operation.The functionalityofthisLED isindependentofmode selected. The LED_ACT pininMode 1 indicatesthepresenceofeithertransmitorreceiveactivity.The LED isON (Pulse)forActivityand OFF forNo Activity.The widthofthepulseisdeterminedby thebits14:13ofthe LEDCR register(0x18).The defaultpulsewidthis200ms. Inmode 3 thispinindicatestheDuplexstatus ofoperation.The LED isON forFullDuplexand OFF forHalfDuplex. Bits2:0oftheLEDCR registerdefinesthepolarityofthesignalson theLED pins. SincetheAuto-Negotiation(AN)configurationoptionssharetheLED outputpins,theexternalcomponents requiredforconfiguration-pinprogrammingand thoseforLED usage must be consideredinordertoavoid contention. See Figure3-2 foran example of AN connectionsto externalcomponents.In thisexample,the AN programmingresultsinAuto-Negotiationwith10/100Half/Full-Duplexadvertised. Figure3-2.AN Pin Configurationand LED Loading Example

16 Configuration Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

Digital□Loopback PHY Digital External□Loopback Analog□LoopbackPCS□Loopback XFMR RJ45 M I I MII□Loopback TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

3.5 Loopback Functionality

The TLK100 providesseveraloptionsforLoopback thattestand verifyvariousfunctionalblockswithinthe PHY. Enablingloopbackmode allowsin-circuittestingof the TLK100 digitaland analog data path. Generally,the TLK100 may be configuredto one of the Near-end loopbackmodes or to the Far-end (reverse)loopback.

3.5.1 Near-End Loopback

Near-endloopbackprovidestheabilitytoloopthetransmitteddataback tothereceiverviathedigitalor analogcircuitry.The pointatwhich thesignalisloopedback isselectedusingloopbackcontrolbitswith severaloptionsbeingprovided.Figure3-3shows thePHY near-endloopbackfunctionality. Figure3-3.Block Diagram,Near-End Loopback Mode The Near-end Loopback mode isselectedby settingthe respectivebitin the BIST ControlRegister (BISCR),MII registeraddress0x16.Bits3:0 of the BISCR registerare used to setthe loopbackmode accordingtothefollowing:

• Bit[0]:MIILoopback
• Bit[1]:PCS Loopback (in100BaseTX only)
• Bit[2]:DigitalLoopback
• Bit[3]:AnalogLoopback WhileinLoopback mode thedataisloopedback and alsotransmittedontothemedia.To ensureproper operationinAnalogLoopback mode 100Ω terminationsshouldbe attachedtotheRJ45 connector. ExternalLoopback can be performedwhileworkinginnormalmode (Bits3:0oftheBISCR registerare assertto0 and on RJ45 connectorpin1 isshortedtopin3 and pin2 isshortedtopin6). To maintainthedesiredoperatingmode, Auto-Negotiationshouldbe disabledbeforeselectingLoopback mode. Thisisnotrelevantforexternal-loopbackmode. Copyright© 2009,Texas InstrumentsIncorporated Configuration 17 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

CAT5 Cable Link□Partner M I I Reverse□Loopback TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

3.5.2 Far-End Loopback

Far-end(Reverse)loopbackisa specialtestmode toallowtestingthePHY fromlinkpartnerside.Inthis mode datathatisreceivedfromthelinkpartnerpass throughthePHY's receiver,loopedback on theMII and transmittedback tothelinkpartner.Figure3-4shows Far-endloopbackfunctionality. Figure3-4.Block Diagram,Far-End Loopback Mode The Reverse Loopback mode isselectedby settingbit4 in the BIST ControlRegister(BISCR),MII registeraddress0x16. WhileinReverse Loopback mode thedataisloopedback and alsotransmittedontotheMAC Interface and alldatasignalsthatcome fromtheMAC areignored.

3.6 BIST

The TLK100 incorporatesan internalPRBS Built-inSelfTest (BIST)circuitto accommodate in-circuit testingordiagnostics.The BIST circuitcan be utilizedtotesttheintegrityofthetransmitand receivedata paths.The BIST testingcan be performedusingbothinternalloopback(digitaloranalog)orexternalloop back usinga cablefixture.The BIST simulatesa realdatatransferscenariosusingrealpacketson the lines.The BIST allowsfullcontrolofthepacketslengthsand oftheInterPacketGap (IPG) The BIST isimplementedwithindependenttransmitand receivepaths,withthetransmitblockgenerating a continuousstream of a pseudo random sequence.The TLK100 generatesa 23-bitpseudo random sequence fordoingtheBIST test.The receiveddataiscompared tothegeneratedpseudo-random data by theBIST LinearFeedback ShiftRegister(LFSR) todeterminetheBIST pass/failstatus.The number of errorbytesthatthe PRBS checkerreceivedisstoredin the BISECR register(0x72h).Thenumber of transmittedbytesthatthePRBS checkerreceivedisstoredintheBISBCR register(0x71h).The statusof whetherthePRBS checkerislockedtotheincomingreceivebitstream,whetherthePRBS isinsync or notand whetherthepacketgeneratorisbusy ornotcan be foundby readingtheBISSR register(0x17h). The PRBS testcan be putina continuousmode orsinglemode by usingthebit15 oftheBISCR register (0x16h).Inthecontinuousmode, when one ofthePRBS counterreachesthemaximum valuethecounter startscountingfrom zeroagain.Inthesinglemode when thePRBS counterreachesitsmaximum value thePRBS checkerstopscounting. TLK100 allowstheusertocontrolthelengthofthePRBS packet.By programming theBISPLR register (0x7Bh)registerone can setthelengthofthePRBS packet.There isalsoan optiontogeneratea single packettransmissionof two types64 and 1518 bytesthroughregisterbit– bit13of the BISCR register (0x16h).The singlegeneratedpacketiscomposed ofa constantdata.

18 Configuration Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

3.7 Cable Diagnostics

With the vastdeploymentof Ethernetdevices,the need forreliable,comprehensiveand user-friendly cablediagnostictoolismore importantthanever.The wide varietyofcables,topologies,and connectors deployedresultswiththeneed tonon-intrusivelyidentifyand reportcablefaults.TI cablediagnosticunit providesextensiveinformationaboutcableintegrity. The TLK100 offersthefollowingcapabilitiesinitsCableDiagnostictoolskit: 1. Time Domain Reflectometry(TDR). 2. ActiveLinkCableDiagnostic(ALCD). 3. DigitalSpectrumAnalyzer(DSA)

3.7.1 TDR

The TLK100 uses Time Domain Reflectometry(TDR) todeterminethequalityofthecables,connectors, and terminationsinadditiontoestimationofthecablelength.Some ofthepossibleproblemsthatcan be diagnosedincludeopens,shorts,cableimpedance mismatch,bad connectors,terminationmismatches, and any otherdiscontinuitieson thecable. The TLK100 devicetransmitsa testpulseof known amplitude(1V)down each of the two pairsof an attachedcable.The transmittedsignalcontinuesdown the cable and reflectsfrom each cable imperfection,fault,bad connectorand theend ofthecableitself.AfterthepulsetransmissiontheTLK100 measures thereturntimeand amplitudeofallthesereflectedpulses.Thistechniqueenablesmeasuring the distanceand magnitude(impedance)of non-terminatedcables(open or short),discontinuities(bad connectors),and improperly-terminatedcableswithan accuracyof±1m. To do this,theTLK100 uses a RAM withup to256 samples torecordalltheinputsampled data(Equals to max possiblemeasured cablelengthof over 200m). The TLK100 alsouses softdata averagingto reducenoiseand improveaccuracy.The TLK100 iscapableofrecordingup tofivereflectionswithinthe testerpair.Incase more than5 reflectionswere recordedtheTLK100 willsave thelast5 ofthem. For allTDR measurements,thetransformationbetween timeofarrivaland physicaldistanceisdone by theexternalhostusingminorcomputations(suchas multiplication/additionand lookuptables).The host must know theexpectedpropagationdelayofthecable,whichdepends,among otherthings,on thecable category(e.g.CAT5/CAT5e/CAT6). Copyright© 2009,Texas InstrumentsIncorporated Configuration 19 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

3.7.2 ALCD

The TLK100 alsosupportsActiveLinkCable Diagnostic(ALCD).The ALCD offersa passivemethod to estimatethe cablelengthduringactivelink.Ituses passivedigitalsignalprocessingbased on adapted datathusenablingmeasurement ofcablelengthwithan activelinkpartner. The ALCD alsouses pre-definedparametersaccordingtothecableproperties(e.g.CAT5/CAT5e/CAT6) inordertoachievehigheraccuracyintheestimatedcablelength.The ALCD Cable lengthmeasurement accuracyis+/-5mforthepairused intheRx path(duetothepassivenatureofthetestwe measure only thepairon theRx path).

3.7.3 DSA

The TLK100 alsooffersa unique capabilityof DigitalSpectrum Analyzer(DSA). The DSA enablesa detailedanalysisof the channel frequencyresponse (Magnitudeonly).The DSA has the following capabilities:

• Producechannelfrequencyresponseinresolutionof119.2Hz.
• Save up to512 binsperDSA run.
• Fullcontrolintheanalyzedfrequencybinslocationand resolution.
• Programmable optionsforinputdatafortheDSA: – Use raw datatakendirectlyfromthechannel – Use adapteddatathatpassed digitalsignalprocessing
• Use additionalfilteringforsmoothingthetotalchannelfrequencyresponse.
• Buildinaveragingformore accurateresults NOTE: Foran example oftheDSA outputpleasesee appendixA To resetthecablediagnosticregisters,setbit14 ofRAMCR2 register(0x0D01)to'1'.Writingsoftware globalreset0x001F bit15 does notresetthecablediagnosticregisters.

20 Configuration Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

MII_TX_CLK MII_TX_EN MII_TXD□[3:0] MII_RX_CLK MII_RX_DV MII_RX_ERR MII_RXD□[3:0] MII_CRS MII_COL TLK100 MAC TX_CLK TX_EN TXD□[3:0] RX_CLK RX_DV RX_ER RXD□[3:0] CRS COL TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

4 Interfaces

4.1 Media IndependentInterface(MII)

The Media IndependentInterface(MII)isa synchronous4-bitwide nibbledatainterfacethatconnectsthe PHY totheMAC in100B-TX and 10B-T modes. The MIIisfullycompliantwithIEEE802.3-2002clause22. The MII consistsof the data signalsMII_TXD[3:0]and MII_RXD[3:0],transmitand receivevalidsignals MII_TX_EN and MII_RX_DV, errorsignalMII_RX_ERR and transmit/receiveclocksMII_TX_CLK and MII_RX_CLK. In addition,the interfaceconsistsof asynchronous linestatussignalsMII_CRS and MII_COL, indicatingcarriersense and collision.Data on MII_TXD[3:0]and MII_RXD[3:0]arelatchedwith referencetotheedges ofMII_RX_CLK and MII_TX_CLK clocksrespectivelyas definedintheMIItiming diagrams 22-14 and 22-15 of IEEE802.3-2002clause22. Both clocksare sourced by the PHY. In 100B-TX mode, the MII_RX_CLK and MII_TX_CLK source 25MHz clocksand in 10B-T, they source 2.5MHz clocks. Figure4-1describestheMIIsignalsconnectivity. Figure4-1.MIISignaling The isolateregister0.10definedinIEEE802.3-2002used toelectricallyisolatethePHY from theMII(if set,alltransactionson theMIIinterfaceareignoredby thePHY). Additionally,the MII interfaceincludesthe carriersense signalMII_CRS, as wellas a collisiondetect signalMII_COL. The MII_CRS signalassertstoindicatethereceptionofdatafrom thenetworkor as a functionoftransmitdatainHalfDuplexmode. The MII_COL signalassertsas an indicationofa collision which can occur during half-duplexoperationwhen both transmitand receiveoperationoccur simultaneously. Copyright© 2009,Texas InstrumentsIncorporated Interfaces 21 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

4.2 SerialManagement Interface

The SerialManagement Interface(SMI),providesaccess to the TLK100 ’s internalregistersspace for statusinformationand configuration.The SMI is compatiblewith IEEE802.3-2002 clause 22. The implementedregistersetconsistsofalltheregistersrequiredby theIEEE802.3-2002inadditiontoseveral others,providingadditionalvisibilityand controllabilityoftheTLK100 device. The SMI includestheMDC management clockinputand themanagement MDIO datapin.The MDC clock issourcedby theexternalmanagement entity(alsoreferredtoas STA), and can run atmaximum clock rateof25MHz. MDC isnotexpectedtobe continuous,and can be turnedoffby theexternalmanagement entitywhen thebus isidle. The MDIO issourcedby theexternalmanagement entityand by thePHY. The dataon theMDIO pinis latchedon the risingedge of the MDC clock.The MDIO pinrequiresa pull-upresistor(1.5kΩ) which, duringIDLE and turnaround,pullsMDIO high. Up to32 PHYs can sharea common SMI bus.To distinguishbetween thePHYs, a 5-bitaddressisused. Duringpower-up reset,the TLK100 latchesthe PHYAD[4:0] configurationpins(Pin25 to Pin 28) to determineitsaddress. The management entitymust notstartan SMI transactioninthefirstcycleafterpower-upreset. To maintainlegaloperation,SMI bus shouldremaininactiveatleastone MDC cycleafterhard resetis de-asserted. In normal MDIO transactions,the registeraddress is taken directlyfrom the management frame’s reg_addr field,thusallowingdirectaccess to 32 16-bitregisters(includingthosedefinedinIEEE802.3 and vendorspecific).The datafieldisused forbothreadingand writing. The Startcode isindicatedby a <01> pattern.Thismakes surethattheMDIO linetransitionsfrom the defaultidlelinestate.Turnaroundisdefinedas an idlebittimeinsertedbetween the RegisterAddress fieldand theData field.To avoidcontentionduringa read transaction,no devicemay activelydrivethe MDIO signalduringthefirstbitofTurnaround.The addressedTLK100 drivestheMDIO witha zeroforthe second bitofturnaroundand followsthiswiththerequireddata.Figure4-2shows thetimingrelationship between MDC and theMDIO as driven/receivedby theStation(STA) and theTLK100 (PHY) fora typical registerreadaccess.

22 Interfaces Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

Z Z Z Z Z0 0 0 00 00 00 00 0 00 00 00 00 0 00 01 1 1 11 1 1 Idle Z ZMDIO (ST A) MDIO (PHY) Idle Start Opcode (Read) PHY Address (PHY AD = 0Ch) Register Address (00h = BMCR) MDC ZZMDIO (ST A) T A Register Data Z Z0 1 0 00 00 00 00 0 00 01 00 00 0 0 00 01 1 0 00 1 0 IdleIdle Start Opcode (Read) PHY Address (PHY AD = 0Ch) Register Address (00h = BMCR) TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 For writetransactions,the station-managemententitywritesdata to the addressed TLK100, thus eliminatingtherequirementforMDIO Turnaround.The Turnaroundtimeisfilledby themanagement entity by inserting<10>. Figure4-3 shows the timingrelationshipfora typicalMII registerwriteaccess.The framestructureand generalread/writetransactionsareshown inTable4-1,Figure4-2,and Figure4-3. Table4-1.TypicalMDIO Frame Format MIIManagement SerialProtocol <idle><start><op code><deviceaddr><reg addr><turnaround><data><idle> Figure4-2.TypicalMDC/MDIO Read Operation Figure4-3.TypicalMDC/MDIO WriteOperation

4.2.1 Extended Address Space Access

The TLK100 SMI functionsupportsread/writeaccess to the extended registerset using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirectmethod definedinIEEE802.3ahDraftforclause22 foraccessingtheclause45 extendedregisterset. Accessingthestandardregisterset,i.e.MDIO registers0 to31,can be performedusingthenormaldirect MDIO access or theindirectmethod,exceptforregisterREGCR(0x000Dh) and ADDAR(0x000Eh) which can be accessedonlyusingthenormalMDIO transaction.The SMI functionwillignoreindirectaccesses totheseregisters. REGCR(0x000Dh) istheMDIO Manageable MMD accesscontrol.Ingeneral,registerREGCR(4:0) isthe deviceaddressDEVAD thatdirectsany accessesofADDAR(0x000Eh) registertotheappropriateMMD. Specifically,the TLK100 uses the vendor specificDEVAD[4:0] = "11111" foraccesses.Allaccesses throughregistersREGCR and ADDAR shoulduse thisDEVAD. TransactionswithotherDEVAD are ignored.REGCR[15:14] holdstheaccess function:address(00),datawithno postincrement(01),data withpostincrementon readand writes(10)and datawithpostincrementon writesonly(11). Copyright© 2009,Texas InstrumentsIncorporated Interfaces 23 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

• ADDAR istheaddress/dataMMD register.Itisused inconjunctionwithREGCR toprovidetheaccess totheextendedregisterset.IfregisterREGCR[15:14] is00,thenADDAR holdstheaddressofthe extendedaddressspace register.Otherwise,ADDAR holdsthedataas indicatedby thecontentsofits addressregister.When REGCR[15:14] issetto00,accessestoregisterADDAR modifytheextended registersetaddressregister.Thisaddressregistershouldalwaysbe initializedinordertoaccessany oftheregisterwithintheextendedregisterset.
• When REGCR[15:14] issetto01,accessestoregisterADDAR accesstheregisterwithintheextended registersetselectedby thevalueintheaddressregister.
• When REGCR[15:14] issetto10,accesstoregisterADDAR accesstheregisterwithintheextended registersetselectedby thevalueintheaddressregister.Afterthataccessiscomplete,forbothreads and writes,thevalueintheaddressregisterisincremented.
• When REGCR[15:14] issetto11,accesstoregisterADDAR accesstheregisterwithintheextended registersetselectedby thevalueintheaddressregister.Afterthataccessiscomplete,forwrite accessesonly,thevalueintheaddressregisterisincremented.Forreadaccesses,thevalueofthe addressregisterremainsunchanged. The followingsectionsdescribehow to performoperationson the extendedregistersetusingregister REGCR and ADDAR.

4.2.1.1 WriteAddress Operation

To settheaddressregister: 1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. SubsequentwritestoregisterADDAR (step2)continuetowritetheaddressregister.

4.2.1.2 Read Address Operation

To readtheaddressregister: 1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. Read theregisteraddressfromregisterADDAR. SubsequentreadstoregisterADDAR (step2)continuetoreadtheaddressregister.

24 Interfaces Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

4.2.1.3 Write(no post increment)Operation

To writean extendedregistersetregister: 1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x401F (data,no postincrementfunctionfield= 01,DEVAD = 31)toregisterREGCR. 4. WritethecontentofthedesiredextendedregistersetregistertoregisterADDAR. SubsequentwritestoregisterADDAR (step4)continuetorewritetheregisterselectedby thevalueinthe addressregister. Note:steps(1)and (2)can be skippediftheaddressregisterwas previouslyconfigured.

4.2.1.4 Read (no post increment)Operation

To readan extendedregistersetregister: 1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x401F (data,no postincrementfunctionfield= 01,DEVAD = 31)toregisterREGCR. 4. Read thecontentofthedesiredextendedregistersetregistertoregisterADDAR. SubsequentreadsfromregisterADDAR (step4)continuereadingtheregisterselectedby thevalueinthe addressregister. Note:steps(1)and (2)can be skippediftheaddressregisterwas previouslyconfigured.

4.2.1.5 Write(postincrement)Operation

1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. WritetheregisteraddressfromregisterADDAR. 3. Writethevalue0x801F (data,postincrementon readsand writesfunctionfield= 10,DEVAD = 31)or thevalue0xC01F (data,postincrementon writesfunctionfield= 11.DEVAD = 31)toregisterREGCR. 4. WritethecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent writestoregisterADDAR (step4) writethenexthigheraddresseddataregisterselectedby thevalueoftheaddressregister,i.eaddressregisterisincrementedaftereach access.

4.2.1.6 Read (postincrement)Operation

To read an extendedregistersetregisterand automaticallyincrementthe addressregisterto the next highervaluefollowingthewriteoperation: 1. Writethevalue0x001F (addressfunctionfield= 00,DEVAD = 31)toregisterREGCR. 2. WritethedesiredregisteraddresstoregisterADDAR. 3. Writethevalue0x801F (data,postincrementon readsand writesfunctionfield= 10,DEVAD = 31)to registerREGCR. 4. Read thecontentofthedesiredextendedregistersetregistertoregisterADDAR. Subsequent readstoregisterADDAR (step4) read thenexthigheraddresseddataregisterselectedby thevalueoftheaddressregister,i.eaddressregisterisincrementedaftereach access. Copyright© 2009,Texas InstrumentsIncorporated Interfaces 25 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

decoding DeScrambler NRZI to NRZ Convertor MLT-3 decoding DSP (BLW Correction, Adapt. Equal) ADC (Filter, Amplifierl) 10Base T Receive Filter Transmit Receive MII 100Base TX 10Base-T Adv. Link Monitor TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

5 Architecture

The TLK100 Fast Ethernettransceiverisphysicallayercore forEthernet100Base-TX and 10Base-T applications.Itcontainsallthe activecircuitryrequiredto implement the physicallayerfunctionsto transmitand receivedataon standardCAT 3 and 5 unshieldedtwistedpair.The coresupportstheIEEE 802.3StandardFastMedia IndependentInterface(MII)fordirectconnectiontoa MAC/Switch port. The TLK100 uses mixed signalprocessingtoperformequalization,datarecoveryand errorcorrectionto achieve robustand low power operationover the existingCAT 5 twistedpairwiring.The TLK100 architecturenotonlymeets therequirementsofIEEE802.3,butmaintainsa highlevelofmarginoverthe IEEE requirementsforNEXT and Aliennoise. Figure5-1.PHY Architecture

5.1 TransmitPath Encoder

In10Base-T,theMAC feedsthe10Mbps transmitdatathroughtheMIIin4-bitwide nibbles.The datais serializedusingan NRZI converter;Manchesterencoded and senttoDAC tobe transmittedthroughone ofthetwistedpairsofthecable.When no dataisavailablefrom theMAC, the10B-T encodertransmits NLP pulsestokeep thelinkalive. In100Base-TX,theMAC feedsthe100Mbps transmitdatain4-bitwide nibblesthroughtheMIIinterface. The dataisencoded into5-bitcode groups,encapsulatedwithcontrolcode symbols and serialized.The control-codesymbolsindicatethestartand end oftheframeand code otherinformationsuch as transmit errors.When no dataisavailablefromtheMAC, IDLE symbolsareconstantlytransmitted.The serialized bitstreamisfedintoa scrambler.The scrambleddatastreampasses throughan NRZI encoderand then throughan MLT3 encoder.Finally,itisfedtotheDAC and transmittedthroughone ofthetwistedpairsof thecable. 5.1.1 4B/5B Encoding The transmitdata thatisreceivedfrom the MAC firstpasses throughthe 4B/5B encoder.This block encodes 4-bitnibbleinto5-bitcode-groupsaccordingtotheTable5-1.Each 4-bitdatanibbleismapped to 16 ofthe32 possiblecode-groups.The remaining16 code-groupsareeitherused forcontrolinformation ortheyareconsideredas notvalid. The code-groupencoder substitutesthe first8-bitsof the MAC preamble witha J/K code-grouppair (11000 10001) upon transmission.The code-group encoder continuesto replacesubsequent 4-bit preambleand datanibbleswithcorresponding5-bitcode-groups.At theend ofthetransmitpacket,upon the de-assertionof TransmitEnable signalfrom the MAC, the code-groupencoder adds the T/R code-grouppair(0110100111)indicatingtheend oftheframe.

26 Architecture Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Afterthe T/R code-grouppair,the code-groupencoder continuouslyadds IDLEs intothe transmitdata streamuntilthenexttransmitpacketisdetected. Table5-1.4B/5B Code Table 4-BitCode Symbol 5-BitCode 0000 0 11110 0001 1 01001 0010 2 10100 0011 3 10101 0100 4 01010 0101 5 01011 0110 6 01110 0111 7 01111 1000 8 10010 1001 9 10011

1010 A 10110

1011 B 10111

1100 C 11010

1101 D 11011

1110 E 11100

1111 F 11101

DESCRIPTION Symbol (1) 5-BitCode Inter-PacketIDLE I 11111 FirstnibbleofSSD J 11000 Second nibbleofSSD K 10001 FirstnibbleofESD T 01101 Second nibbleofESD R 00111 TransmitErrorSymbol H 00100 INVALID CODES V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 (1) Controlcode-groupsI,J,K,T and R indatafieldswillbe mapped as invalidcodes,togetherwith RX_ER asserted.

5.1.2 Scrambler

The purposeofthescrambleristoflattenthepower spectrumofthetransmittedsignal,thusreduceEMI. The scramblerseed isgeneratedwithreferenceto the PHY addressso thatmultiplePHYs thatreside withinthesystemwillnotuse thesame scramblersequence. Copyright© 2009,Texas InstrumentsIncorporated Architecture 27 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

5.1.3 NRZI and MLT-3 Encoding

To comply withtheTP-PMD standardfor100BASE-TX transmissionoverCAT-5 unshieldedtwistedpair cable,thescrambleddatamust be NRZI encoded.The serialbinarydatastreamoutputfrom theNRZI encoder is furtherencoded to MLT-3. MLT-3 is a tri-levelcode where a change in the logiclevel representsa code bit'1'and thelogicoutputremainingatthesame levelrepresentsa code bit'0'.

5.1.4 DigitaltoAnalog Converter

The multipurposeprogrammable transmitDigitalto Analog Converter(DAC) receivesdigitalcoded symbolsand generatesfilteredanalogsymbolstobe transmittedon theline.In100B-TX theDAC applies a low-passshapingfiltertominimizeEMI. The DAC isdesignedtoimprovethereturnlossrequirements and enabletheuse oflow-costtransformers. Digitalpulse-shapefilteringisalsoappliedinordertoconformtothepulsemasks definedby standardand toreduceEMI and highfrequencysignalharmonics. In10Base-T,theManchestercoded symbolsarefedthrougha pre-equalizationfilter.

5.2 Receive Path Decoder

In10B-T,afterthefarend clockisrecovered,thereceivedManchestersymbols pass totheManchester decoder.The serialdecoded bitstream isalignedto the startof the frame,de-serializedto 4-bitwide nibblesand senttotheMAC throughtheMII. In100B-TX,theadaptiveequalizerdrivesthereceivedsymbolstotheMLT3 decoder.The decoded NRZ symbolsaretransferredtothedescramblerblockforde-scramblingand de-serialization.

5.2.1 Analog FrontEnd

The ReceiverAnalogFrontEnd (AFE) residesinfrontofthe100B-TX receiver.Itconsistsofan Analogto DigitalConverter(ADC),receivefiltersand a Programmable Gain Amplifier(PGA). The ADC samples theinputsignalatthe125MHz clockrecoveredby thetimingloopand feedsthedata intotheadaptiveequalizer.The ADC isdesignedtooptimizetheSNR performanceatthereceiverinput whileutilizinghigh power-supplyrejectionratioand maintaininglow power. There isonlyone ADC in TLK100, which receivesthe analog inputdata from the relevantcable pair,accordingto MDI-MDIX resolution. The PGA, digitallycontrolledby the adaptiveequalizer,fullyutilizesthe dynamic range of the ADC by adjustingthe incoming-signalamplitude.Generally,the PGA attenuatesshort-cablestrongsignalsand amplifieslong-cableweak signals.

5.2.2 AdaptiveEqualizer

The adaptiveequalizerremoves Inter-SymbolInterference(ISI)fromthereceivedsignalintroducedby the channel and analog Tx/Rx filters.The TLK100 includesboth Feed Forward Equalization(FFE) and DecisionFeedback Equalization(DFE).The combinationofthebothadaptivemodules withtheadaptive gain controlresultsin a powerfulequalizerthatcan eliminateISI and compensate over the cable attenuationforcablesofup to200m and even more.Inaddition,theEqualizerincludesa ShiftGear Step mechanism to providefastconvergenceon the one hand and smallresidual-adaptivenoiseinSteady stateon theotherhand.

5.2.3 BaselineWander Correction

The DC offsetofthetransmittedsignalisshifteddown orup based on thepolarityofthetransmitteddata because the MLT-3 data iscoupledonto the CAT 5 cablethrougha transformerthatishigh-passin nature.Thisphenomenon iscalledBaselinewander.To preventcorruptionofthereceiveddatabecause ofthisphenomenon, thereceivercorrectsthebaselinewander and can receivetheANSI TP-PMD defined "killerpacket"withno biterrors.

28 Architecture Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

5.2.4 NRZI and MMLT-3 Decoding

The TLK100 decodes the MLT-3 informationfrom the DigitalAdaptiveEqualizerblockto binaryNRZI data.The NRZI-to-NRZdecoderisused topresentNRZ-formatteddatatothedescrambler.

5.2.5 Descrambler

The descrambleris used to descramble the receivedNRZ data.Itis furtherdeserializedand the parallelizeddata is alignedto 5-bitcode-groupsand mapped into4-bitnibbles.At initialization,the 100B-TX descrambleruses the IDLE-symbolssequence to lockon the far-endscramblerstate.During thattime,neitherdata transmissionnor receptionis enabled.Afterthe far-endscramblerstateis recovered,thedescramblerconstantlymonitorsthedataand checks whetheritstillsynchronized.If,for any reason,synchronizationislost,the descramblertriesto re-acquiresynchronizationusingthe IDLE symbols. 5.2.6 45/5B Decoder The code-groupdecoderfunctionsas a lookup tablethattranslatesincoming5-bitcode-groupsinto4-bit nibbles.The code-groupdecoderfirstdetectstheJ/Kcode-grouppairprecededby IDLE code-groupsand replacesthe J/K witha MAC preamble.Specifically,the J/K 10-bitcode-grouppairisreplacedby the nibblepair(01010101).Allsubsequent5-bitcode-groupsareconvertedtothecorresponding4-bitnibbles forthedurationoftheentirepacket.Thisconversionceasesupon thedetectionoftheT/R code-grouppair denotingtheEnd-of-StreamDelimiter(ESD),oron thereceptionofa minimum oftwo IDLE code-groups.

5.2.7 Timing Loop and Clock Recovery

The receivermust lockon thefar-endtransmitterclockinordertosample thedataattheoptimum timing. The timingloop recoversthe far-endclockfrequencyand offsetfrom the receiveddata samples and tracksinstantaneousphase driftscaused by timingjitter. The TLK100 has a robustadaptive-timingloop(Tloop)mechanism thatisresponsiblefortrackingthe Far-EndTX clockand adjustingtheAFE samplingpointtotheincomingsignal.The Tloopimplementsan advanced trackingmechanism thatwhen combined withdifferentavailablephases,alwayskeeps trackof theoptimizedsamplingpointforthedata,and thusoffersa robustRX pathtobothPPM and Jitter.The TLK100 iscapableofdealingwithPPM and jitteratlevelsfarhigherthanthosedefinedby thestandard.

5.2.8 Phase-Locked Loops (PLL)

In 10B-T the digitalphase lockloop (DPLL) functionrecoversthe far-endlink-partnerclockfrom the receivedManchestersignalThe DPLL isabletocombat clockjitteringofup to±18ns and frequencydrifts of ±500ppm between the localPHY clockand the far-endclock.The DPLL feedsthe decoder witha decoded serialbitstream. The integratedanalogPhase-LockedLoop (PLL)providestheclockstotheanalogand digitalsectionsof thePHY. The PLL isdrivenby an externalreferenceclock(sourcedattheXI,XO pins).

5.2.9 LinkMonitor

The TLK100 implementsthe linkmonitorSM as definedby the IEEE 802.3 100BASE-TX Standard.In addition,the TLK100 enables severaladd-ons to the linkmonitorState Machine(SM) activatedby configurationbits.These add-ons are supplementaryto the IEEE standardand are enabledby default. The new add-onsincludetherecoverystatewhichenablesthePHY toattemptrecoveryintheeventofa temporaryenergy losssituationor linkfailurebeforeenteringLINK_FAIL state,and thus,restartingthe whole linkestablishmentprocedure.Thisallowssignificantreductionoftherecoverytimeifthetemporary linkislost. To move to the LINK_DOWN state,the linkmonitorstatemachine relieson variouscriteriasuch as descramblersynchronizationfailure,SNR, and energy indications.These criteriaallowthe TLK100 to reachthefastlinkdown timemode when required. Copyright© 2009,Texas InstrumentsIncorporated Architecture 29 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

5.2.10 SignalDetect

The signaldetectfunctionof the TLK100 isincorporatedto meet the specificationsmandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholdsand timingparameters. The energy-detectormodule providessignal-strengthindicationinvariousscenarios.Because itisbased on an IIRfilter,thisrobustenergydetectorhas excellentreactiontimeand reliability.The filteroutputis compared topredefinedthresholdsinordertodecidethepresenceorabsence ofan incomingsignal. The energydetectoralsoimplementshysteresistoavoidjitteringinthesignal-detectindication.Inaddition ithas fully-programmablethresholdsand listening-timeperiods,enablingshorteningofthereactiontimeif required.

5.2.11 Bad SSD Detection

A Bad StartofStream Delimiter(Bad SSD) isany transitionfromconsecutiveidlecode-groupstonon-idle code-groupswhich isnotprefixedby thecode-grouppair/J/K.Ifthisconditionisdetected,theTLK100 assertsMII_RX_ERR presentsMII_RXD[3:0]= 1110 totheMIIforthecyclesthatcorrespondtoreceived 5B code-groupsuntilatleasttwo IDLE code groupsaredetected.Inaddition,theFCSCR register(0x42h) isincrementedby one foreveryerrorinthenibble. When atleasttwo IDLE code groupsaredetected,RX_ER and MII_CRS become de-asserted. 5.3 10M Squelch The squelchfeaturedetermineswhen validdataispresenton thedifferentialreceiveinputs.The TLK100 implementsa squelchto preventimpulsenoiseon the receiveinputsfrom beingmistakenfora valid signal.Squelchoperationisindependentofthe10BASE-T operatingmode. The squelchcircuitryemploys a combinationof amplitudeand timingmeasurements (as specifiedin the IEEE 802.3 10BASE-T standard)todeterminethevalidityofdataon thetwisted-pairinputs. The signalatthestartofa packetischecked by thesquelch,and any pulsesnotexceedingthesquelch level(eitherpositiveor negative,dependingupon polarity)are rejected.When thisfirstsquelchlevelis exceeded correctly,theoppositesquelchlevelmust thenbe exceeded no earlierthan50ns.Finally,the signalmust again exceed the originalsquelchlevelno earlierthan 50ns to qualifyas a validinput waveform,and notbe rejected.Thischeckingprocedureresultsinthetypicallossofthreepreamblebits at the beginningof each packet.When the transmitteris operating,fiveconsecutivetransitionsare checkedbeforeindicatingthatvaliddataispresent.Atthistime,thesquelchcircuitryisreset.

5.3.1 CollisionDetection

When inHalf-Duplexmode, a 10BASE-T collisionisdetectedwhen receiveand transmitchannelsare activesimultaneously.Collisionsarereportedby theMII_COL signalon theMII. The MII_COL signalremainssetforthedurationofthecollision.IfthePHY isreceivingwhen a collisionis detected,itisreportedimmediately(throughtheMII_COL pin).

5.3.2 CarrierSense

CarrierSense (MII_CRS) may be asserteddue to receiveactivityaftervaliddata isdetectedviathe squelch function.For 10Mb/s Half Duplex operation,MII_CRS is asserted during eitherpacket transmissionor reception.For 10Mb/s FullDuplex operation,MII_CRS isassertedonlyduringreceive activity. MII_CRS isde-assertedfollowingan end-of-packet.

30 Architecture Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

5.3.3 Jabber Function

Jabberisa conditioninwhicha stationtransmitsfora periodoftimelongerthanthemaximum permissible packetlength,usuallydue to a faultcondition.The jabberfunctionmonitorsthe TLK100 outputand disablesthetransmitterifitattemptstotransmita packetoflongerthanlegalsize.A jabbertimermonitors thetransmitterand disablesthetransmissionifthetransmitterisactiveforapproximately100ms. When disabledby theJabberfunction,thetransmitterstaysdisabledfortheentiretimethattheENDEC module'sinternaltransmitenableisasserted.Thissignalmust be de-assertedforapproximately500ms (theunjabtime)beforetheJabberfunctionre-enablesthetransmitoutputs. The Jabberfunctionisonlyavailableand activein10BASE-T mode.

5.3.4 Automatic LinkPolarityDetectionand Correction

Swapping thewireswithinthetwistedpaircauses polarityerrors.Wrong polarityaffectsthe10B-T PHYs. The 100B-TX is invulnerableto polarityproblems because ituses MLT3 encoding.The 10B-T automaticallydetectsreversedpolarityaccordingtothereceivedlinkpulsesordata. 5.3.5 10Base-T Transmitand Receive Filtering External10BASE-T filtersarenotrequiredwhen usingtheTLK100, as therequiredsignalconditioningis integratedintothedevice.Only isolationtransformersand impedance matchingresistorsarerequiredfor the10BASE-T transmitand receiveinterface.The internaltransmitfilteringensuresthatalltheharmonics inthetransmitsignalareattenuatedby atleast30dB. 5.3.6 10Base-T OperationalModes The TLK100 has two basic10BASE-T operationalmodes:

• HalfDuplexmode – InHalfDuplexmode theTLK100 functionsas a standardIEEE 802.310BASE-T transceiversupportingtheCSMA/CD protocol.
• FullDuplexmode – InFullDuplexmode theTLK100 iscapableofsimultaneouslytransmittingand receivingwithoutassertingthecollisionsignal.The TLK100 10 Mb/s ENDEC isdesignedtoencode and decode simultaneously.

5.4 Auto MDI/MDI-X Crossover

The auto MDI/MDI-X crossoverfunctiondetectswire crossover(alsoreferredto as MDI/MDI-X).It automaticallyperformsthepairswaps such thateach transmitterisconnectedtoitslinkpartnerreceiver and viceversa,withoutusing an externalcrossed cable.The auto MDI/MDI-X crossoverfunctionis capableofestablishinga linkwithPHYs thatdo notimplementa crossovermechanism. Table5-2.MDI/MDI-X PairSwaps Combinations MDI MDI-X PIN 10B-T 100B-TX 10B-T 100B-TX TD ± (pin8,9) TD TD RD RD RD ± (pin5,6) RD RD TD TD Detectinglinkpulsesor energy on one or more of the MDI pinsdeterminesthe crossoverstateand whetherthereisa need toperforma swap. IfbothlinkpartnersimplementtheMDI/MDI-X crossover,then a random algorithm,compliantwithone describedinIEEE 802.3section40.4.4isused.Iftheotherlink partnerisa legacy10B-T PHY then the same algorithmisused. Ifthe otherlinkpartnerisa legacy 100B-TX PHY, thenthecrossoverstateisdeterminedaccordingtothesignaldetectionfunction. As described,thelinkpartners’configurationand abilities,whethertheyuse theautonegotiationand/or activatea crossovermechanism, greatlyinfluencethe method picked by the crossoverfunctionto Copyright© 2009,Texas InstrumentsIncorporated Architecture 31 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com determineifand how tocross.Insome oftheconfigurations,theremay be situationsinwhichthelinkis notestablished.Particularly,itmay occuriftheTLK100 isforcedtooperatein10B-T or100B-TX modes (auto-negotiationisdisabled)and the otherlinkpartneractivatesauto-negotiation.For thatreason,itis recommended todisabletheautoMDI/MDI-X functionpriortodisablingtheauto-negotiation.However,the userhas thefullabilitytocontroltheautonegotiationand theautoMDI/MDIX independently. The cross-overmechanism can be turnedoffand forcedtotheMDI orMDI-X stateby settingconfiguration pinMDIX_EN (Pin31),whose stateislatchedduringpower-upreset.When MDIX_EN issetto‘0’,then thecrossovermechanism isdisabledand thePHY operatesinMDI orMDI/X mode respectively.Ifthepin issetto'1',thenthecross-overmechanism isenabledand MDI/MDI-X stateisselectedduringoperation. The auto MDI/MDI-X crossoverfunctionis controlledby registerPHYCR(0x10) bits[6:5].MDI/MDI-X statuscan be readthroughregisterPHYSR(0x11) bit8.

5.5 Auto Negotiation

5.5.1 Operation

The auto negotiationfunction,describedin detailin IEEE802.3 chapter28, providesthe means to exchange informationbetween two devicesand automaticallyconfigureboth of them to takemaximum advantage of theirabilities.The auto negotiationuses the 10B-T linkpulses.Itencapsulatesthe transmitteddatainsequence ofpulses,alsoreferredtoas a FastLinkPulses(FLP)burst.The FLP Burst consistsofa seriesofcloselyspaced 10B-T linkintegritytestpulsesthatform an alternatingclock/data sequence.Extractionof the data bitsfrom the FLP Burstyieldsa LinkCode Word thatidentifiesthe operationalmodes supportedby the remote device,as wellas some informationused forthe auto negotiationfunction’s handshake mechanism. The informationexchanged between the devicesduringthe auto-negotiationprocess consistsof the devices'abilitiessuch as duplexsupportand speed.Itallowshigherlevelsofthenetwork(MAC) tosend totheotherlinkpartnervendor-specificdata(viatheNext Page mechanism, see below),and providesthe mechanism forbothpartiestoagreeon thehighestperformancemode ofoperation. When autonegotiationhas started,theTLK100 transmitsFLP on one twistedpairand listenson theother, thustryingtofindoutwhethertheotherlinkpartnersupportstheautonegotiationfunctionas well.The decisionon what pairtotransmit/listendepends on theMDI/MDI-X state.Iftheotherlinkpartneractivates auto negotiation,then the two partiesbeginto exchange theirinformation.Ifthe otherlinkpartnerisa legacyPHY or does not activatethe auto negotiation,then the TLK100 uses the paralleldetection function,as describedin IEEE802.3 chapters40 and 28, to determine10B-T or 100B-TX operation modes. BMCR Registerbit6 reportswhether the linkwas establishedusingthe auto negotiationor paralleldetectionfunctions.

5.5.2 Initializationand Restart

The TLK100 initiatestheautonegotiationfunctionifitisenabledthroughtheconfigurationjumperoptions AN_EN, AN_1 and AN_0 (pins34,35,36)and one ofthefollowingeventshas happened: 1. Hardware resetde-assertion. 2. Softwarereset(viaregister). 3. Autonegotiationrestart(viaregisterBMCR (0x0000h)bit9). 4. Power-upsequence (viaregisterBMCR (0x0000h)bit11 ). The auto-negotiationfunctionisalsoinitiatedwhen theauto-negotiationenablebitissetinregisterBMCR (0x0000h)bit12 and one ofthefollowingeventshas happened: 1. Softwarerestart. 2. Transitioningtolink_failstate,as describedinIEEE802.3.

32 Architecture Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 To disabletheauto-negotiationfunctionduringoperation,clearregisterBMCR (0x0000h)bit12.During operation,setting/resettingthisregisterdoes not affectthe TLK100 operation.For the changes to take place,issuea restartcommand throughregisterBMCR (0x0000h)bit9.

5.5.3 ConfigurationBits

The auto-negotiationoptionscan be configuredthroughtheconfigurationbitsAN_EN, AN_1 and AN_0 as describedinTable5-3.The configurationbitsallowtheusertodisable/enabletheautonegotiation,and selectthedesirableadvertisementfeatures. Duringhardware/softwarereset,thevaluesoftheseconfigurationbitsarelatchedintotheauto-negotiation registersand availableforuserreadand modification. Table5-3.Auto-NegotiationModes AN_EN AN_1 AN_0 Forced Mode 0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN1 AN0 AdvertisedMode 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 10BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T,Half-Duplex 100BASE-TX, Half-Duplex 1 1 1 10BASE-T,Half/Full-Duplex 100BASE-TX, Half/Full-Duplex

5.5.4 Next Page Support

The TLK100 supportstheoptionalfeatureofthetransmissionand receptionofauto-negotiationadditional (vendorspecific)nextpages. Ifnextpages areneeded,thentheusermust setregisterANAR(0x0004h) bit15 to'1'.The nextpages are thensentand receivedthroughregistersANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively.The usermust pollregisterANER(0x0006h) bit1 tocheck whethera new page has been received,and then read registerANLNPTR forthereceivednextpage'scontent.Only afterregisterANLNPTR isread may theuserwritetoregisterANNPTR thenextpage tobe transmitted.AfterregisterANNPTR iswritten,new nextpages overwritethecontentsofregisterANLNPTR. IfregisterANAR(0x0004h) bit15 isset,thenthenextpage sequence iscontrolledby theuser,meaning thattheauto-negotiationfunctionalwayswaitsforregisterANNPTR tobe writtenbeforetransmittingthe nextpage. Ifadditionaluser-definednextpages aretransmittedand thelinkpartnerhas more nextpages tosend,it istheuser'sresponsibilitytokeep writingnullpages (ofvalue0x2001)toregisterANNPTR untilthelink partnernotifiesthatithas sentitslastpage (bysettingbit15 ofitstransmittednextpage tozero). Copyright© 2009,Texas InstrumentsIncorporated Architecture 33 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

6 Reset and Power Down Operation

At power up itisrecommended tohave theexternalresetpin(RESETN) active(low).The RESETN pin shouldbe de-asserted200μs afterthepower isramped up toallowtheinternalcircuitstosettleand for theinternalregulatorstobe stabilized.Ifrequiredduringnormaloperation,thedevicecan be resetby a hardwareorsoftwarereset.

6.1 Hardware Reset

A hardwareresetisaccomplishedby applyinga low pulse(TTL level),witha durationofatleast1μs,to theRESETN. Thiswillresetthedevicesuch thatallregisterswillbe reinitializedtodefaultvaluesand the hardwareconfigurationvalueswillbe re-latchedintothedevice(similartothepower-up/resetoperation).

6.2 SoftwareReset

A softwareresetisaccomplishedby settingtheresetbit(bit15) oftheBMCR register(0x00h).Thisbit onlyresetstheIEEE definedstandardregistersintheaddressspace 0x00h to0x07h.The softwareglobal resetisaccomplishedby settingbit15 of registerPDN (0x001F)to ‘1’. This bitresetsIEEE defined registers(0x00h to 0x07h) and allthe extendedregistersexceptforthe cable-diagnosticregistersand RAM registers.For resettingthe cable diagnosticsand RAM registers,bit14 of registerRAMCR2 (0x0D01)shouldbe setto ‘1’. The timefrom the pointwhen the resetbitissetto the pointthe when softwareresethas concludedisapproximately1.3μs. The softwareglobalresetresetsthe devicesuch thatallregistersare resetto defaultvaluesand the hardwareconfigurationvaluesare maintained.Softwaredrivercode must wait3 μs followinga software resetbeforeallowingfurtherserialMIIoperationswiththeTLK100.

6.3 Power Down/Interrupt

The Power Down and Interruptfunctionsare multiplexedon pin42 of the device.By default,thispin functionsas a power down inputand theinterruptfunctionisdisabled.Thispincan be configuredas an interruptoutputpinby settingbit15 (INTN_OE) to‘1’and bit12 (INTN_OEN) to‘0’oftheMINTCR (0x14h) register.Bit13 ofthesame MINTCR registerisused tosetthepolarityoftheinterrupt.

6.3.1 Power Down ControlMode

The PWRDNN/INT pincan be assertedlow toputthedeviceina Power Down mode. An externalcontrol signalcan be used todrivethepinlow,overcomingtheweak internalpull-upresistor.Alternatively,the devicecan be configuredtoinitializeintoa Power Down stateby use ofan externalpulldownresistoron thePWRDNN/INT pin.

6.3.2 InterruptMechanisms

The interruptfunctioniscontrolledviaregisteraccess.Allinterruptsourcesare disabledby default.The MINTMR registerprovidesindependentinterruptenable bitsforthe differentinterruptssupportedby TLK100. The PWRDNN/INT pinisasynchronouslyassertedlow when an interruptconditionoccurs.The sourceoftheinterruptcan be determinedby readingtheinterruptstatusregisterMINTSR (0x13h).One or more bitsinthe MINTSR willbe set,denotingallcurrentlypendinginterrupts.Reading of the MINTSR clearsALL pendinginterrupts.

34 Resetand Power Down Operation Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

6.4 Power Down Modes

TLK100 supportsfourtypesof power savingmodes. The lowestpower consumptionisinthe "Extreme Low Power" mode (ELP).To enterintotheELP mode thePWRDNN/INT pinispulledLOW. To enable the power-down modes describedbelow,set bit11 of registerBMCR (0x00h)to '1'.In all power-down modes, theentirePHY ispowered down exceptfortheSMI interface;thePHY staysinthat conditionas longas thevalueofbit11 ofregisterBMCR (0x00h)remains'1'.When thisbitiscleared,the PHY powers up and returnstothelaststateitwas inbeforeitwas powered down. In General Power Down mode, bits9 and 8 of the PHYCR register(0x10h)should be set to "01". Additionally,bit4 ofthePHYCR register(0x10h)shouldbe setto'1'so as topower down theinternalPLL. The SMI wouldoperateon thereferenceclock. InActivesleepmode, or Energy-Detectmode, every1.4seconds a Normal LinkPulse(NLP) issentto wake up thelink-partner.To enterintotheactivesleepmode, bits9 and 8 ofregisterPHYCR (0x10h)is setto"10".Automaticpowerup isdone when thelinkpartnerisdetected. In passivesleepmode, allcore blocksare powered down. Automaticpower-up isdone when the link partnerisdetected.To enterintothepassivesleepmode, bits9 and 8 ofregisterPHYCR (0x10h)issetto "11". Copyright© 2009,Texas InstrumentsIncorporated Resetand Power Down Operation 35 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

RD– RD– RD+ RD+ 49.9 /c87 49.9 /c87 Vdd Vdd TD– TD– TD+ TD+49.9 /c87 49.9 /c87 Vdd 1:1 1:1 T1 RJ45 Place□resistors□and□capacitors□close□to□the□device. Common-mode□chokes may□be□required. Note:□□Center□tap□is□connected□to□Vdd *□Place□capacitors□close□to□the transformer□center□taps All□values□are□typical□and□are 1%/c177 S0339-01 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

7 Design Guidelines

7.1 TPI Network Circuit

Figure7-1shows therecommended circuitfora 10/100Mb/s twistedpairinterface.Below isa partiallist of recommended transformers.Itis importantthatthe user realizethatvariationswith PCB and component characteristicsrequirethatthe applicationbe testedto verifythatthe circuitmeets the requirementsoftheintendedapplication.

• PulseH1102
• PulseHX1188 Figure7-1.10/100Mb/s TwistedPairInterface

7.2 Clock In(XI)Requirements

The TLK100 supportsan externalCMOS-level oscillatorsourceor an internaloscillatorwithan external crystal.

7.2.1 Oscillator

Ifan externalclocksourceisused,XI shouldbe tiedtotheclocksourceand XO shouldbe leftfloating. The amplitudeoftheoscillatorshouldbe a nominalvoltageof1.8V.

36 DesignGuidelines Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

7.2.2 Crystal

The use ofa 25MHz, parallel,20pF-loadcrystalresonatorisrecommended ifa crystalsourceisdesired. Figure7-2 shows a typicalconnectionfora crystalresonatorcircuit.The loadcapacitorvalueswillvary withthecrystalvendors;checkwiththevendorfortherecommended loads. The oscillatorcircuitisdesignedtodrivea parallelresonanceAT-cutcrystalwitha minimum drivelevelof 100μW and a maximum of500μW. Ifa crystalisspecifiedfora lowerdrivelevel,a currentlimitingresistor shouldbe placedinseriesbetween XO and thecrystal. As a startingpointforevaluatingan oscillatorcircuit,iftherequirementsforthecrystalarenotknown, set thevaluesforC L1 and C L2 at33pF,and R 1 shouldbe setat0Ω. Specificationfor25MHz crystalarelistedinTable7-2. Figure7-2.CrystalOscillatorCircuit Table7-1.25 MHz OscillatorSpecification PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency 25 MHz FrequencyTolerance OperationalTemperature ±50 ppm FrequencyStability 1 yearaging ±50 ppm Rise/FallTime 10% –90% 8 nsec Jitter(Shortterm) Cycle-to-cycle 50 psec Jitter(Longterm) Accumulativeover10 ms 1 nsec Symmetry DutyCycle 40% 60% Load Capacitance 15 30 pF Table7-2.25 MHz CrystalSpecification PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency 25 MHz FrequencyTolerance OperationalTemperature ±50 ppm At25°C ±50 ppm FrequencyStability 1 yearaging ±5 ppm Load Capacitance 10 40 pF Copyright© 2009,Texas InstrumentsIncorporated DesignGuidelines 37 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

7.3 Thermal ViasRecommendation

The followingthermalviaguidelinesapplytoGNDPAD, pin49: 1. Thermalviasize= 0.2mm 2. Recommend 4 vias 3. Viashave a centertocenterseparationof2 mm. Adherence tothisguidelineisrequiredtoachievetheintendedoperatingtemperaturerangeofthedevice. Figure7-3illustratesan example layout. Figure7-3.Example Layout

38 DesignGuidelines Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8 RegisterBlock

Table8-1.RegisterMap OFFSET HEX ACCESS TAG DESCRIPTION 00h RW BMCR BasicMode ControlRegister 01h RO BMSR BasicMode StatusRegister 02h RO PHYIDR1 PHY IdentifierRegister#1 03h RO PHYIDR2 PHY IdentifierRegister#2 04h RW ANAR Auto-NegotiationAdvertisementRegister 05h RO ANLPAR Auto-NegotiationLinkPartnerAbilityRegister 06h RO ANER Auto-NegotiationExpansionRegister 07h RW ANNPTR Auto-NegotiationNextPage TX 08h RO ANLNPTR Auto-NegotiationLinkPartnerAbilityNextPage Register 09h–0Ch RW RESERVED RESERVED 0Dh RW REGCR Registercontrolregister 0Eh RW ADDAR AddressorData register 0Fh RW RESERVED RESERVED EXTENDED REGISTERS 10h RW PHYCR PHY ControlRegister 11h RO PHYSR PHY StatusRegister 12h RW MINTMR MIIInterruptMask Register 13h RO MINTSR MIIInterruptStatusRegister 14h RW MINTCR MIIInterruptControlRegister 15h RO RECR ReceiveErrorCounterRegister 16h RW BISCR BIST ControlRegister 17h RO BISSR BIST StatusRegister 18h RW LEDCR LED DirectControlRegister 19h RW RESERVED RESERVED 1Ah RW CDCR CableDiagnosticControlRegister 1Bh RW CDSR CableDiagnosticStatusRegister 1Ch RO CDRR CableDiagnosticResultsRegister 1Dh-1Eh RW RESERVED RESERVED 1Fh RW PDR Power Down Register 42h RO FCSCR FalseCarrierSense CounterRegister 70h RW RXCCR RX ChannelControlRegister 71h RO BISBCR BIST ByteCount Register 72h RO BISECR BIST ErrorCount Register 7Bh RW BISPLR BIST PacketLengthRegister 7Ch RW BISIPGR BIST InterPacketGap Register 80h RW TDRSMR TDR StateMachine EnableRegister 90h RW TDRPAR TDR PatternAmplitudeRegister 94h RW TDRMPR TDR Manual PulseRegister 0C00h –0C0Ch RW TDR AlgorithmRegisters 0C26h –0C2Ah RW ALCD/DSA Registers 0D00h, 0D01h, RAM registersRW0D04h 0107h RW CD Pre TestConfiguration1 Register 010Fh RW CD Pre TestConfiguration2 Register 00AC RW LPF Bypass Register Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 39 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

40 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table8-2.RegisterTable RegisterName Addr Tag Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BasicMode Control 00h BMCR Reset Loopback Speed Auto-Neg Power Isolate Restart Duplex Collision Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register Selection Enable Down Auto-Neg Mode Test BasicMode Status 01h BMSR 100Base 100Base 100Base 10Base-T 10Base-T Reserved Reserved Reserved Reserved MF Auto-Neg Remote Auto-Neg LinkStatus Jabber Extended Register -T4 -TX FDX -TX HDX FDX HDX Preamble Complete Fault Ability Detect Capability Suppress PHY Identifier 02h PHYIDR 1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB Register1 PHY Identifier 03h PHYIDR 2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ MDL_ REV MDL_ REV MDL_ REV MDL_ REV Register2 MDL MDL MDL MDL MDL MDL Auto-Negotiation 04h ANAR NextPage Reserved Remote Reserved ASM_DI R PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol Advertisement Ind Fault Selection Selection Selection Selection Selection Register Auto-NegotiationLink 05h ANLPAR NextPage ACK Remote Reserved ASM_DI R PAUSE T4 TX_FD TX 10_FD 10 Protocol Protocol Protocol Protocol Protocol PartnerAbility Ind Fault Selection Selection Selection Selection Selection Register(BasePage) Auto-Negotiation 06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_ NP_ ABLE PAGE_ RX LP_AN_AB ExpansionRegister ABLE LE Auto-NegotiationNext 07h ANNPTR NextPage Reserved Message ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE Page TX Register Ind Page Auto-NegotiateLink 08h ANLNPTR NextPage Reserved Message ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE PartnerAbilityPage Ind Page Register RESERVED 09-0Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RegisterControl 0Dh REGCR Function Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DEVICE DEVICE DEVICE DEVICE DEVICE Register ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS AddressorData 0Eh ADDAR Addr/Data Addr/Data Addr /Data Addr /Data Addr/Data Addr/Data Addr /Data Addr /Data Addr/Data Addr/Data Addr /Data Addr /Data Addr/Data Addr/Data Addr /Data Addr /Data Register RESERVED 0Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EXTENDED REGISTERS PHY ControlRegister 10h PHYCR TX FIFO TX FIFO Reserved Reserved Reserved ForceLink Power Power Reserved AutoMDI-X Manual Disable Reserved Reserved Reserved Disable Depth Depth Good Down Mode Down Mode Enable MDI-X PLL Jabber Enable PHY StatusRegister 11h PHYSR Reserved Speed Duplex Page AutoNego LinkStatus Reserved MDI Cross Reserved Sleep Reserved Reserved Reserved Reserved Polarity Jabber Received Complete over Mode MIIInterruptMask 12h MINTMR AutoNego Speed Duplex Page AutoNego LinkStatus Reserved Reserved FIFO Over MDI cross Reserved Sleep Reserved Reserved Polarity Jabber Register error Change Mode Received Complete Change Under flow over Mode Change Interrupt Enable Enable Change Enable Enable Enable Enable change Change Enable Enable Enable Enable Enable MIIInterruptStatus 13h MINTSR AutoNego Speed Duplex Page AutoNego LinkStatus Reserved Reserved FIFO Over MDI Reserved Sleep Reserved Reserved Polarity Jabber Register Error Changed Mode Received Complete Changed Underflow Crossover Mode Changed Changed Changed Changed MIIInterruptControl 14h MINTCR Interrupt Reserved Interrupt Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Register PinEnable Polarity PinEnable ReceiveError 15h RECR RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXCERNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT RXERCNT CounterRegister BIST ControlRegister 16h BISCR PRBS Generate 64 bitmode Packet Reserved Reserved Reserved Reserved Reserved Reserved Reserved Loopback Loop back Loop back Loop back Loop back Count PRBS Generation Mode Mode Mode Mode Mode Mode Packets Enable Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 41 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table8-2.RegisterTable (continued) RegisterName Addr Tag Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BIST StatusRegister 17h BISSR Reserved Reserved Reserved Reserved PRBS PRBS Sync PRBS Core Power Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Locked Loss Generator Mode busy Status BIST ByteCount 71h BISBCR PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS Register Count Count Count Count Count Count Count Count Count Count Count Count Count Count Count Count BIST ErrorCount 72h BISECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PRBS ErrorPRBS ErrorPRBS ErrorPRBS ErrorPRBS ErrorPRBS ErrorPRBS ErrorPRBS Error Register Count Count Count Count Count Count Count Count BIST PacketLength 7Bh BISPLR PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS register Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Packet Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length BIST InterPacket 7Ch BISIPGR PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG PRBS IPG Gap Register Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length Length LED ControlRegister 18h LEDCR LED PulseWidth PulseWidth Force Reserved Reserved BlinkRate BlinkRate Reserved LED Mode LED Mode Reserved Reserved LED ACT LED LED LINK Enable Interrupt Polarity SPEED Polarity Polarity Power Down Register 1Fh PDR Software Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Global Reset FalseCarrierSense 42h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Idle_error_cIdle_error_cIdle_error_cIdle_error_cIdle_error_cIdle_error_cIdle_error_cIdle_error_c CounterRegister ount ount ount ount ount ount ount ount RX ChannelControl 70h RXCCR Rese-rved Rese-rved Rese-rved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Polarity Mdix Reserved Reserved Register Inversion CableDiagnostic 1Ah CDCR Reserved Reserved ALCD/ DSA TDR test Reserved CableDiag CableDiag CableDiag Reserved Reserved Reserved Reserved Reserved Reserved Reserved Channel Register teststart Start result result result Select Select Select Select CableDiagnostic 1Bh CDSR ALCD/ DSA TDR Fail TDR Done Reserved Reserved Reserved DSA Input DSA Input DSA Input DSA Input DSA ALCD/ DSA Reserved Reserved Reserved Reserved StatusRegister Done Signal Signal Signal Signal Enalbe mode CableDiagnostic 1Ch CDRR CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag CableDiag ResultsRegister Results Results Results Results Results Results Results Results Results Results Results Results Results Results Results Results TDR StateMachine 80h TDRSMR Cmn_tdr_ Cmn_tdr Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Enable sm_mode _tx_sm_ mode TDR Pattern 90h TDRPAR Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved Rese- rved TDR TDR TDR TDR TDR AmplitudeRegister pattern pattern pattern pattern pattern TDR Manual Pulse 94h TDRMPR Rese-rved Rese-rved Rese-rved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TDR_TX Reserved Register _START TDR Algorithm 0C00h – 0C0ChRegisters ALCD/DSA Registers 0C26h – 0C2Ah CableDiagnosticalgorithmrelatedregisters CD Pre test 0107h,010Fh Configuration LPF Bypass Register 00ACh

42 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.1 RegisterDefinition

Intheregisterdefinitionsunderthe‘Default’heading,thefollowingdefinitionsholdtrue:

• RW = Read Writeaccess
• SC = Registersetson eventoccurrenceand Self-Clearswhen eventends
• RW/SC = Read WriteAccess/SelfClearingbit
• RO = Read Onlyaccess
• COR = Clearon Read
• RO/COR = Read Only,Clearon Read
• RO/P = Read Only,Permanentlysettoa defaultvalue
• LL = LatchedLow and helduntilread,based upon theoccurrenceofthecorrespondingevent
• LH = LatchedHighand helduntilread,based upon theoccurrenceofthecorrespondingevent Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 43 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.1.1 Basic Mode ControlRegister(BMCR)

Table8-3.Basic Mode ControlRegister(BMCR), address 0x0000 BIT BIT NAME DEFAULT DESCRIPTION

15 Reset 0,RW/SC PHY SoftwareReset:

1 = InitiatesoftwareReset/ResetinProcess. 0 = Normal operation. Writinga 1 tothisbitcauses thePHY tobe reset.When theresetoperationisdone,thisbit isclearedto0 automatically.The configurationisrelatched.

14 Loopback 0,RW Loopback:

1 = Loopback enabled. 0 = Normal operation. When loopbackmode isactivated,thetransmitterdatapresentedon TXD isloopedback to RXD internally

13 Speed Selection Jumper,RW Speed Select:

When auto-negotiationisdisabledwritingtothisbitallowstheportspeed tobe selected. 1 = 100 Mb/s 0 = 10 Mb/s

12 Auto-Negotiation Jumper,RW Auto-NegotiationEnable:

Enable Configurationpin(jumper)controlsinitialvalueatreset. 1 = Auto-NegotiationEnabled– bits8 and 13 ofthisregisterareignoredwhen thisbitis set. 0 = Auto-NegotiationDisabled– bits8 and 13 determinetheportspeed and duplex mode.

11 Power Down 0,RW Power Down:

1 = EnablesPower Down Modes -GeneralPower Down Mode, ActiveSleepMode and PassiveSleepMode (seeregister0x10) 0 = Normal operation.

10 Isolate 0,RW Isolate:

1 = IsolatesthePortfromtheMIIwiththeexceptionoftheserialmanagement. 0 = Normal operation.

9 RestartAuto- 0,RW/SC RestartAuto-Negotiation:

Negotiation 1 = RestartAuto-Negotiation.Re-initiatestheAuto-Negotiationprocess.If Auto-Negotiationisdisabled(bit12 = 0),thisbitisignored.Thisbitisself-clearing and willreturna valueof1 untilAuto-Negotiationisinitiated,whereupon itwill self-clear.OperationoftheAuto-Negotiationprocessisnotaffectedby the management entityclearingthisbit. 0 = Normal operation. Re-initiatestheAuto-Negotiationprocess.IfAuto-Negotiationisdisabled(bit12 = 0),thisbit isignored.Thisbitisself-clearingand willreturna valueof1 untilAuto-Negotiationis initiated,whereupon itself-clears.OperationoftheAuto-Negotiationprocessisnotaffected by themanagement entityclearingthisbit.

8 DuplexMode Jumper,RW Duplex Mode:

When auto-negotiationisdisabledwritingtothisbitallowstheportDuplexcapabilitytobe selected. 1 = FullDuplexoperation. 0 = HalfDuplexoperation.

7 CollisionTest 0,RW CollisionTest:

1 = Collisiontestenabled. 0 = Normal operation 6:0 RESERVED 0,RO RESERVED: Writeignored,readas 0.

44 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.1.2 Basic Mode StatusRegister(BMSR)

Table8-4.Basic Mode StatusRegister(BMSR), address 0x0001 BIT BIT NAME DEFAULT DESCRIPTION 15 100BASE-T4 0,RO/P 100BASE-T4 Capable: Thisprotocolisnotavailable.Always0 = Devicedoes notperform100BASE-T4 mode. 14 100BASE-TX 1,RO/P 100BASE-TX FullDuplex Capable: FullDuplex 1 = Deviceabletoperform100BASE-TX infullduplexmode. 0 = Devicenotabletoperform100BASE-TX infullduplexmode. 13 100BASE-TX 1,RO/P 100BASE-TX HalfDuplex Capable: HalfDuplex 1 = Deviceabletoperform100BASE-TX inhalfduplexmode. 0 = Devicenotabletoperform100BASE-TX inhalfduplexmode. 12 10BASE-T 1,RO/P 10BASE-T FullDuplex Capable: FullDuplex 1 = Deviceabletoperform10BASE-T infullduplexmode. 0 = Devicenotabletoperform10BASE-T infullduplexmode. 11 10BASE-T 1,RO/P 10BASE-T HalfDuplex Capable: HalfDuplex 1 = Deviceabletoperform10BASE-T inhalfduplexmode. 0 = Devicenotabletoperform10BASE-T inhalfduplexmode. 10: RESERVED 0,RO RESERVED: Writeas 0,readas 0.

6 MF Preamble 1,RO/P Preamble suppressionCapable:

Suppression 1 = Deviceabletoperformmanagement transactionwithpreamblesuppressed,32-bitsofpreamble needed onlyonce afterreset,invalidopcode orinvalidturnaround. 0 = Devicewillnotperformmanagement transactionwithpreamblessuppressed.

5 Auto- 0,RO Auto-NegotiationComplete:

Negotiation 1 = Auto-Negotiationprocesscomplete.Complete 0 = Auto-Negotiationprocessnotcomplete(eitherstillinprocess,disabled,orreset)

4 Remote Fault 0,RO/LH Remote Fault:

1 = Remote Faultconditiondetected(clearedon readorby reset).Faultcriteria:FarEnd Fault IndicationornotificationfromLinkPartnerofRemote Fault. 0 = No remotefaultconditiondetected.

3 Auto- 1,RO/P Auto NegotiationAbility:

Negotiation 1 = DeviceisabletoperformAuto-Negotiation.Ability 0 = DeviceisnotabletoperformAuto-Negotiation.

2 LinkStatus 0,RO/LL LinkStatus:

1 = Validlinkestablished(foreither10 or100 Mb/s operation). 0 = Linknotestablished. 1 JabberDetect 0,RO/LH Jabber Detect:Thisbitonlyhas meaning in10 Mb/s mode. 1 = Jabberconditiondetected. 0 = No Jabber.conditiondetected.

0 Extended 1,RO/P Extended Capability:

Capability 1 = Extendedregistercapabilities. 0 = Basicregistersetcapabilitiesonly. The PHY IdentifierRegisters#1 and #2 togetherform a uniqueidentifierforthe TLK100. The Identifier consistsof a concatenationof the OrganizationallyUnique Identifier(OUI),the vendor'smodel number and the model revisionnumber. A PHY may returna valueof zero ineach of the 32 bitsof the PHY Identifierifdesired.The PHY Identifierisintendedtosupportnetworkmanagement. The IEEE-assigned OUI forTexas Instrumentsis080028h. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 45 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.1.3 PHY IdentifierRegister#1 (PHYIDR1)

Table8-5.PHY IdentifierRegister#1 (PHYIDR1),address 0x0002 BIT BIT NAME DEFAULT DESCRIPTION 15 OUI_MSB <0010 0000 0000 OUI Most SignificantBits:Bits3 to18 oftheOUI (080028h)arestoredinbits15 to0 of 0000>, thisregister.The most significanttwo bitsoftheOUI areignored(theIEEE standardrefers RO/P totheseas bits1 and 2).

8.1.4 PHY IdentifierRegister#2 (PHYIDR2)

Table8-6.PHY IdentifierRegister#2 (PHYIDR2),address 0x0003 BIT BIT NAME DEFAULT DESCRIPTION 15:10 OUI_LSB <101000>, OUI LeastSignificantBits: RO/P Bits19 to24 oftheOUI (080028h)aremapped frombits15 to10 ofthisregisterrespectively. 9:4 VNDR_MDL <100000>, Vendor Model Number: RO/P The sixbitsofvendormodel number aremapped frombits9 to4 (mostsignificantbittobit9). 3:0 MDL_REV <0001>,RO/P Model RevisionNumber: Four bitsofthevendormodel revisionnumber aremapped frombits3 to0 (mostsignificantbitto bit3).Thisfieldisincrementedforallmajordevicechanges.

46 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.1.5 Auto-NegotiationAdvertisementRegister(ANAR)

Thisregistercontainstheadvertisedabilitiesofthisdeviceas theyaretransmittedtoitslinkpartnerduring Auto-Negotiation. Table8-7.Auto NegotiationAdvertisementRegister(ANAR), address 0x0004 BIT BIT NAME DEFAULT DESCRIPTION

15 NP 0,RW Next Page Indication:

0 = NextPage Transfernotdesired. 1 = NextPage Transferdesired. 14 RESERVED 0,RO/P RESERVED by IEEE:Writesignored,Read as 0.

13 RF 0,RW Remote Fault:

1 = Advertisesthatthisdevicehas detecteda Remote Fault. 0 = No Remote Faultdetected.

12 RESERVED 0,RW RESERVED forFutureIEEE use:Writeas 0,Read as 0

11 ASM_DIR 0,RW Asymmetric PAUSE Support forFullDuplex Links:

1 = AsymmetricPAUSE implemented. 0 = AsymmetricPAUSE notimplemented.

10 PAUSE 0,RW PAUSE Support forFullDuplex Links:

1 = MAC PAUSE implemented 0 = MAC PAUSE notimplemented

9 T4 0,RO/P 100BASE-T4 Support:

1 = 100BASE-T4 issupportedby thelocaldevice. 0 = 100BASE-T4 notsupported.

8 TX_FD Jumper,RW 100BASE-TX FullDuplex Support:

1 = 100BASE-TX FullDuplexissupportedby thelocaldevice. 0 = 100BASE-TX FullDuplexnotsupported.

7 TX Jumper,RW 100BASE-TX Support:

1 = 100BASE-TX issupportedby thelocaldevice. 0 = 100BASE-TX notsupported. 6 10_FD Jumper,RW 10BASE-T FullDuplex Support: 1 = 10BASE-T FullDuplexissupportedby thelocaldevice. 0 = 10BASE-T FullDuplexnotsupported. 5 10 Jumper,RW 10BASE-T Support: 1 = 10BASE-T issupportedby thelocaldevice. 0 = 10BASE-T notsupported. 4:0 Selector <00001>,RW ProtocolSelectionBits: These bitscontainthebinaryencoded protocolselectorsupportedby thisport.<00001> indicatesthat thisdevicesupportsIEEE 802.3u. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 47 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.1.6 Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (BASE Page)

ThisregistercontainstheadvertisedabilitiesoftheLinkPartneras receivedduringAuto-Negotiation.The contentchanges afterthesuccessfulauto-negotiationifNext-pagesaresupported. Table8-8.Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (BASE Page),address 0x0005 BIT BIT NAME DEFAULT DESCRIPTION

15 NP 0,RO Next Page Indication:

0 = LinkPartnerdoes notdesireNextPage Transfer. 1 = LinkPartnerdesiresNextPage Transfer.

14 ACK 0,RO Acknowledge:

1 = LinkPartneracknowledgesreceptionoftheabilitydataword. 0 = Not acknowledged.The Auto-Negotiationstatemachine willautomaticallycontrolthethisbit based on theincomingFLP bursts.

13 RF 0,RO Remote Fault:

1 = Remote Faultindicatedby LinkPartner. 0 = No Remote Faultindicatedby LinkPartner. 12 RESERVED 0,RO RESERVED forFutureIEEE use:Writeas 0,readas 0.

11 ASM_DIR 0,RO ASYMMETRIC PAUSE:

1 = Asymmetricpause issupportedby theLinkPartner. 0 = Asymmetricpause isnotsupportedby theLinkPartner.

10 PAUSE 0,RO PAUSE:

1 = Pause functionissupportedby theLinkPartner. 0 = Pause functionisnotsupportedby theLinkPartner.

9 T4 0,RO 100BASE-T4 Support:

1 = 100BASE-T4 issupportedby theLinkPartner. 0 = 100BASE-T4 isnotsupportedby theLinkPartner.

8 TX_FD 0,RO 100BASE-TX FullDuplex Support:

1 = 100BASE-TX FullDuplexissupportedby theLinkPartner. 0 = 100BASE-TX FullDuplexisnotsupportedby theLinkPartner.

7 TX 0,RO 100BASE-TX Support:

1 = 100BASE-TX issupportedby theLinkPartner. 0 = 100BASE-TX isnotsupportedby theLinkPartner. 6 10_FD 0,RO 10BASE-T FullDuplex Support: 1 = 10BASE-T FullDuplexissupportedby theLinkPartner. 0 = 10BASE-T FullDuplexisnotsupportedby theLinkPartner. 5 10 0,RO 10BASE-T Support: 1 = 10BASE-T issupportedby theLinkPartner 0 = 10BASE-T isnotsupportedby theLinkPartner. 4:0 Selector <0 0000>,RO ProtocolSelectionBits: LinkPartner’s binaryencoded protocolselector.

48 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.1.7 Auto-NegotiateExpansion Register(ANER)

ThisregistercontainsadditionalLocalDeviceand LinkPartnerstatusinformation. Table8-9.Auto-NegotiateExpansion Register(ANER), address 0x0006 BIT BIT NAME DEFAULT DESCRIPTION 15:5 RESERVED 0,RO RESERVED: Writesignored,Read as 0.

4 PDF 0,RO ParallelDetectionFault:

1 = A faulthas been detectedviatheParallelDetectionfunction. 0 = A faulthas notbeen detected.

3 LP_NP_ABLE 0,RO LinkPartnerNext Page Able:

1 = LinkPartnerdoes supportNextPage. 0 = LinkPartnerdoes notsupportNextPage.

2 NP_ABLE 1,RO/P Next Page Able:

1 = Indicateslocaldeviceisabletosend additionalNextPages. 0 = Indicateslocaldeviceisnotabletosend additionalNextPages.

1 PAGE_RX 0,RO/COR LinkCode Word Page Received:

1 = LinkCode Word has been received,clearedon a read. 0 = LinkCode Word has notbeen received.

0 LP_AN_ABLE 0,RO LinkPartnerAuto-NegotiationAble:

1 = indicatesthattheLinkPartnersupportsAuto-Negotiation. 0 = indicatesthattheLinkPartnerdoes notsupportAuto-Negotiation. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 49 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.1.8 Auto-NegotiateNext Page TransmitRegister(ANNPTR)

This registercontainsthe next page informationsent by thisdevice to itsLink Partnerduring Auto-Negotiation. Table8-10.Auto-NegotiationNext Page TransmitRegister(ANNPTR), address 0x0007 BIT BIT NAME DEFAULT DESCRIPTION 0 = No otherNextPage Transferdesired. 1 = AnotherNextPage desired. 14 RESERVE 0,RO RESERVED: Writesignored,readas 0. D

13 MP 1,RW Message Page:

1 = Message Page. 0 = UnformattedPage.

12 ACK2 0,RW Acknowledge2:

1 = Willcomplywithmessage. 0 = Cannot complywithmessage. Acknowledge2isused by thenextpage functiontoindicatethatLocalDevicehas theabilityto complywiththemessage received.

11 TOG_TX 0,RO Toggle:

1 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 0. 0 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 1. Toggleisused by theArbitrationfunctionwithinAuto-NegotiationtosynchronizewiththeLink PartnerduringNextPage exchange.ThisbitalwaystakestheoppositevalueoftheTogglebitin thepreviouslyexchanged LinkCode Word. 10:0 CODE <000 0000 0001>, Thisfieldrepresentsthecode fieldofthenextpage transmission.IftheMP bitisset(bit13 ofthis RW register),thenthecode isinterpretedas a Message Page,as definedinannex 28C ofIEEE 802.3u.Otherwise,thecode isinterpretedas an UnformattedPage,and theinterpretationis applicationspecific. The defaultvalueoftheCODE representsa NullPage as definedinAnnex 28C ofIEEE 802.3u.

50 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.1.9 Auto-NegotiationLinkPartnerAbilityNext Page Register(ANLNPTR)

This registercontainsthe next page informationsent by thisdevice to itsLink Partnerduring Auto-Negotiation. Table8-11.Auto-NegotiationLinkPartnerAbilityRegisterNext Page (ANLNPTR), address 0x0008 BIT BIT NAME DEFAULT DESCRIPTION 1 = No otherNextPage Transferdesired. 0 = AnotherNextPage desired 1 = LinkPartneracknowledgesreceptionoftheabilitydataword. 0 = Not acknowledged. The Auto-Negotiationstatemachine willautomaticallycontrolthisbitbased on theincomingFLP bursts.Softwareshouldnotattempttowritetothisbit.

13 MP 1,RO Message Page:

1 = Message Page. 0 = UnformattedPage.

12 ACK2 0,RO Acknowledge2:

1 = Willcomplywithmessage. 0 = Cannot complywithmessage Acknowledge2isused by thenextpage functiontoindicatethatLocalDevicehas theabilityto complywiththemessage received.

11 Toggle 0,RO Toggle:

1 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 0. 0 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 1. Toggleisused by theArbitrationfunctionwithinAuto-NegotiationtosynchronizewiththeLink PartnerduringNextPage exchange.ThisbitalwaystakestheoppositevalueoftheTogglebitin thepreviouslyexchanged LinkCode Word. 10:0 CODE <000 0000 0001>, Code: RO Thisfieldrepresentsthecode fieldofthenextpage transmission.IftheMP bitisset(bit13 of thisregister),thenthecode isinterpretedas a Message Page, as definedinannex 28C ofIEEE 802.3u.Otherwise,the code isinterpretedas an UnformattedPage, and the interpretationis applicationspecific. The defaultvalueoftheCODE representsa NullPage as definedinAnnex 28C ofIEEE 802.3u. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 51 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.2 RegisterControlRegister(REGCR)

Thisregistercontainsthedeviceaddresstobe writtentoaccess theextendedregisters.Write0x1F into bits4:0ofthisregister.Italsocontainsselectionbitsforautoincrementofthedataregister. Table8-12.RegisterControlRegister(REGCR), address 0x000D BIT BIT NAME DEFAULT DESCRIPTION 15:1 Function 0,RW 00 = Address 4 01 = Data,no postincrement 10 = Data,postincrementon readand write 11 = Data,postincrementon writeonly 13:5 RESERVED 0,RO RESERVED: Writesignored,read as 0. 4:0 DEVAD 0,RW DeviceAddress

8.3 Address or Data Register(ADDAR)

Thisistheaddress/dataregister. Table8-13.Data Register(ADDAR), address 0x000E BIT BIT NAME DEFAULT DESCRIPTION 15:0 Addr/data 0,RW IfREGCR register15:14= 00,holdstheMMD DEVAD's addressregister,otherwiseholdsthe MMD DEVAD's dataregister

52 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.4 Extended Registers

8.4.1 PHY ControlRegister(PHYCR)

Thisregisterprovidesquickaccesstocommonly accessedPHY controlinformation. Table8-14.PHY ControlRegister(PHYCR), address 0x0010 BIT BIT NAME DEFAULT DESCRIPTION 15:14 TX FIFO Depth 0x1,RW 00 = 4 nibbles 01 = 5 nibbles 10 = 6 nibbles 11 = 8 nibbles 13:12 Reserved 0,RO Ignoreon read

11 Reserved 0,RO Ignoreon read

10 ForceLinkGood 0,RW 1 = Forcelink_ctrl_en10/100accordingtoselectedspeed inregister0x0

0 = Do Normal operation 9:8 Power Down 00,RW 00 = Normal mode Mode 01 = GeneralPower Down mode: BesidesSMI module everythingispowered down, ifbit[4] setto’1’,PLL isalsopowered down. When PLL ispowered down, Referenceclockis used. 10 = ActiveSleepmode – same as passivesleep,butalsosend NLP every~1.4Sec towake up link-partner.Automaticpower-upisdone when linkpartnerisdetected. 11 = PassiveSleepMode -BesidesSMI and energydetectmodules,everythingispowered down. Automaticpower-upisdone when linkpartnerisdetected. Bit11 oftheBMCR register(0x00)to'1'forallofthesepower down modes.

7 Reserved 0,RW Reserved

6 AutoMDI-X SOR,RW 1 = Enableautomaticcrossover

Enable 0 = Disableautomaticcrossover

5 Manual MDI-X 0,RW 0 = Manual MDI configuration

Mode 1 = Manual MDI-X configuration

4 DisablePLL 0,RW 1 = DisablePLL

0 = EnablePLL 3:1 Reserved 0,RO Ignoreon read

0 DisableJabber 0,RW 1 = DisableJabberfunction

0 = EnableJabberfunction Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 53 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.4.2 PHY StatusRegister(PHYSR)

ThisregisterimplementsthePHY SpecificStatusregister. Table8-15.PHY StatusRegister(PHYSR), address 0x0011 BIT NAME DEFAULT DESCRIPTION

15 Reserved 0,RO Ignoreon read

14 Speed 0,RO 0 = 10Mbps

1 = 100Mbps

13 Duplex 0,RO 1 = Fullduplex

0 = Halfduplex

12 Page Received 0,RO,LH 1 = Page received

0 = Page notreceived

11 Auto-Negotiation 0,RO 1 = Auto-Negotiationcompletedordisabled

Complete 0 = Auto-Negotiationenabledand notcompleted

10 LinkStatus 0,RO 1 = Linkisup

0 = Linkisdown

9 Reserved 0,RO Ignoreon read

8 MDI CrossoverStatus 0,RO 1 = MDI-X

0 = MDI

7 Reserved 0,RO Ignoreon read

6 SleepMode Status 0,RO 1 = Sleep

0 = Active 5:2 Reserved 0,RO Ignoreon read 1 Polarity 0,RO 10BT data/nlppolarity. "1"-positivepolarity. "0"-negativepolarity.

0 Jabber 0,RO 1 = Jabber

0 = No Jabber

54 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.4.3 MIIInterruptMask Register(MINTMR)

Thisregistercontainsenablesforvariousinterruptfunctionssupportedby TLK100. Table8-16.MIIInterruptMask Register(MINTMR), address 0x0012 BIT NAME DEFAULT DESCRIPTION

15 Auto-NegotiationInterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt

14 Speed Changed InterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt

13 DuplexMode Changed Interrupt 0,RW 1 = Enableinterrupt

Enable 0 = Disableinterrupt

12 Page ReceivedInterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt

11 Auto-NegotiationCompletedInterrupt 0,RW 1 = Enableinterrupt

Enable 0 = Disableinterrupt

10 LinkStatusChanged InterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt 9:8 Reserved 0,RO Ignoreon read

7 FIFO Overflow/UnderflowInterrupt 0,RW 1 = Enableinterrupt

Enable 0 = Disableinterrupt

6 MDI CrossoverChanged Interrupt 0,RW 1 = Enableinterrupt

Enable 0 = Disableinterrupt

5 Reserved 0,RO Ignoreon read

4 SleepMode Changed Interrupt 0,RW 1 = Enableinterrupt

Enable 0 = Disableinterrupt 3:2 Reserved 0,RO Ignoreon read

1 PolarityChanged InterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt

0 JabberInterruptEnable 0,RW 1 = Enableinterrupt

0 = Disableinterrupt Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 55 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.4.4 MIIInterruptStatusRegister(MINTSR)

Thisregistergivesthestatusofthedifferentinterruptfunctionsupportedby TLK100. Table8-17.MIIInterruptStatusRegister(MINTSR),address 0x0013 BIT NAME DEFAULT DESCRIPTION

15 Auto-NegotiationError 0,RO, LH 1 = Auto-Negotiationerrorhas occurred

0 = Auto-Negotiationerrorhas notoccurred

14 Speed Changed 0,RO,LH 1 = Linkspeed has changed

0 = Linkspeed has notchanged

13 DuplexMode Changed 0,RO,LH 1 = Duplexmode has changed

0 = Duplexmode has notchanged

12 Page Received 0,RO,LH 1 = Page has been received

0 = Page has notbeen received

11 Auto-NegotiationCompleted 0,RO,LH 1 = Auto-Negotiationhas completed

0 = Auto-Negotiationhas notcompleted

10 LinkStatusChanged 0,RO,LH 1 = Linkstatushas changed

0 = Linkstatushas notchanged 9:8 Reserved 0,RO Ignoreon read

7 FIFO Overflow/Underflow 0,RO,LH 1 = FIFO Overflow/Underflowoccurred

0 = FIFO Overflow/Underflowdidnotoccur

6 MDI CrossoverChanged 0,RO,LH 1 = MDI crossoverhas changed

0 = MDI crossoverhas notchanged

4 SleepMode Changed 0,RO,LH 1 = Sleepmode has changed

0 = Sleepmode has notchanged 3:2 Reserved 0,RO Ignoreon read

1 PolarityChanged 0,RO,LH 1 = Data polarityhas changed

0 = Data polarityhas notchanged

0 Jabber 0,RO,LH 1 = Jabberdetected

0 = Jabbernotdetected

8.4.5 MIIInterruptControlRegister(MINTCR)

Thisregisterenablestocontrolthepolarityand enablingtheinterrupts. Table8-18.MIIInterruptControlRegister(MINTCR),address 0x0014 BIT NAME DEFAULT DESCRIPTION

15 INTN_OE 0,RW Bit15 Bit12 Pin42 Function

14 Reserved 0,RO Ignoreon read

13 InterruptPolarity 1,RW 1 = Interruptpinisactivelow

0 = Interruptpinisactivehigh 12 INTN_OEN 1,RW Refertothetablegiveninthebit15 description. 11:0 Reserved 0,RO Ignoreon read

56 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.4.6 ReceiverErrorCounter Register(RECR)

Thiscounterkeeps countofthenumber ofreceiveerrors. Table8-19.ReceiverErrorCounter Register(RECR), address 0x0015 BIT BIT NAME DEFAULT DESCRIPTION 15:0 RX ErrorCount 0,RO, SC Receiveerrorscounter(saturatesinmax value,clearson dummy write)

8.4.7 BIST ControlRegister(BISCR)

Thisregisterisused forconfiguringthePRBS BIST and toselecttheloopbackpointinthesignalchain. Table8-20.BIST ControlRegister(BISCR),address 0x0016 BIT NAME DEFAULT DESCRIPTION

15 PRBS Count Mode 0,RW 1 = Continuousmode, when on ofthePRBS countersreachesmax value,pulseis

generatedand counterstartscountingfromzeroagain 0 = Singlemode, When one ofthePRBS countersreachesit'smax value,PRBS checkerstopscounting. 14 GeneratePRBS Packets 0,RW 1 = When packetgeneratorisenabled,generatecontinuouspacketswithPRBS data. When packetgeneratorisdisabled,PRBS checkerisstillenabled. 0 = When packetgeneratorisenabled,generatesinglepacketwithconstantdata. PRBS gen/checkisdisabled.

13 PacketGeneration64 bit 0,RW 1 = Transmit64 bytepacketsinpacketgenerationmode

mode 0 = Transmit1518 bytepacketsinpacketgenerationmode

12 PacketGenerationEnable 0,RW 1 = Enablepacket/PRBSgenerator

0 = Disablepacket/PRBSgenerator 11:5 Reserved 0,RO Ignoreon read 4:0 Loopback Mode 0,RW Selectsloopback mode: Near-endLoopbacks [00001]– MIILoopback [00010]– PCS Loopback (In100BaseTX only) [00100]– DigitalLoopback [01000]– AnalogLoopback (requires100Ω termination) Far-endLoopback: [10000]– ReverseLoopback

8.4.8 BIST STATUS Register(BISSR)

ThisregistergivesthestatusofthePRBS testand thesleepmode ofthecore. Table8-21.BIST STATUS Register(BISSR),address 0x0017 BIT NAME DEFAULT DESCRIPTION 15:12 Reserved 0,RO Ignoreon read

11 PRBS Locked 0,RO 1 = PRBS checkerislockedon receivedbytestream

0 = PRBS checkerisnotlocked

10 PRBS Sync Loss 0,RO,LH 1 = PRBS checkerhas lostsync

0 = PRBS checkerhas notlostsync

9 PacketGeneratorBusy 0,RO 1 = Packetgeneratorisinprocess

0 = Packetgeneratorisnotinprocess

8 Core Power Mode 0,RO 1 = Core isinnormalpower mode

Status 0 = Core ispowered down orinsleepmode 7:0 Reserved 0,RO Ignoreon read Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 57 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.4.9 BIST Byte Count Register(BISBCR)

Thisregistergivesthetotalnumber ofbytesreceivedby thePRBS checker. Table8-22.BIST Count Register(BISBCR),address 0x0071 BIT BIT NAME DEFAULT DESCRIPTION 15:0 prbs_byte_cnt 0,RO Holdsnumber oftotalbytesthatreceivedby thePRBS checker.Valueinthisregisterislocked when writeisdone toregister0x0072 bit[0]orbit[1].When PRBS Count Mode settozero, countstopson 0xFFFF (seeregister0x0016)

8.4.10 BIST ErrorCount Register(BISECR)

Thisregistergivesthetotalnumber oferrorbytesthatwas receivedby thePRBS checker. Table8-23.BIST ErrorCount Register(BISECR),address 0x0072 BIT BIT NAME DEFAULT DESCRIPTION 15:8 Reserved 0,RO Ignoreon read 7:0 prbs_err_cnt 0,RO Holdsnumber oferroneousbytesreceivedby thePRBS checker.Valueinthisregisteris lockedwhen writeisdone tobit[0]orbit1. When PRBS Count Mode settozero,countstopson 0xFF (seeregister0x0016) Notes: Writingbit0 generatesa locksignalforthePRBS counters Writingbit1 generatesa lockand clearsignalforthePRBS counters

8.4.11 BIST Packet Length Register(BISPLR)

ThisregisterallowsprogrammingthelengthofthePRBS packetinbytes. Table8-24.BIST Packet Length Register(BISPLR),address 0x007B BIT BIT NAME DEFAULT DESCRIPTION 15:0 Cfg_pkt_len_prbs 0X5DC,RW LengthofPRBS packetsinbytes

8.4.12 BIST InterPacket Gap Register(BISIPGR)

Thisregisterallowsprogrammingtheinterpacketgap,inbytes,between thePRBS packets. Table8-25.BIST InterPacket Gap Register(BISIPGR),address 0x007C BIT BIT NAME DEFAULT DESCRIPTION 15:0 Cfg_ipg_len 0X7D,RW Inter-packetgap (inbytes)between PRBS packets

58 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.4.13 LED DirectControlRegister(LEDCR)

Thisregisterprovidestheabilitytodirectlycontrolany or allLED outputs.The polarity,pulsewidthand blinkratescan be programmed usingthisregister. Table8-26.LED DirectControlRegister(LEDCR), address 0x0018 BIT NAME DEFAULT DESCRIPTION

15 LEDs Enable 1,RW 1 = EnableLEDs

0 = DisableLEDs 14:13 PulseWidth 0x2,RW 00 = 50mSec 01 = 100mSec 10 = 200mSec 11 = 500mSec

12 ForceInterrupt 0,RW 1 = Assertinterruptpin

0 = Normal interruptmode 11:10 Reserved 0,RO Ignoreon read 9:8 BlinkRate 0x2,RW 00 = 20Hz (50mSec) 01 = 10Hz (100mSec) 10 = 5Hz (200mSec) 11 = 2Hz (500mSec) 6:5 LED Mode 0,SOR,RW 01 = Mode1 00 = Mode2 10 = Mode3 4:3 Reserved 0,RO Ignoreon read

2 LED ACT Polarity SOR,RW 0 = Activelow

1 = Activehigh

1 LED SPEED Polarity SOR,RW 0 = Activelow

1 = Activehigh

0 LED LINK Polarity SOR,RW 0 = Activelow

1 = Activehigh

8.4.14 Power Down Register(PDR)

Thisregisterprovidescontrolfordoinga softwareresetofthePHY. Table8-27.Power Down Register(PDR),address 0x001F BIT NAME DEFAULT DESCRIPTION

15 SoftwareGlobal 0,RW,SC 1 = ResetPHY (Same effectas inhardwarereset,includingregistersreset)

Reset 0 = Normal mode 14:0 Reserved 0,RO Alwayswritezero Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 59 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.4.15 FalseCarrierSense Counter Register(FCSCR)

Thisregistercountsthe errornibblesbetween the IDLE nibbles(BAD_SSD), innibbletime.Thiscount registerisresetwhen thisregisterisread. Table8-28.FalseCarrierSense Counter Register(FCSCR), address 0x0042 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0,RO Ignoreon read 7:0 idle_err_count_100 0,RO IDLE errorcountervalue.Countsreceivederrornibblesbetween IDLE nibbles(BAD_SSD), in nibbletime. Note:Readingthisregisterclearstheidle_err_count_100counter

8.4.16 RX Channel ControlRegister(RXCCR)

This registerallowsconfigurationof RX channel.By programming bits3,2 of thisregisterto ‘1’ the channelscan be mirrored. Table8-29.RX Channel ControlRegister(RXCCR), address 0x0070 BIT NAME DEFAULT FUNCTION 15:4 Reserved 0,RO Ignoreon read

3 Polarity_inv 0,RW When 1 Change thepolarityof:

1 = PolarityofRD and TD isinverted 0 = PolarityofRD and TD isnotinverted

2 Mdix 0,RW 1 = MDIX

0 = MDI 1:0 Reserved 0,RW Alwayswrite0

8.5 Cable DiagnosticRegisters

8.5.1 Cable DiagnosticRegisters(CDCR)

Thisregisterisused toselectthechannelforwhich cablediagnosticstestneeds tobe done.Ithas the enablebitsforthediagnostictestsand alsoallowsone tochoose which TDR peak and locationwillbe writtentotheCDRR register(0x001C). Table8-30.Cable DiagnosticRegisters(CDCR), address 0x001A BIT NAME DEFAULT DESCRIPTION 15:14 Reserved 0,RW, SC Always0 13 ALCD/DSA Test 0,RW, SC 1 = StartALCD/DSA test. Start 0 = Do notstartALCD/DSA test

12 TDR TestStart 0,RW, SC 1 = StartTDR test

0 = Do notstartTDR test

11 Reserved 0,RO Reserved

10:8 CableDiagnostics 0,RW Selectstheoutputofregister0x1C as follows: ResultSelect 0:{TDR peak 0 amplitude,TDR peak 0 location} 1:{TDR peak 1 amplitude,TDR peak 1 location} 2:{TDR peak 2 amplitude,TDR peak 2 location} 3:{TDR peak 3 amplitude,TDR peak 3 location} 4:{TDR peak 4 amplitude,TDR peak 4 location} 6:ALCD Length 8:1 Reserved 0,RO Ignoreon read

0 ChannelSelect 0,RW SelectschannelforCableDiagnosticsTest

0 = TD ± 1 = RD ±

60 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.5.2 Cable DiagnosticStatusRegister(CDSR)

Thisregistergivesthestatusofthecablediagnostictests.Italsoallowsconfiguringdifferentmodes ofthe ALCD and DSA tests. Table8-31.Cable DiagnosticStatusRegister(CDSR), address 0x001B BIT NAME DEFAULT DESCRIPTION

15 ALCD/DSA Done 0,RO 1 = ALCD/DSA isdone

0 = ALCD/DSA isnotdone

14 TDR Fail 1,RO 1 = TDR has failed

0 = TDR has notfailed

13 TDR Done 0,RO 1 = TDR isdone

0 = TDR isnotdone 12:10 Reserved 0x4,RO Ignoreon read 9:6 DSA InputSignal 7,RW 7 = ALCD 5 = DSA Adaptivedatamode 3 = DSA Raw datamode Othersarereserved

5 DSA Enable 0,RW 1 = DSA Engineisenabled

0 = DSA Engineisdisabled

4 ALCD/DSA mode 1,RW 1 = DSA Raw datamode

0 = ALCD/DSA Adaptivedatamode 3:0 Reserved 0,RO Ignoreon read

8.5.3 Cable DiagnosticResultsRegister(CDRR)

Thisregistergivestheresultofthecablediagnostictests.The softwarewillpostprocessthisresult. Table8-32.Cable DiagnosticResultsRegister(CDRR), address 0x001C BIT BIT NAME DEFAULT DESCRIPTION 15:0 CableDiagnosticsResultRegister 0,RO As specifiedinregister0x1A bits[11:8]

8.5.4 TDR StateMachine Enable (TDRSMR)

ThisregisterallowsconfigurationoftheTDR statemachines.Only when thebits15,14 ofthisregisterare setto‘1’theregisters0x0090 and 0x0094 can be used. Table8-33.TDR StateMachine Enable Register(TDRSMR), address 0x0080 BIT NAME TYPE RESET FUNCTION 15 cmn_tdr_sm_mode RW 0 1 = ConfigureTDR statemachine mode. Thisbitisclearedwhen TDR iscomplete 14 cmn_tdr_tx_sm_m RW 0 1 = ConfigureTDR transmitstatemachine mode. Thisbitisclearedwhen theTDR is ode complete. 13:0 Reserved RW 0 Reserved Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 61 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.5.5 TDR PatternAmplitude Register(TDRPAR)

Thisregisterallowstoprogram thepatternused togeneratetheTDR pulses.Bits4:0ofthisregistergive theamplitudeoftheTDR pulse.A valueof0x8 maps toan amplitudeof1V. For valuesfrom0x8 to0xF theamplitudeissaturatedto1V. The TDR patternis16 symbols long.So, sixteenconsecutivewritesto thisregisterarerequired.The valueofthesebitsforeach writedeterminestheamplitudeforthatsymbol. Each symbol is8ns wide.For thisregistertofunction,thebits15,14ofTDRSMR register(0x0080)should be setto‘1’ Table8-34.TDR PatternAmplitude Register(TDRPAR), address 0x0090 BIT NAME DEFAULT FUNCTION 15:5 Reserved 0,RO Ignoreon read 4:0 tdr_pattern_din_config 0,RW ConfigureTDR TransmitPattern.

8.5.6 TDR Manual Pulse Register(TDRMPR)

Thisregisterallowstoprogram a manual TDR pulse.When bit1 ofthisregisterissetthenthepattern programmed inthe TDRPAR registerisput on the TD line.Ifthe TDRPAR registerisnot programmed thena defaultTDR pulseisputon theTD line.ItisNOT used forTDR measurements. Table8-35.TDR Manual Pulse Register(TDRMPR), address 0x0094 BIT NAME DEFAULT FUNCTION 15:2 Reserved 0,RO Ignoreon read 1 tdr_tx_start 0,RW 1 = StartTDR patterntransmission 0 = Do notstartTDR patterntransmission

0 Reserved 0x0,RW Reserved

8.5.7 TDR Channel SilenceRegister(TDRCSR)

ThisregisterallowsprogrammingoftheTDR channelsilencetimers. Table8-36.TDR Channel SilenceRegister(TDRCSR), address 0x0C00 BIT NAME DEFAULT FUNCTION 15:14 Reserved 0,RO Ignoreon read 13:12 cfg_link_down_timer 0x2,RW Holdtime,tomake surethelinkfailed: 0x0 – no holdtime. 0x1 – 500ms holdtime. 0x2 – 1s holdtime. 0x3 – 2s holdtime. 11:10 cfg_post_silence_time 0x1,RW The needed silencetimeaftertheTDR test: 0x0 – no silenceneeded. 0x1 – 10ms ofsilence. 0x2 – 100ms ofsilence. 0x3 – 1s ofsilence. 9:8 cfg_pre_silence_time 0x1,RW The needed silencetimebeforetheTDR test: 0x0 – no silenceneeded. 0x1 – 10ms ofsilence. 0x2 – 100ms ofsilence. 0x3 – 1s ofsilence. 7:0 cfg_silence_th 0xC8,RW Energycalculatorthresholdvalue,tobreaksilence.

62 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.5.8 TDR ControlRegister(TDRCR)

ThisregisterallowsconfiguringtheTDR modes. Table8-37.TDR ControlRegister(TDRCR), address 0x0C01 BIT NAME DEFAULT FUNCTION 15:11 Reserved 0x02,RO Ignoreon read 10 cfg_tdr_tx_mode 0x1,RW 1 – EnableTDR TX transmissionmode

9 Reserved 0,RW Reserved

8:6 cfg_soft_avr_cycles 0x7,RW Number ofaveragingcycles: 0x0 – TDR disabled. 0x1 – 1 TDR cycle(noaveraging). 0x2 – 2 TDR cycles. 0x3 – 4 TDR cycles. 0x4 – 8 TDR cycles. 0x5 – 16 TDR cycles. 0x6 – 32 TDR cycles. 0x7 – 64 TDR cycles. 5:3 cfg_post_cmp_size 0x4,RW Number offorwardsamplesforpeak detectioncomparison. 2:0 cfg_pre_cmp_size 0x3,RW Number ofbackwardsamplesforpeak detectioncomparison.

8.5.9 TDR Clock Cycles Register(TDRLCR)

Thisregisterallowsconfiguringthenumber ofclockcyclesina patternTDR test. Table8-38.TDR Clock Cycles Register(TDRLCR), address 0x0C02 BIT NAME DEFAULT FUNCTION 15:8 Reserved 0,RO Ignoreon read 7:0 cfg_ptrn_cycle_time 0xFF,RW Number ofclockcyclesina TDR patterntest.

8.5.10 TDR Low ThresholdRegister(TDRLT1)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-39.TDR Low ThresholdRegister(TDRLT1),address 0x0C03 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_low_th_1 0xC,RW Peak (absolute)lowthresholdvalue1,forTX pattern. 6:0 cfg_ptrn_low_th_0 0x10,RW Peak (absolute)lowthresholdvalue0,forTX pattern.

8.5.11 TDR Low ThresholdRegister(TDRLT2)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-40.TDR Low ThresholdRegister(TDRLT2),address 0x0C04 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_low_th_3 0x7,RW Peak (absolute)lowthresholdvalue3,forTX pattern. 6:0 cfg_ptrn_low_th_2 0x9,RW Peak (absolute)lowthresholdvalue2,forTX pattern. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 63 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.5.12 TDR Low ThresholdRegister(TDRLT3)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-41.TDR Low ThresholdRegister(TDRLT3),address 0x0C05 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_low_th_5 0x4,RW Peak (absolute)lowthresholdvalue5,forTX pattern. 6:0 cfg_ptrn_low_th_4 0x5,RW Peak (absolute)lowthresholdvalue4,forTX pattern.

8.5.13 TDR Low ThresholdRegister(TDRLT4)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-42.TDR Low ThresholdRegister(TDRLT4),address 0x0C06 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_low_th_7 0x3,RW Peak (absolute)lowthresholdvalue7,forTX pattern. 6:0 cfg_ptrn_low_th_6 0x3,RW Peak (absolute)lowthresholdvalue6,forTX pattern.

8.5.14 TDR High ThresholdRegister(TDRHT1)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-43.TDR High ThresholdRegister(TDRHT1), address 0x0C07 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_High_th_1 0x53,RW Peak (absolute)Highthresholdvalue1,forTX pattern. 6:0 cfg_ptrn_High_th_0 0x53,RW Peak (absolute)Highthresholdvalue0,forTX pattern.

64 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.5.15 TDR High ThresholdRegister(TDRHT2)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-44.TDR High ThresholdRegister(TDRHT2), address 0x0C08 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_High_th_3 0x4A,RW Peak (absolute)Highthresholdvalue3,forTX pattern. 6:0 cfg_ptrn_High_th_2 0x53,RW Peak (absolute)Highthresholdvalue2,forTX pattern.

8.5.16 TDR High ThresholdRegister(TDRHT3)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-45.TDR High ThresholdRegister(TDRHT3), address 0x0C09 BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_High_th_5 0x2F,RW Peak (absolute)Highthresholdvalue5,forTX pattern. 6:0 cfg_ptrn_High_th_4 0x3A,RW Peak (absolute)Highthresholdvalue4,forTX pattern.

8.5.17 TDR High ThresholdRegister(TDRHT4)

Thisregisterallowsconfiguringthethresholdforfindingthepeaks ofthereflectedsignalintheTDR test. Table8-46.TDR High ThresholdRegister(TDRHT4), address 0x0C0A BIT NAME DEFAULT FUNCTION 14:8 cfg_ptrn_High_th_7 0x1F,RW Peak (absolute)Highthresholdvalue7,forTX pattern. 6:0 cfg_ptrn_High_th_6 0x26,RW Peak (absolute)Highthresholdvalue6,forTX pattern.

8.5.18 TDR PatternControlRegister1 (TDRLCR1)

Thisregisterallowsconfiguringtheforwardshadow valuesfortheTDR test. Table8-47.TDR PatternControlRegister1 (TDRLCR1), address 0x0C0B BIT NAME DEFAULT FUNCTION 15:12 Reserved 0,RO Ignoreon read 11:9 cfg_ptrn_fr_shdw_inc 0x1,RW Forwardshadow areafrompeak detectionincrementfactor(X/128). 8:5 cfg_ptrn_init_fr_shdw 0x6,RW Forwardshadow areafrompeak detectioninitialsamplessize. 4:0 cfg_ptrn_init_skip 0x10,RW Initialskip(ignore)samplesnumber fromTx start. Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 65 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.5.19 TDR PatternControlRegister2 (TDRLCR2)

ThisregisterallowsconfiguringthegearthresholdvaluesfortheTDR test. Table8-48.TDR PatternControlRegister2 (TDRLCR2), address 0x0C0C BIT NAME DEFAULT FUNCTION 15:9 Reserved 0,RO Ignoreon read 8:4 cfg_ptrn_gear_tout 0x14,RW Thresholdsgearshiftsdistanceinsamples 3:0 Reserved 0x8,RO Ignoreon read

8.5.20 DSA ConfigurationRegister1 (DSACR1)

Thisregisterallowsuse ofthesmoothingfilterduringtheDSA tests. Table8-49.DSA ConfigurationRegister1 (DSACR1), address 0x0C26 BIT NAME DEFAULT FUNCTION 15:7 Reserved 0x180,RO Ignoreon read 6 cfg_dsa_smooth_filt_byps 0x1,RW 0 = DisableDSA enginesmooth filterbypass 1 = EnableDSA enginesmooth filterbypass 5:0 Reserved 0x04,RO Ignoreon read

8.5.21 DSA ConfigurationRegister2 (DSACR2)

ThisregisterallowsconfigurationoftheDSA tapsareused fortheDSA tests.We specifythefirstand last tapsinuse and theDSA uses allthetapsbetween them. Table8-50.DSA ConfigurationRegister2 (DSACR2), address 0x0C27 BIT NAME DEFAULT FUNCTION 15:8 cfg_dsa_en_last_coeff_num 0x1E,RW Lastcoefficientnumber used by theDSA engine 7:0 cfg_dsa_en_first_coeff_num 0x0,RW Firstcoefficientnumber used by theDSA engine

8.5.22 DSA StartFrequency (DSASFR)

ThisregisterallowsconfigurationofthestartingfrequencyforthespectrumanalysisoftheDSA engine.It represents1.9kHz resolutioninthefrequencydomain. Table8-51.DSA StartFrequency (DSASFR), address 0x0C28 BIT NAME DEFAULT FUNCTION 15:0 cfg_start_freq 0x0,RW StartingfrequencyfortheDSA

8.5.23 DSA Frequency Control(DSAFCR)

Thisregisterdefinestheaveragefactorwe willuse intheDSA. Inadditionitdefinesthefrequencystepfor theDSA. The fieldrepresentsresolutionof119.2Hz. Table8-52.DSA Frequency Control(DSAFCR), address 0x0C29 BIT NAME DEFAULT FUNCTION 15:12 cfg_dsa_average 0xA,RW AveragingfactorforDSA engine– 2X cycles

11 Reserved 0x0,RO Reserved

10:0 cfg_dsa_inc_factor 0x400,RW DSA Frequencyincrementfactor(frequencystep)

66 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

8.5.24 DSA Output Control(DSAOCR)

This registerconfigureswhich DSA outputsare selectedto the 16 bitRAM availablebits.The files configuretheMSB locationoftheDSA engine. Table8-53.DSA Output Control(DSAOCR), address 0x0C2A BIT NAME DEFAULT FUNCTION 15:12 cfg_dsa_output_msb 0x0,RW DSA outputMSB select.SelectwhichbitsoftheDSA outputaresaved inthe RAM 11:0 Reserved 0x003,RO Reserved

8.5.25 RAM Control1 (RAMCR1)

ThisregisterenablestheRAM inordertoreadtheDSA results. Table8-54.RAM Control1 (RAMCR1), address 0x0D00 BIT NAME DEFAULT FUNCTION 15 cpu_ram_en 0x0,RW 1 = EnableCPU accesstoRAM 0 = DisableCPU accesstoRAM 14:0 Reserved 0x0,RO Reserved

8.5.26 RAM Control2 (RAMCR2)

ThisregisterenablesresettingtheRAM memory and addresspriortostartingtheDSA test Table8-55.RAM Control2 (RAMCR2), address 0x0D01 BIT NAME DEFAULT FUNCTION 15 man_cable_diag_restart 0x0,RW 1= Restartcablediagnosticsblockmanual 0 = Do notrestartcablediagnosticsblockmanual 14 man_cable_diag_reset 0x0,RW 1= Softresetofcablediagnosticsblockmanual 0 = Do notresetcablediagnosticsblockmanual 13 reset_ram_addr_indx 0x0,RW 1= ResetRAM addressindex 0 = Do notresetRAM addressindex 12:0 Reserved 0x0,RO Reserved

8.5.27 RAM Data Out (RAMDR)

ThisregisteristheDSA outputresultregister. Table8-56.RAM Data Out (RAMDR), address 0x0D04 BIT NAME DEFAULT FUNCTION 15:0 RAM Data Out 0x0,RW RAM dataout

8.5.28 CD Pre TestConfigurationControl1 (CDPTC1R)

Thisregisterenablescablediagnosticpretestconfiguration. Table8-57.CD Pre TestConfigurationControl1 (CDPTC1R), address 0x0107 BIT NAME DEFAULT FUNCTION 15:9 Reserved 0x0,RO Reserved 8 cd_pre_test_cfg_en 0,RW 1 = EnableCablediagnosticpretestconfiguration 0 = DisableCablediagnosticpretestconfiguration 7:0 Reserved 0,RO Reserved Copyright© 2009,Texas InstrumentsIncorporated RegisterBlock 67 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

8.5.29 CD Pre TestConfigurationControl2 (CDPTC2R)

Thisregisterlatchestheoutcome ofenablingthecablediagnosticpretestconfiguration. Table8-58.CD Pre TestConfigurationControl2 (CDPTC2R), address 0x010F BIT NAME DEFAULT FUNCTION 15:4 Reserved 0x034,RO Reserved 3 cd_pre_test_cfg_latched 0,RW 1 = CableDiagnosticpretestconfigurationislatched 0 = CableDiagnosticpretestconfigurationisnotlatched 2:0 Reserved 0,RO Reserved

8.5.30 LPF Bypass (LPFBR)

ThisregisterenablestobypasstheLPF fortheDSA tests. Table8-59.LPF Bypass (LPFBR),address 0x00AC BIT NAME DEFAULT FUNCTION 15:11 Reserved 0x0,RO Reserved 10 dsa_lpf_bypass 0,RW 1 = Bypass DSA LPF 0 = Do notbypassDSA LPF 9:0 Reserved 0,RO Reserved

68 RegisterBlock Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

9 ElectricalSpecifications

Allparametersarederivedby test,statisticalanalysis,ordesign.

9.1 ABSOLUTE MAXIMUM RATINGS (1)

VDD33_IO, VDD33_VA11, Supplyvoltage –0.3to3.8 V VDD33_V18, VDD33_VD11 V18_PFBIN1, V18_PFBIN2 –0.3to2.2 V VA11_PFBIN1, VA11_PFBIN2 –0.3to1.8 V XI DC Inputvoltage –0.3to2.2 V TD-,TD+, RD-,RD+ –0.3to6 V OtherInputs –0.3to3.8 V XO DC Outputvoltage –0.3to2.2 V Otheroutputs –0.3to3.8 V Maximum dietemperatureθJ 105 °C IEC 60749-26ESD (human-bodymodel)(2) ±16 kV JEDEC Standard22,TestMethod A114 (human-bodymodel)(2) ±16 ESD JEDEC Standard22,TestMethod A114 (human-bodymodel),allpins 1.5 JEDEC Standard22,TestMethod C101 (charged-devicemodel),allpins 1.5 (1) Stressesbeyond thoselistedunder“absolutemaximum ratings”may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) On pinsTD+, TD-,RD+, RD-,withVDD33_IO, VDD33_VA11 VDD33_V18, VDD33_VD11, V18_PFBIN1, V18_PFBIN2, VA11_PFBIN1, VA11_PFBIN2, VA11_PFBOUT, V18_PFBOUT, VDD11, VSS connectedtogroundpotential.

9.2 THERMAL CHARACTERISTICS

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER MIN TYP MAX UNIT θJA Junction-to-ambientthermalresistance(noairflow) 26.8 θJB Junction-to-boardthermalresistance 16.2 °C/W θJC Junction-to-casethermalresistance 40

9.3 RECOMMENDED OPERATING CONDITIONS

VDD33_VA11,VDD33_V18, Core Supplyvoltage 2.38 3.3 3.6 V VDD33_VD11 VDD33_IO I/O3.3VSupply 3.0 3.3 3.6 V V18_PFBIN1, ExternalSupply(1) 1.7 1.8 1.9 V V18_PFBIN2 VA11_PFBIN1, 1.04 1.1 1.15 V VA11_PFBIN2 TA Ambienttemperature(2) –40 85 °C PD Power dissipation(3) 189 mW (1) When theinternalvoltageregulatorisnotused and theexternalsupplyisused (2) ProvidedthatGNDPAD, pin49,issoldereddown. See ThermalViasRecommendation formore detail. (3) For100Base-TX,When external1.8V,1.1and 3.3Vsuppliesareused. Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com

9.4 DC CHARACTERISTICS

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Inputhighvoltage(1) 2.0 V VIL Inputlowvoltage(1) 0.8 V IIH Inputhighcurrent VIN = VCC 10 μA IIL Inputlowcurrent VIN = GND 10 μA VOL Outputlowvoltage IOL = 4 mA 0.4 V VOH Outputhighvoltage IOH = –4 mA VCC – 0.5 V IOZ 3-Stateleakage VOUT = VCC ,VOUT = GND ±10 μA VTPTD_100 100M transmitvoltage 0.95 1 1.05 V VTPTDsym 100M transmitvoltagesymmetry ±2% VTPTD_10 10M transmitvoltage 2.2 2.5 2.8 V C IN1 CMOS inputcapacitance 5 pF COUT1 CMOS outputcapacitance 5 pF mV diffSD THon 100BASE-TX Signaldetectturnonthreshold 1000 pk-pk mV diffSD THoff 100BASE-TX Signaldetectturnoffthreshold 200 pk-pk VTH1 10BASE-T Receivethreshold 585 mV (1) NominalVCC ofVDD33_IO = 3.3V

9.5 POWER SUPPLY CHARACTERISTICS

The data was measured from a TLK100 evaluationboard.The currentfrom each of the power supplyis measured and thepower dissipationiscomputed.For thesingle3.3V externalsupplycase thepower dissipation acrossthe internallinearregulatorisalsoincluded.Allthe power dissipationnumbers are measured at the nominalpower supplyand typicaltemperatureof25°C.

9.5.1 ActivePower

PARAMETER TEST CONDITIONS FROM THE FROM THE UNIT POWER SUPPLIES CENTER TAP MultipleExternalSupplies 146 43 100BASE-T /W Traffic(fullpacket1518B rate) Single3.3Vexternalsupply 316 80 mW MultipleExternalSupplies 84 205 10BASE-T /W Traffic(fullpacket1518B rate) Single3.3Vexternalsupply 189 205

9.5.2 Power Down Power

PARAMETER TEST CONDITIONS FROM THE POWER SUPPLIES UNIT MultipleExternalSupplies 14.2 ExtremeLow Power Mode Single3.3Vexternalsupply 23.1 MultipleExternalSupplies 18.2 GeneralPower Down Mode (1) Single3.3Vexternalsupply 33 mW MultipleExternalSupplies 51.4 PassiveSleepMode Single3.3Vexternalsupply 102.3 MultipleExternalSupplies 51.4 ActiveSleepMode Single3.3Vexternalsupply 102.3 (1) The internalPLL isdisabled.System worksoftheRefclk

70 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

XI□Clock Hardware RESET_N Dual□Function□Pins Become□Enabled As□Outputs Input Output T0338-01 VCC XI□Clock Hardware RESET_N T0339-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

9.6 AC Specifications

Table9-1.Power Up Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 Resetdeassertiontimefrompower up 200 μs Time fromresetdeassertiontothehardware Hardware ConfigurationPinsaredescribedint2 46 nsconfigurationpinstransitiontooutputdrivers thePinDescriptionsection. Figure9-1.Power Up Timing NOTE Itis importantto choose pull-upand/orpull-downresistorsforeach of the hardware configurationpinsthatprovidefastRC timeconstantsinordertolatch-inthepropervalue priortothepintransitioningtoan outputdriver. Table9-2.Reset Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT XIClockmust be stableforatmin.of1mst1 RESET pulsewidth 1 μsduringRESET pulselowtime. Figure9-2.Reset Timing Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

MDIO (Output) MDIO (Input) V alid Data T0340-01 TX_CLK TXD[3:0] TX_EN V alid Data T0341-01 t1 t2 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-3.MIISerialManagement Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 MDC Frequency 2.5 25 MHz t2 MDC toMDIO (Output)DelayTime 0 ns t3 MDIO (Input)toMDC HoldTime 10 ns t4 MDIO (Input)toMDC SetupTime 10 ns Figure9-3.MIISerialManagement Timing Table9-4.100Mb/s MIITransmitTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_CLK HighTime

100 Mb/s Normal mode 16 20 24 ns

t2 TX_CLK Low Time t3 TXD[3:0],TX_EN Data SetuptoTX_CLK 100 Mb/s Normal mode 10 ns t4 TXD[3:0],TX_EN Data HoldfromTX_CLK 100 Mb/s Normal mode 0 ns Figure9-4.100Mb/s MIITransmitTiming

72 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

RX_CLK V alid Data RXD[3:0] RX_DV RX_ER T0342-01 t1 t2 TX_CLK TX_EN TXD PMD Output Pair (J/K)IDLE DA T A T0343-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table9-5.100Mb/s MIIReceive Timing PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT t1 RX_CLK HighTime t2 RX_CLK Low Time t3 RX_CLK toRXD[3:0],RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns (1) RX_CLK may be heldloworhighfora longerperiodoftimeduringtransitionbetween referenceand recoveredclocks.Minimum high and lowtimeswillnotbe violated. Figure9-5.100Mb/s MIIReceive Timing Table9-6.100BASE-TX TransmitPacket Latency Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_CLK toPMD OutputPairLatency 100 Mb/s Normal mode (1) 8.6 bits (1) ForNormal mode, latencyisdeterminedby measuringthetimefromthefirstrisingedge ofTX_CLK occurringaftertheassertionof TX_EN tothefirstbitofthe'J'code groupas outputfromthePMD OutputPair.1 bittime= 10ns in100 Mb/s mode. Figure9-6.100BASE-TX TransmitPacket Latency Timing Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

TX_CLK TXD TX_EN PMD Output Pair (T/R)DA T A IDLE (T/R)DA T A IDLE T0344-01 PMD Output Pair +1 rise +1□fall –1□fall –1 rise 90% 10% 10% 90% PMD□Output Pair Eye□Pattern T0345-01 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-7.100BASE-TX TransmitPacket DeassertionTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_CLK toPMD OutputPairdeassertion 100 Mb/s Normal mode 8.6 bits Figure9-7.100BASE-TX TransmitPacket Latency Timing Table9-8.100BASE-TX TransmitTiming (tR/F and Jitter) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

100 Mb/s PMD OutputPairtR and tF

(1) 3 4 5 ns

100 Mb/s tR and tF Mismatch(2) 500 ps

t2 100 Mb/s PMD OutputPairTransmitJitter 1.4 ns (1) Riseand falltimestakenat10% and 90% ofthe+1 or-1amplitude. (2) Normal Mismatchisthedifferencebetween themaximum and minimum ofallriseand falltimes. Figure9-8.100BASE-TX TransmitTiming (tR/F and Jitter)

74 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

IDLE (J/K) Data CRS PMD□Input□Pair RXD[3:0] RX_DV RX_ER T0346-01 DATA (T/R) IDLEPMD□Input□Pair CRS T0347-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table9-9.100BASE-TX Receive Packet Latency Timing PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT t1 CarrierSense ON Delay(2) 100 Mb/s Normal mode 13.6 bits(3) t2 ReceiveData Latency 100 Mb/s Normal mode 18.4 bits (1) PMD InputPairvoltageamplitudeisgreaterthantheSignalDetectTurn-OnThresholdValue. (2) CarrierSense On Delayisdeterminedby measuringthetimefromthefirstbitofthe“J”code grouptotheassertionofCarrierSense. (3) 1 bittime= 10 ns in100 Mb/s mode Figure9-9.100BASE-TX Receive Packet Latency Timing Table9-10.100BASE-TX Receive Packet DeassertionTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 CarrierSense OFF Delay(1) 100 Mb/s Normal mode 13.6 bits(2) (1) CarrierSense OffDelayisdeterminedby measuringthetimefromthefirstbitofthe“T”code grouptothedeassertionofCarrierSense. (2) 1 bittime= 10 ns in100 Mb/s mode Figure9-10.100BASE-TX Receive Packet DeassertionTiming Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

TX_CLK V alid DataTXD[3:0] TX_EN T0348-01 RX_CLK V alid DataRXD[3:0] RX_DV T0349-01 t1 t2 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-11.10 Mb/s MIITransmitTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_CLK Low Time

10 Mb/s MIImode 190 200 210 ns

t2 TX_CLK HighTime t3 TXD[3:0],TX_EN Data SetuptoTX_CLK ↓ 10 Mb/s MIImode 25 ns t4 TXD[3:0],TX_EN Data HoldfromTX_CLK ↑ 10 Mb/s MIImode 0 ns Figure9-11.10 Mb/s MIITransmitTiming Table9-12.10Mb/s MIIReceive Timing PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT t1 RX_CLK HighTime 160 200 240 ns t2 RX_CLK Low Time t3 RX_CLK risingedge delayfromRXD[3:0],RX_DV Valid 10 Mb/s MIImode 100 ns t4 RX_CLK toRXD[3:0],RX_DV Delay 10 Mb/s MIImode 100 ns (1) RX_CLK may be heldlowfora longerperiodoftimeduringtransitionbetween referenceand recoveredclocks.Minimum highand low timeswillnotbe violated. Figure9-12.10Mb/s MIIReceive Timing

76 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

TX_CLK TX_EN TXD PMD Output Pair TX_CLK TX_EN PMD Output Pair 0 0 1 1PMD Output Pair TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table9-13.10BASE-T TransmitTiming (StartofPacket) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) t1 TransmitOutputDelayfromtheFallingEdge ofTX_CLK 10 Mb/s MIImode 5.8 bits (1) (1)1 bittime= 100ns in10Mb/s. Figure9-13.10BASE-T TransmitTiming (StartofPacket) Table9-14.10BASE-T TransmitTiming (End ofPacket) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 End ofPacketHighTime (with‘0’endingbit) 250 310 ns t2 End ofPacketHighTime (with‘1’endingbit) 250 310 ns Figure9-14.10BASE-T TransmitTiming (End ofPacket) Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

1 SFD□Bit□Decodedst

RX_CLK RX_DV RXD[3:0] 0000 Preamble SFD Data T0354-01 1 0 1 IDLE PMD□Input□Pair RX_CLK CRS TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-15.10BASE-T Receive Timing (StartofPacket) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 CarrierSense TurnOn Delay(PMD InputPairtoMII_CRS) 550 1000 ns t2 RX_DV Latency(1) 9.3 bits Measurement shown fromt3 ReceiveData Latency 14 bitsSFD (1) 10BASE-T RX_DV Latencyismeasured fromfirstbitofdecoded SFD on thewiretotheassertionofRX_DV Figure9-15.10BASE-T Receive Timing (StartofPacket) Table9-16.10BASE-T Receive Timing (End ofPacket) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 CarrierSense TurnOffDelay 1.3 μs Figure9-16.10BASE-T Receive Timing (End ofPacket)

78 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

Normal□Link□Pulse(s) T0358-01 Fast□Link□Pulse(s) Clock Pulse Data Pulse Clock Pulse FLP Burst FLP Burst T0359-01 t3 t3 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table9-17.10Mb/s Jabber Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 JabberActivationTime 100 ms Figure9-17.10Mb/s Jabber Timing Table9-18.10BASE-T Normal LinkPulse Timing PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT t1 PulsePeriod 16 ms t2 PulseWidth 100 ns (1) Transmittiming Figure9-18.10BASE-T Normal LinkPulse Timing Table9-19.Auto-NegotiationFastLinkPulse (FLP)Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 ClockPulsetoClockPulsePeriod 125 μs t2 ClockPulsetoData PulsePeriod Data = 1 62 μs t3 Clock,Data PulseWidth 114 ns t4 FLP BursttoFLP BurstPeriod 16 ms t5 BurstWidth 2 ms Figure9-19.Auto-NegotiationFastLinkPulse (FLP)Timing Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

PMD□Input□Pair SD+□Intermal T0360-01 t1 t2 TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] T0361-01 TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-20.100BASE-TX SignalDetectTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 SD InternalTurn-onTime 100 μs t2 SD InternalTurn-offTime 500 μs NOTE: The signalamplitudeon PMD InputPairmust be TP-PMD compliant. Figure9-20.100BASE-TX SignalDetectTiming Table9-21.100 Mb/s InternalLoopback Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_EN toRX_DV Loopback 100 Mb/s internalloopbackmode 272 ns (1) Due to the natureof the descramblerfunction,all100BASE-TX Loopback modes willcause an initialdead-timeof up to 550 μs duringwhich timeno dataispresentatthereceiveMIIoutputs.The 100BASE-TX timingspecifiedisbased on devicedelaysafter theinitial550µs dead-time. (2) Measurement ismade fromthefirstrisingedge ofTX_CLK afterassertionofTX_EN. Figure9-21.100 Mb/s InternalLoopback Timing

80 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] T0362-01 ISOLATE NORMALMODE H/W□or□S/W□Reset T0365-01 TLK100 www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 Table9-22.10 Mb/s InternalLoopback Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 TX_EN toRX_DV Loopback 10 Mb/s internalloopbackmode 2.4 μs NOTE: Measurement ismade fromthefirstrisingedge ofTX_CLK afterassertionofTX_EN. Figure9-22.10 Mb/s InternalLoopback Timing Table9-23.IsolationTiming PARAMETER TEST CONDITIONS MIN TYP MAX UNIT From DeassertionofS/W orH/W ResettotransitionfromIsolatetoNormalt1 65 nsmode Figure9-23.IsolationTiming Copyright© 2009,Texas InstrumentsIncorporated ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

25□MHz_OUT T0366-01 t2 t3 RX_CLK V alid Data RXD[3:0] RX_DV RX_ER TLK100 SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com Table9-24.25 MHz_OUT Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 25 MHz_OUT (1)propagationdelay RelativetoXI 8.8 ns t2 25 MHz_OUT (1)HighTime 20 MIImode ns t3 25 MHz_OUT (1)Low Time 20 (1) 25 MHz_OUT characteristicsaredependentupon theXIinputcharacteristics. Figure9-24.25 MHz_OUT Timing Table9-25.100 Mb/s MIILoopback Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 RX_CLK toRXD[3:0],RX_DV, RX_ER Delay 100 Mb/s MIILoopback mode 1 ns Figure9-25.100 Mb/s MIILoopback Timing

82 ElectricalSpecifications Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

www.ti.com SLLS931B –AUGUST 2009–REVISED DECEMBER 2009

10 Appendix A: DigitalSpectrum Analyzer(DSA) Output

The followingfigureisan example oftheDSA output.Inthefigure,512 samplesofthespectralanalysisof 4 differentcablelengthsare provided.The firstbinis23.4 MHz. Each followingbinrepresents61kHz increment.A view of the LPF natureof the channeland how itincreasesas longercablesare used is seen. Copyright© 2009,Texas InstrumentsIncorporated AppendixA:DigitalSpectrumAnalyzer(DSA) Output 83 SubmitDocumentationFeedback ProductFolderLink(s):TLK100

SLLS931B –AUGUST 2009–REVISED DECEMBER 2009 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion.

• Changed notefrom"On pinsTD+, TD-,RD+, RD-,VDD33_IO, VDD33_VA11 VDD33_V18, VDD33_VD11, V18_PFBIN1, V18_PFBIN2, VA11_PFBIN1, VA11_PFBIN2, VA11_PFBOUT, V18_PFBOUT, VDD11, VSS."to

84 AppendixA:DigitalSpectrumAnalyzer(DSA) Output Copyright© 2009,Texas InstrumentsIncorporated

SubmitDocumentationFeedback ProductFolderLink(s):TLK100

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLK100PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLK100PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2009 Addendum-Page 1

Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,modifications,enhancements,improvements, and otherchanges toitsproductsand servicesatany timeand todiscontinueany productorservicewithoutnotice.Customersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allproductsare soldsubjecttoTI’s termsand conditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standard warranty.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessarytosupportthiswarranty.Exceptwhere mandated by governmentrequirements,testingofallparametersofeach productisnotnecessarilyperformed. TIassumes no liabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithcustomerproductsand applications,customersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany TIpatentright,copyright,mask work right, orotherTIintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIproductsorservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensefromTItouse such productsorservicesora warrantyorendorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectual propertyofthethirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalterationand isaccompanied by allassociatedwarranties,conditions,limitations,and notices.Reproductionofthisinformationwithalterationisan unfairand deceptive businesspractice.TIisnotresponsibleorliableforsuch altereddocumentation.Informationofthirdpartiesmay be subjecttoadditional restrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatproductorservicevoidsall expressand any impliedwarrantiesfortheassociatedTIproductorserviceand isan unfairand deceptivebusinesspractice.TIisnot responsibleorliableforany such statements. TIproductsarenotauthorizedforuse insafety-criticalapplications(suchas lifesupport)where a failureoftheTIproductwouldreasonably be expectedtocause severepersonalinjuryordeath,unlessofficersofthepartieshave executedan agreementspecificallygoverning such use.Buyersrepresentthattheyhave allnecessaryexpertiseinthesafetyand regulatoryramificationsoftheirapplications,and acknowledgeand agreethattheyaresolelyresponsibleforalllegal,regulatoryand safety-relatedrequirementsconcerningtheirproducts and any use ofTIproductsinsuch safety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmay be providedby TI.Further,Buyersmust fullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsin such safety-criticalapplications. TIproductsareneitherdesignednorintendedforuse inmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedby TIas military-gradeor"enhanced plastic."Onlyproductsdesignatedby TIas military-grademeet military specifications.Buyersacknowledgeand agreethatany such use ofTIproductswhichTIhas notdesignatedas military-gradeissolelyat theBuyer's risk,and thattheyaresolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIproductsareneitherdesignednorintendedforuse inautomotiveapplicationsorenvironmentsunlessthespecificTIproductsare designatedby TIas compliantwithISO/TS 16949 requirements.Buyersacknowledgeand agreethat,iftheyuse any non-designated productsinautomotiveapplications,TIwillnotbe responsibleforany failuretomeet such requirements. FollowingareURLs where you can obtaininformationon otherTexas Instrumentsproductsand applicationsolutions: Products Applications Audio www.ti.com/audio Communicationsand Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP ® Products www.dlp.com Energyand Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocksand Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportationand www.ti.com/automotive Automotive Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IFand ZigBee® Solutions www.ti.com/lprf TIE2E Community Home Page e2e.ti.com MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2011,Texas InstrumentsIncorporated