TLIN2027DRQ1

TLIN2027-Q1 TI1 | Alldatasheet

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Technical content

1 kŸ LIN Bus Master Node Pullup 3 78 220 pF VBAT NC NC Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLIN2027-Q1 SLLSF59 –JULY 2020–REVISED JULY 2020 TLIN2027-Q1FaultProtectedLocalInterconnectNetwork(LIN)Transceiver

1 Features

1• AEC-Q100 Qualified for automotive applications – Temperature grade 1: –40°C to 125°C TA – Device HBM certification level: ±8 kV – Device CDM certification level: ±1.5 kV

• Compatible with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4.2 (See Switching Characteristics)
• Compatible with SAE J2602 recommended practice for LIN
• Supports ISO 9141 (K-Line)
• Supports 24 V applications
• LIN transmit data rate up to 20-kbps
• Wide operating ranges – 4-V to 48-V Supply voltage – ±58-V LIN bus fault protection
• Sleep mode: ultra-low current consumption allows wake-up event from: – LIN bus – Local wake up through EN
• Power up and down glitch free operation
• Protection features: – Under voltage protection on VSUP – Thermal shutdown protection – Unpowered node or ground disconnection failsafe at system level.
• Available in SOIC (8) and leadless VSON (8) packages with improved automated optical inspection (AOI) capability

2 Applications

• Body electronics and lighting
• Infotainment and cluster
• Hybrid electric vehicles and power train systems
• Passive safety
• Appliances

3 Description

The TLIN2027-Q1 is a local interconnect network (LIN) physical layer transceiver with integrated wake- up and protection features, compatible with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4.2 standards. LIN is a single-wire bidirectional bus typically used for low speed in-vehicle networks using data rates up to 20 kbps. The TLIN2027-Q1 is designed to support 24-V applications with wider operating voltage and additional bus-fault protection. The LIN receiver supports data rates up to 100 kbps for faster in-line programming. The TLIN2027-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. Ultra-low current consumption is possible using the sleep mode which allows wake-up via LIN bus or EN pin. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLIN2027-Q1 SOIC (D) (8) 4.90 mm x 3.91 mm VSON (DRB) (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematics, Master Mode Simplified Schematics, Slave Mode

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13.2 Receiving Notification of Documentation Updates 28

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2020 * Initial release.

5 Description (continued)

The integrated resistor, electrostatic discharge (ESD) and fault protection allows designers to save board space in their applications.

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6 Pin Configuration and Functions

8-Pin (SOIC) Top View 8-Pin (VSON) Top View Pin Functions PIN Type DESCRIPTION Name No. RXD 1 DO RXD output (open-drain) interface reporting state of LIN bus voltage EN 2 DI Enable input - High puts the device in normal operation mode and low puts the device in sleep mode NC 3 – Not connected TXD 4 DI TXD input interface to control state of LIN output - Internally pulled to ground GND 5 GND Ground LIN 6 HV I/O LIN bus single-wire transmitter and receiver VSUP 7 HV Supply Device supply voltage (connected to battery in series with external reverse blocking diode) NC 8 – Not connected Thermal Pad GND No electrical connection. Can bve connected to the PCB to improve thermal coupling (DRB package only)

SLLSF59 –JULY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: TLIN2027-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) Symbol Parameter MIN MAX UNIT VSUP Supply voltage range (ISO/DIS 17987 Param 10) –0.3 60 V VLIN LIN bus input voltage (ISO/DIS 17987 Param 82) –60 60 V VLOGIC Logic pin voltage (RXD, TXD, EN) –0.3 6 V TA Ambient temperature range –40 125 °C TJ Junction temperature range –55 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) LIN bus is stressed with respect to GND.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM) TXD, RXD, EN Pins, per AEC Q100- 002(1) ±4000 VHuman body model (HBM) LIN and VSUP Pin, per AEC Q100- 002(2) ±8000 Charged device model (CDM), per AEC Q100-011 All terminals ±1500 (1) IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different system level configurations may lead to different results (2) SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request (3) ISO 7637 is a system level transient test. Different system level configurations may lead to diffrent results

7.3 ESD Ratings - IEC

ESD and Surge Protection Ratings VALUE UNIT V(ESD) Electrostatic discharge(1) ISO 10605 per IEC 62228-3 Contact discharge R = 300 Ω, C = 150 pF ±8000 V V(ESD) Powered ESD Performance, per SAEJ2962-1(2) contact discharge ±8000 V air-gap discharge ±25000 ISO 7637-2 and IEC 62215-3 transients according to IBEE LIN EMC test specifications(3) (LIN and VSUP) Pulse 1 –100 V Pulse 2 75 V Pulse 3a –150 V Pulse 3b 100 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) UNITD (SOIC) DRB (VSON) 8-PINS 8-PINS RΘJA Junction-to-ambient thermal resistance 115.5 48.5 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 58.7 55.5 °C/W RΘJB Junction-to-board thermal resistance 58.9 22.2 °C/W ΨJT Junction-to-top characterization parameter 14.1 1.2 °C/W ΨJB Junction-to-board characterization parameter 58.2 22.2 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance 4.8 °C/W

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7.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER - DEFINITION MIN NOM MAX UNIT VSUP Supply voltage 4 48 V VLIN LIN Bus input voltage 0 48 V VLOGIC Logic Pin Voltage (RXD, TXD, EN) 0 5.25 V TSD Thermal shutdown temperature 165 °C TSD(HYS) Thermal shutdown hysteresis 15 °C

7.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply VSUP Operational supply voltage (ISO/DIS

17987 Param 10, 53)

Device is operational beyond the LIN defined nominal supply voltage range See Figure 1 and Figure 2 4 48 V VSUP Nominal supply voltage (ISO/DIS 17987 Param 10, 53) Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 1 and Figure 2 4 48 V Sleep Mode 4 48 V UVSUP Under voltage VSUP threshold Min is falling edge and Max is rising edge 2.9 3.85 V UVHYS Delta hysteresis voltage for VSUP under voltage threshold 0.2 V ISUP Supply current Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 7) 5 mA Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF (See Figure 7) 1 2.1 mA ISUP Supply current Normal Mode: EN = high, bus recessive (LIN = VSUP) 400 700 µA Standby Mode: EN = low, bus recessive (LIN = VSUP) 20 35 µA Sleep Mode: 4.0 V < VSUP ≤ 27 V, LIN = VSUP, EN = 0 V, TXD and RXD floating 9 15 µA Sleep Mode: 27 V < VSUP ≤ 48 V, LIN = VSUP, EN = 0 V, TXD and RXD floating 30 µA TSD Thermal shutdown 165 ℃ TSD(HYS) Thermal shutdown hysteresis 15 ℃ RXD OUTPUT PIN (OPEN DRAIN) VOL Output low voltage RPU = 2.4 kΩ 0.6 V IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA IILG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 µA TXD INPUT PIN VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.5 V IILG Low level input leakage current TXD = low –5 0 5 µA RTXD Internal pull-down resistor value 125 350 800 kΩ LIN PIN

SLLSF59 –JULY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: TLIN2027-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) LIN driver bus load conditions (CLIN, RLIN): No external load VOH HIGH level output voltage LIN recessive, TXD = high, IO = 0 mA, VSUP = 7 V to 48 V(1) 0.85 VSUP LIN recessive, TXD = high, IO = 0 mA, VSUP = 4 V ≤ VSUP < 7 V(1) 3 V VOL LOW level output voltage LIN dominant, TXD = low, VSUP = 7 V to 48 V(1) 0.2 VSUP LIN dominant, TXD = low, VSUP = 4 V ≤ VSUP < 7 V(1) 1.2 V VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11, 54/56) TXD & RXD open LIN = 4 V to 58 V –0.3 58 V IBUS_LIM Limiting current (ISO/DIS 17987 Param 12, 57) TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V, VBUSdom < 4.518 V See Figure 6 40 90 200 mA IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13, 58) LIN = 0 V, VSUP = 24 V Driver off/recessive Figure 7 –1 mA IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) LIN > VSUP, 4 V ≤ VSUP ≤ 45 V Driver off; Figure 8 20 µA IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14, 59) LIN = VSUP, Driver off; Figure 8 –5 5 µA IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) GND = VSUP, VSUP = 27 V, LIN = 0 V; Figure 9 –1 1 mA IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15, 60) GND = VSUP, VSUP ≥ 36 V, LIN = 0 V; Figure 9 –1.5 1.5 mA IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS

17987 Param 16, 61) LIN = 48 V, VSUP = GND; Figure 10 5 µA

Low level input voltage (ISO/DIS 17987 Param 17, 62) LIN dominant (including LIN dominant for wake up) See Figure 4, Figure 3 0.4 VSUP VBUSrec High level input voltage (ISO/DIS 17987 Param 18, 63) LIN recessive See Figure 4, Figure 3 0.6 VSUP VBUS_CNT Receiver center threshold (ISO/DIS

17987 Param 19, 64)

VBUS_CNT = (VIL + VIH)/2 See Figure 4, Figure 3 0.475 0.5 0.525 VSUP VHYS Hysteresis voltage (ISO/DIS 17987 Param 20, 65) VHYS = (VIL - VIH) See Figure 4, Figure 3 0.175 VSUP VSERIAL_DIODE Serial diode LIN term pull-up path By design and characterization 0.4 0.7 1 V RSLAVE Internal pull-up resistor to VSUP Normal and standby modes 20 45 60 kΩ IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 27 V, LIN = GND –2 –20 µA CLINPIN Capacitance of the LIN pin VSUP = 14 V 25 pF EN INPUT PIN VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.5 V VIT Hysteresis voltage By design and characterization 50 500 mV IILG Low level input current EN = low –5 0 5 µA REN Internal pull-down resistor 125 350 800 kΩ

www.ti.com SLLSF59 –JULY 2020–REVISED JULY 2020 Product Folder Links: TLIN2027-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) Duty cycles: LIN driver bus load conditions (CLIN, RLIN): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω, Load3 = 6.8 nF, 660 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TLIN2027 also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D112V Duty Cycle 1 (ISO/DIS 17987 Param 27)(1) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7.4 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.396 D112V Duty Cycle 1 THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.368 D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 9.4 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.396 D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4 V to 7.4 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.581 D212V Duty Cycle 2 THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.67 D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 9.4 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.581 D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.417 D312V Duty Cycle 3 THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.417 D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 4.6 V to 7.4 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.59 D412V Duty Cycle 4 THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.4 V to 9.4 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.6 D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.4 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.59 D124V Duty Cycle 1 (ISO/DIS 17987 Param 72)(1) THREC(MAX) = 0.710 x VSUP, THDOM(MAX) = 0.544 x VSUP, VSUP = 15 V to 36 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.33 D224V Duty Cycle 2 (ISO/DIS 17987 Param 73) THREC(MIN) = 0.446 x VSUP, THDOM(MIN) = 0.302 x VSUP, VSUP = 15.6 V to 36 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.642

SLLSF59 –JULY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: TLIN2027-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D324V Duty Cycle 3 (ISO/DIS 17987 Param 74) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 36 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.386 D324V Duty Cycle THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11, Figure 12) 0.386 D424V Duty Cycle 4 (ISO/DIS 17987 Param 75) THREC(MIN) = 0.442 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4.6 V to 36 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11, Figure 12) 0.591

7.8 Timing Requirements

SYMBOL DESCRIPTION TEST CONDITIONS MIN NOM MAX UNIT trx_pdr, trx_pdf Receiver rising propagation delay time (ISO/DIS 17987 Param 31, 76) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 13 and Figure 14 ) 6 µs trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 13 and Figure 14 ) –2 2 µs tLINBUS LIN wakeup time (Minimum dominant time on LIN bus for wakeup) See Figure 17, Figure 20, and Figure 21 25 65 150 µs tCLEAR Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) See Figure 21 8 25 50 µs tMODE_CHANGE Mode change delay time Time to change from standby mode to normal mode or normal mode to sleep mode through EN pin (See Figure 15 and Figure 22) 2 15 µs tNOMINT Normal mode initialization time Time for normal mode to initialize and data on RXD pin to be valid See Figure 15 35 µs tPWR Power up time Upon power up time it takes for valid data on RXD 1.5 ms

7.9 Typical Characteristics

8 Parameter Measurement Information

Figure 1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10 Figure 2. RX Response: Operating Voltage Range Figure 3. LIN Bus Input Signal

Figure 12. Definition of Bus Timing Parameters

& Protection Filter Wake Up State & Control EN NC VSUP LIN RXD TXD VSUP/2 350 kŸ 45 kŸ NC DR/ Slope CTL 350 kŸ Comp TLIN2027-Q1 SLLSF59 –JULY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: TLIN2027-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The TLIN2027-Q1 is a Local Interconnect Network (LIN) physical layer transceiver, compatible with LIN 2.0, LIN LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks using data rates from 2.4 kbps to 20 kbps. The TLIN2027-Q1 LIN receiver works up to 100 kbps supporting in-line programming. The LIN protocol data stream on the TXD input is converted by the TLIN2027-Q1 into a LIN bus signal using a current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up components are required for slave applications. Master applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification. The TLIN2027-Q1 provides many protection features such as immunity to ESD and high bus standoff voltage. The device also provides two methods to wake up: EN pin and from the LIN bus.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 LIN (Local Interconnect Network) Bus

This high voltage input/output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive transient voltages up to 60 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking diodes, even in the event of a ground shift or loss of supply (VSUP).

9.3.1.1 LIN Transmitter Characteristics

resistor and series diode to VSUP must be added when the device is used for a master node application.

9.3.1.2 LIN Receiver Characteristics

up resistance) and driver characteristics used in the system.

9.3.1.2.1 Termination

be added when the device is used for master node applications as per the LIN specification. Figure 19. Master Node Configuration with Voltage Levels

9.3.2 TXD (Transmit Input and Output)

9.3.3 RXD (Receive Output)

ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.

9.3.4 VSUP (Supply Voltage)

(ignition supplied) while the rest of the network remains powered (battery supplied).

9.3.5 GND (Ground)

9.3.6 EN (Enable Input)

has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.

9.3.7 Protection Features

The TLIN2027-Q1 has several protection features that will now be described.

9.3.8 Bus Stuck Dominant System Fault: False Wake Up Lockout

waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. dominant, preventing excessive current use. Figure 20 and Figure 21 show the behavior of this protection. Figure 20. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup

Figure 21. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup

9.3.9 Thermal Shutdown

the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains on.

9.3.10 Under Voltage on VSUP

when VSUP is less than UVSUP.

9.3.11 Unpowered Device and LIN Bus

the bus so an unpowered node does not affect the network or load it down.

9.4 Device Functional Modes

shows the relationship while Table 1 shows the state of pins. Table 1. Operating Modes Figure 22. Operating State Diagram

9.4.1 Normal Mode

tMODE_CHANGE plus tNOMINT.

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9.4.2 Sleep Mode

Sleep mode is the power saving mode for the TLIN2027-Q1. Sleep mode is only entered when the EN pin is low and from normal mode. Even with extremely low current consumption in this mode, the TLIN2027-Q1 can still wake up from LIN bus through a wake up signal or if EN is set high for > tMODE_CHANGE. The LIN bus is filtered to prevent false wake up events. The wake up events must be active for the respective time periods (tLINBUS). The sleep mode is entered by setting EN low for longer than tMODE_CHANGE. While the device is in sleep mode, the following conditions exist.

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.

9.4.3 Standby Mode

This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The LIN bus slave termination circuit is turned on when standby mode is entered. Standby mode is signaled through a low level on RXD. See Standby Mode Application Note for more application information. When EN is set high for longer than tMODE_CHANGE while the device is in standby mode, the device returns to normal mode. The normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.

9.4.4 Wake Up Events

There are two ways to wake up from sleep mode:

• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN bus where the dominant state is be held for tLINBUS filter time. After this tLINBUS filter time has been met and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up event, eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than tMODE_CHANGE.

9.4.4.1 Wake Up Request (RXD)

When the TLIN2027-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal mode, the RXD pin is releases the wake up request signal and the RXD pin then reflects the receiver output from the LIN bus.

9.4.4.2 Mode Transitions

When the TLIN2027-Q1 is transitioning from normal to sleep or standby modes the device needs the time tMODE_CHANGE to allow the change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep or standby to normal mode the device needs tMODE_CHANGE plus tNOMINT.

24 V VBAT

validate and test their design implementation to confirm system functionality.

10.1 Application Information

with the ability to support both remote wake up request and local wake up request.

10.2 Typical Application

both master and slave applications. (1) If RXD on MCU on LIN slave has internal pullup; no external pullup resistor is needed. (2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor. (3) Master node applications require and external 1 kΩ pullup resistor and serial diode. (4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥ 10 µF. Figure 23. Typical LIN Bus

10.2.1 Design Requirements

device should be decoupled with a 100-nF capacitor as close to the supply pin of the device as possible.

10.2.2 Detailed Design Procedures

10.2.2.1 Normal Mode Application Note

10.2.2.2 Standby Mode Application Note

10.2.3 Application Curves

and recessive to dominant stated under lightly loaded conditions. Figure 24. Recessive to Dominant Propagation Figure 25. Dominant to Recessive Propagation

11 Power Supply Recommendations

good practice for some applications with noisier supplies to include 1 µF and 10 µF decoupling capacitor, as well.

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12 Layout

In order for your PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the PCB and system.

12.1 Layout Guidelines

• Pin 1 (RXD): The pin is an open drain output and requires and external pull-up resistor in the range of 1 kΩ and 10 kΩ to function properly. Note that the minimum value will depend on the VIO supply used. See IOL in electrical specifications. If the microprocessor paired with the transceiver does not have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the microprocessor.
• Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not used the pin should be pulled high to the regulated voltage supply of the microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit current on the digital lines in the case of an over voltage fault.
• Pin 3 (NC): Not Connected.
• Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the microcontroller. A series resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
• Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
• Pin 6 (LIN): This pin connects to the LIN bus. For slave applications a 220 pF capacitor to ground is implemented. For master applications an additional series resistor and blocking diode should be placed between the LIN pin and the VSUP pin. See Figure 23.
• Pin 7 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close to the device as possible.
• Pin 8 (NC): Not Connected. NOTE All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance.

12.2 Layout Example

Figure 26. Layout Example

SLLSF59 –JULY 2020–REVISED JULY 2020 www.ti.com Product Folder Links: TLIN2027-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following: LIN Standards:

• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer (EPL) specification 12V/24V
• SAEJ2602-1: LIN Network for Vehicle Applications
• LIN Specifications LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A EMC requirements:
• SAEJ2962-1: Communication Transceivers Qualification Requirements - LIN
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4: Direct RF power injection method
• IEC 61000-4-2
• IEC 61967-4
• CISPR25 Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL) conformance test specification
• SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

www.ti.com SLLSF59 –JULY 2020–REVISED JULY 2020 Product Folder Links: TLIN2027-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

13.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 2-Jul-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLIN2027DRBRQ1 PREVIEW SON DRB 8 3000 TBD Call TI Call TI -40 to 125 TLIN2027DRQ1 PREVIEW SOIC D 8 2500 TBD Call TI Call TI -40 to 125 TL027 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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