Logic IC

TLIN2021ADDFRQ1

Texas Instruments

TLIN2021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake APRIL 2022

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TLIN2021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake

1 Features

AEC-Q100 (Grade 1) Qualified for automotive

applications

Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO 17987–4 electrical physical layer (EPL) specification
Compliant to SAE J2602-1 LIN Network for Vehicle
Functional Safety-Capable – Documentation available to aid in functional safety system design
Support for 12-V and 24-V applications
Wide input operational voltage range: – VSUP range from 4.5 V to 45 V
LIN transmit data rate up to 20 kbps
LIN receive data rate up to 100 kbps
Operating modes: Normal, Standby and Sleep
Low-power mode wake-up support with source recognition: – Remote wake-up over the LIN bus – Local wake-up via the WAKE pin – Local wake-up via EN
Integrated 45-kΩ LIN pull-up resistor
Control of system-level power using the INH pin
Power-up/down glitch-free operation on LIN bus and RXD output
Protection features: ±60 V LIN bus fault tolerant, 58 V load dump support, undervoltage protection on VSUP, TXD dominant state time-out, thermal shutdown, unpowered node or ground disconnection fail-safe at system level
Junction temperature from -40°C to 150°C
Available in 8-pin SOIC, VSON with wettable flanks, and SOT23 packages

2 Applications

Body electronics and lighting
Automotive infotainment and cluster
Hybrid electric vehicles and power train systems
Industrial transportation

3 Description

The TLIN2021A-Q1 is a local interconnect network (LIN) physical layer transceiver. LIN is a low-speed universal asynchronous receiver transmitter (UART) communication protocol that supports automotive in- vehicle networking. The TLIN2021A-Q1 transmitter supports data rates up to 20 kbps. The transceiver controls the state of the LIN bus via the TXD pin and reports the state of the bus on its open-drain RXD output pin. The device has a current-limited wave-shaping driver to reduce electromagnetic emissions (EME). The TLIN2021A-Q1 is designed to support 12-V and 24-V applications with a wide input voltage operating range. The device supports low-power sleep mode, as well as wake-up from low-power mode through wake over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that can be present on a node through the device INH output pin. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TLIN2021A SOIC (D) (8)(2) 4.90 mm x 3.91 mm VSON (DRB) (8) 3.00 mm x 3.00 mm SOT23 (DDF) (8)(2) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Product Preview Voltage Regulator MCU LIN Controller or SCI/UART TLIN2021A VDD VDD VDD VSUP VDD EN RXD TXDGND I/O VIN LIN 1 k LIN Bus Commander Node Pullup 3 78 VBAT = 24 V 220 pF INH WAKE 3 kΩSW EN 33 kΩ Simplified Commander Node Schematic Voltage Regulator MCU LIN Controller or SCI/UART TLIN2021A VDD VDD VDD VSUP VDD EN RXD TXDGND I/O VIN LIN LIN Bus 3 78 VBAT = 24 V 220 pF INH WAKE 3 k SW EN 33 k Simplified Responder Node Schematic TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

13.2 Receiving Notification of Documentation Updates..33

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (January 2021) to Revision A (April 2022) Page

Changed the WAKE IIL parameter description from "Ligh-level input leakage current" to "Low-level input

5 Description (continued)

The TLIN2021A-Q1 integrates a resistor for LIN responder node applications, ESD protection, and fault protection which allow for a reduced amount of external components in the applications. The device prevents back-feed current through LIN to the supply input in case of a ground shift or supply voltage disconnection. The TLIN2021A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the fault condition is removed. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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6 Pin Configuration and Functions

Figure 6-1. D Package, 8-Pin (SOIC), and DDF 1RXD 8 INH 2EN 7 VSUP 3WAKE 6 LIN 4TXD 5 GND Not to scale Thermal Pad Figure 6-2. DRB Package, 8-Pin (VSON), Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. RXD 1 Digital LIN receive data output, open-drain EN 2 Digital Sleep mode control input, integrated pull-down WAKE 3 High Voltage Local wake-up input, high voltage TXD 4 Digital LIN transmit data input, integrated pulled down - active low after a local wake-up event GND 5 GND Ground connection LIN 6 Bus IO LIN bus input/output line VSUP 7 Supply High-voltage supply from the battery INH 8 High Voltage Inhibit output to control system voltage regulators and supplies, high voltage Thermal Pad — Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB) ground plane for thermal relief www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLIN2021A-Q1

7 Specification

7.1 Absolute Maximum Ratings

(1) (2) MIN MAX UNIT VSUP Supply voltage range (ISO 17987) –0.3 60 V VLIN LIN Bus input voltage (ISO 17987) –60 60 V VWAKE WAKE pin input voltage –0.3 60 V VINH INH pin output voltage –0.3 60 and VO ≤ VSUP+0.3 V VLOGIC_INPUT Logic input voltage –0.3 6 V VLOGIC_OUTPUT Logic output voltage –0.3 6 V IO Digital pin output current 8 mA IO(INH) Inhibit output current 4 mA IO(WAKE) WAKE output current due to ground shift (VWAKE ≤ VGND) – 0.3 V thus current out of the WAKE pin must be limited 3 mA TJ Junction Temp –55 165 °C Tstg Storage temperature -65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the ground terminal.

7.2 ESD Ratings

VESD Electrostatic discharge Human body model (HBM) classification level 3B: VSUP, INH, and WAKE with respect to ground ±8000 V Human body model (HBM) classification level 3B: LIN with respect to ground ±10000 Human body model (HBM) classification level 3A: all other pins, per AEC Q100-002(1) ±4000 Charged device model (CDM) classification level C5, per AEC Q100-011 All pins ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings - IEC Specification

VESD Electrostatic discharge LIN, VSUP, WAKE terminal to GND(1) IEC 62228-2 per ISO 10605 Contact discharge R = 330 Ω, C = 150 pF (IEC 61000-4-2) ±8000 V LIN terminal to GND(1) IEC 62228-2 per ISO 10605 Indirect contact discharge R = 330 Ω, C = 150 pF (IEC 61000-4-2) ±8000 TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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7.3 ESD Ratings - IEC Specification (continued)

injection LIN, VSUP, WAKE terminal to GND(1) IEC 62228-2 per IEC 62215-3

12 V electrical systems

-100 V IEC 62215-3

24 V electrical systems (3)

-450 IEC 62228-2 per IEC 62215-3 IEC 62228-2 per IEC 62215-3 -150 IEC 62215-3 -225 IEC 62228-2 per IEC 62215-3 Direct capacitor coupling LIN terminal to GND(2) SAE J2962-1 per ISO 7637-3 DCC - Slow transient pulse ±30 (1) Results given here are specific to the IEC 62228-2 Integrated circuits – EMC evaluation of transceivers – Part 2: LIN transceivers. Testing performed by OEM approved independent 3rd party, EMC report available upon request. (2) Results given here are specific to the SAE J2962-1 Communication Transceivers Qualification Requirements - LIN. Testing performed by OEM approved independent 3rd party, EMC report available upon request. (3) Verified during characterization

7.4 Thermal Information

THERMAL METRIC(1) TLIN2021A-Q1 UNITD (SOIC) DRB (VSON) DDF(SOT)

8 PINS 8 Pins 8 PINS

RθJA Junction-to-ambient thermal resistance 126.2 54.4 120.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 66.4 61.1 60.2 °C/W RθJB Junction-to-board thermal resistance 69.6 26.8 42.1 °C/W ΨJT Junction-to-top characterization parameter 18.7 2.3 2.4 °C/W ΨJB Junction-to-board characterization parameter 68.9 26.7 41.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance – 10.8 – °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Recommended Operating Conditions

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) MIN NOM MAX UNIT VSUP Supply Voltage 4.5 45 V VLIN LIN Bus input voltage 0 45 V VLOGIC Logic Pin Voltage 0 5.25 V TJ Operating virtual junction temperature range -40 150 °C TSDR Thermal shutdown rising 160 °C TSDF Thermal shutdown falling 150 °C TSD(HYS) Thermal shutdown hysteresis 10 °C www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLIN2021A-Q1

7.6 Power Supply Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Voltage and Current VSUP Operational supply voltage Device is operational beyond the LIN defined nominal supply voltage range See Figure 8-1 See Figure 8-2 4.5 45 V Nominal supply voltage Normal and standby modes(1) See Figure 8-1 See Figure 8-2 4.5 45 V Sleep mode 4.5 45 V ISUP Supply current Bus dominant Normal mode EN = VCC, RLIN ≥ 500 Ω, CLIN ≤ 10 nF, INH = WAKE = VSUP 1.8 7.5 mA Standby mode EN = 0 V, RLIN ≥ 500 Ω, CLIN ≤ 10 nF, INH =WAKE = VSUP 1 2.1 mA Supply current Bus recessive Normal mode EN = VCC, INH = WAKE = VSUP 400 850 µA Standby mode EN = 0 V, INH = WAKE = VSUP 20 55 µA Supply current Sleep mode

4.5 V < VSUP ≤ 27 V, TJ = 125℃

EN = 0 V, LIN = WAKE = VSUP, TXD and RXD floating 12 20 µA

27 V < VSUP ≤ 45 V, TJ = 125℃

EN = 0 V, LIN = WAKE = VSUP, TXD and RXD floating 26 µA UVSUPR Under voltage VSUP threshold Ramp up 4.15 4.45 V UVSUPF Under voltage VSUP threshold Ramp down 3.5 4 V UVHYS Delta hysteresis voltage for VSUP under voltage threshold 0.13 V (1) Normal mode ramp VSUP while LIN signal is a 10 kHz square wave with 50% duty cycle and 36 V swing.

7.7 Electrical Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RXD Output Terminal VOL Low-level voltage Based upon external pull-up to VCC (4) 0.6 V IOL Low-level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 5 µA TXD Input Terminal VIL Low-level input voltage 0.8 V VIH High-level input voltage 2 V ILKG Low-level input leakage current TXD = 0 V –5 5 µA ITXD(WAKE) Local wake-up source recognition TXD Standby mode after a local wake-up event VLIN = VSUP, WAKE = 0 V or VSUP, TXD = 1 V 1.3 8 mA RTXD Internal pull-down resistor value 125 350 800 kΩ EN Input Terminal VIL Low-level input voltage –0.3 0.8 V VIH High-level input voltage 2 5.25 V VHYS Hysteresis voltage By design and characterization 30 500 mV IIL Low-level input current EN = 0 V –5 5 µA REN Internal pull-down resistor 125 350 800 kΩ LIN Terminal (Referenced to VSUP) TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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7.7 Electrical Characteristics (continued)

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH LIN recessive high-level output voltage(3) TXD = VCC, IO = 0 mA 7 V ≤ VSUP ≤ 45 V 0.85 VSUP VOH LIN recessive high-level output voltage(1) (2) TXD = VCC, IO = 0 mA 7 V ≤ VSUP ≤ 18 V 0.8 VSUP VOH LIN recessive high-level output voltage(3) TXD = VCC, IO = 0 mA

4.5 V ≤ VSUP ≤ 7 V 3 V

VOL LIN dominant low-level output voltage(3) TXD = 0 V 7 V ≤ VSUP ≤ 45 V 0.2 VSUP VOL LIN dominant low-level output voltage(1) (2) TXD = 0 V 7 V ≤ VSUP ≤ 18 V 0.2 VSUP VOL LIN dominant low-level output voltage(3) TXD = 0 V 4.5 V ≤ VSUP ≤ 7 V 1.2 V VBUSdom Low-level input voltage(3) LIN dominant (including LIN dominant for wake up) See Figure 8-3 See Figure 8-4

0.4 VSUP

VBUSrec High-level input voltage(3) LIN recessive See Figure 8-3 See Figure 8-4

0.6 VSUP

VIH LIN recessive high-level input voltage(1) (2) 7 V ≤ VSUP ≤ 18 V 0.47 0.6 VSUP VIL LIN dominant low-level input voltge(1) (2) 7 V ≤ VSUP ≤ 18 V 0.4 0.53 VSUP VSUP_NON_OP VSUP where impact of recessive LIN bus < 5%(3) TXD & RXD open 4.5 V ≤ VLIN ≤ 60 V –0.3 60 V VBUS_CNT Receiver center threshold(3) VBUS_CNT = (VBUSrec + VBUSdom)/2 See Figure 8-3 See Figure 8-4 0.475 0.5 0.525 VSUP VHYS Hysteresis voltage (ISO 17987) VHYS = VBUSrec - VBUSdom See Figure 8-3 See Figure 8-4

0.175 VSUP

Hysteresis voltage (SAE J2602) VHYS = VIH - VIL See Figure 8-3 See Figure 8-4 0.07 0.175 VSUP VSERIAL_DIODE Serial diode LIN termination pull-up path ISERIAL_DIODE = 10 µA 0.4 0.7 1.0 V IBUS(LIM) Limiting current TXD = 0 V, VLIN = 36 V, RMeas = 480 Ω VSUP = 36 V, VBUSdom < 10.224 V 75 120 300 mA IBUS_PAS_dom Receiver leakage current, dominant Driver off/recessive, LIN = 0 V VSUP = 24 V See Figure 8-6 –1 mA IBUS_PAS_rec1 Receiver leakage current, recessive Driver off/recessive, LIN ≥ VSUP

4.5 V ≤ VSUP ≤ 45 V

20 µA IBUS_PAS_rec2 Receiver leakage current, recessive Driver off/recessive, LIN = VSUP See Figure 8-7 –5 5 µA IBUS_NO_GND Leakage current, loss of ground GNDDevice = VSUP = 24 V RMeas = 1 kΩ

0 V < VLIN < 36 V

–1.5 1.5 mA Ileak gnd(dom) Leakage current, loss of ground(5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = dominant –1 1 mA Ileak gnd(rec) Leakage current, loss of ground(5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = recessive –100 100 µA www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLIN2021A-Q1

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IBUS_NO_BAT Leakage current, loss of supply VSUP = GND

0 V ≤ VLIN ≤ 36 V

5 µA IRSLEEP Pull-up current source to VSUP sleep mode VSUP = 27 V, LIN = GND –20 –1.5 µA RPU Pull-up resistor to VSUP Normal and standby modes 20 45 60 kΩ CLIN Capacitance of the LIN pin VSUP = 14 V 25 pF INH Output Terminal ΔVH High level voltage drop INH with respect to VSUP IINH = - 0.5 mA 0.5 1 V ILKG(INH) Leakage current sleep mode INH = 0 V –0.5 0.5 µA WAKE Input Terminal VIH High-level input voltage Standby and sleep mode VSUP – 1.8 V VIL Low-level input voltage Standby and sleep mode VSUP – 3.85 V IIH High-level input leakage current WAKE = VSUP - 1 V –25 –12.5 µA IIL Low-level input leakage current WAKE = 1 V 15 25 µA tWAKE WAKE hold time Wake up time from sleep mode 5 50 µs Duty Cycle Characteristics D112V Duty cycle 1(3) ISO 17987 Param 27 THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.396 D112V Duty cycle 1(3) (6) THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP VSUP = 4.5 V to 7 V, tBIT = 50 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.396 D112V Duty cycle 1(1) (2) (6) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.396 D212V Duty cycle 2(3) ISO 17987 Param 28 THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.581 D212V Duty cycle 2(3) (6) THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 4.5 V to 7 V, tBIT = 50 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.581 D212V Duty cycle 2(1) (2) (6) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.581 D312V Duty cycle 3(3) ISO 17987 Param 29 THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.417 D312V Duty cycle 3(3) (6) THREC(MAX) = 0.665 x VSUP THDOM(MAX) = 0.499 x VSUP VSUP = 4.5 V to 7 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.417 TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D312V Duty cycle 3(1) (2) (6) THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.417 D412V Duty cycle 4(3) ISO 17987 Param 30 THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.59 D412V Duty cycle 4(3) (6) THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP VSUP = 4.5 V to 7 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.59 D412V Duty cycle 4(1) (2) (6) THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.59 D124V Duty cycle 1 ISO 17987 Param 72 THREC(MAX) = 0.710 x VSUP, THDOM(MAX) = 0.554 x VSUP, VSUP = 15 V to 36 V, tBIT = 50 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.330 D224V Duty cycle 2 ISO 17987 Param 73 THREC(MIN) = 0.446 x VSUP, THDOM(MIN) = 0.302 x VSUP, VSUP = 15.6 V to 36 V, tBIT = 50 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.642 D324V Duty cycle 3 ISO 17987 Param 74 THREC(MAX) = 0.744 x VSUP THDOM(MAX) = 0.581 x VSUP VSUP = 7 V to 36 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.386 D324V Duty cycle 3 (6) THREC(MAX) = 0.645 x VSUP THDOM(MAX) = 0.581 x VSUP VSUP = 4.5 V to 7 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.386 D424V Duty cycle 2 (6) ISO 17987 Param 75 THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4.5 V to 36 V, tBIT = 96 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-8 and Figure 8-9 0.591 D1LB Duty cycle 1 at low battery(1) (2) (6) THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 52 µs 0.396 D2LB Duty cycle 2 at low battery(1) (2) (6) THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 52 µs 0.581 D3LB Duty cycle 3 at low battery(1) (2) (6) THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 µs 0.396 D4LB Duty cycle 4 at low battery(1) (2) (6) THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 96 µs 0.581 Tr-d max_D1 Transmitter propagation delay timings for the duty cycle(1) (2) (6) Recessive to dominant THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP

7 V ≤ VSUP ≤ 18 V, tBIT = 52 µs

tREC(MAX)_D1 - tDOM(MIN)_D1 10.8 µs Td-r max_D2 Transmitter propagation delay timings for the duty cycle(1) (2) (6) Dominant to recessive THREC(MAX) = 0.422 x VSUP, THDOM(MAX) = 0.284 x VSUP tDOM(MAX)_D2 - tREC(MIN)_D2 8.4 µs www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLIN2021A-Q1

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Tr-d max_D3 Transmitter propagation delay timings for the duty cycle(1) (2) (6) Recessive to dominant THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP

7 V ≤ VSUP ≤ 18 V, tBIT = 96 µs

tREC(MAX)_D3 - tDOM(MIN)_D3 15.9 µs Td-r max_D4 Transmitter propagation delay timings for the duty cycle(1) (2) (6) Dominant to recessive THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP tDOM(MAX)_D4 - tREC(MIN)_D4 17.28 µs Tr-d max_low Low battery transmitter propagation delay timings for the duty cycle(1) (2) (6) Recessive to dominant THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP

5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 µs

tREC(MAX)_low - tDOM(MIN)_low 10.8 µs Td-r max_low Low battery transmitter propagation delay timings for the duty cycle(1) (2) (6) Dominant to recessive THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP

6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 µs

tDOM(MAX)_low - tREC(MIN)_low 8.4 µs (1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ (2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω (3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω. (4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage. (5) Ileak gnd = (VBAT - VLIN)/RLoad (6) Specified by design

7.8 AC Switching Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Device Switching Characteristics trx_pdr Receiver rising propagation delay time ISO 17987 Param 31 4.5 V ≤ VSUP < 5.5 V, RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 8-10 and Figure 8-11 6 µs trx_pdf Receiver falling propagation delay time ISO 17987 Param 31 6 µs trx_pdr Receiver rising propagation delay time ISO 17987 Param 31 5.5 V ≤ VSUP, RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 8-10 and Figure 8-11 5 µs trx_pdf Receiver falling propagation delay time ISO 17987 Param 31 5 µs trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time ISO 17987 Param 32 Rising edge with respect to falling edge trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF See Figure 8-10 and Figure 8-11 –2 2 µs tLINBUS Minimum dominant time on LIN bus for wake-up See Figure 8-14, Figure 9-2 and Figure 9-3 25 65 150 µs tCLEAR Time to clear false wake-up prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) See Figure 9-3 8 25 50 µs tMODE_CHANGE Mode change delay time Time to change from normal mode to sleep mode through EN pin See Figure 8-12 2 15 µs tNOMINT Normal mode initialization time(1) Time for normal mode to initialize and data on RXD pin to be valid, includes tMODE_CHANGE for standby to normal mode. See Figure 8-12 45 µs tPWR Power-up time Time it takes for valid data on RXD upon power-up 1.5 ms tTXD_DTO Dominant state time out 20 50 80 ms (1) The transition time from sleep mode to normal mode includes both tMODE_CHANGE and tNOMINT. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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7.9 Typical Curves

Supply Voltage (V) VOH (V) 0 5 10 15 20 25 30 35 40 D001 -55°C 25°C 125°C 150°C Figure 7-1. VOH vs VSUP vs Temperature Supply Voltage (V) VOL (V) 0 5 10 15 20 25 30 35 40 0.6 0.8 1.2 1.4 1.6 1.8 D002 -55°C 25°C 125°C 150°C Figure 7-2. VOL vs VSUP vs Temperature Supply Voltage (V) ISUP (mA) 0 5 10 15 20 25 30 35 40 0.5 1.5 2.5 D003 -55°C 25°C 125°C 150°C Figure 7-3. ISUP (DOM) vs VSUP vs Temperature Supply Voltage (V) ISUP (PA) 0 5 10 15 20 25 30 35 40 150 200 250 300 350 400 450 500 D004 -55°C 25°C 125°C 150°C Figure 7-4. ISUP (REC) vs VSUP vs Temperature Supply Voltage (V) ISUP (mA) 0 5 10 15 20 25 30 35 40 0.2 0.4 0.6 0.8 1.2 D005 -55°C 25°C 125°C 150°C Figure 7-5. ISUP(STBY_DOM) vs VSUP vs Temperature Supply Voltage (V) ISUP (mA) 0 5 10 15 20 25 30 35 40 0.2 0.4 0.6 0.8 1.2 D005 -55°C 25°C 125°C 150°C Figure 7-6. ISUP(STBY_REC) vs VSUP vs Temperature www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLIN2021A-Q1

7.9 Typical Curves (continued)

Supply Voltage (V) ISUP (PA) 0 5 10 15 20 25 30 35 40 D007 -55°C 25°C 125°C 150°C Figure 7-7. ISUP(SLP) vs VSUP vs Temperature TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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8 Parameter Measurement Information

O-scope: DMM Power Supply Resolution: 10mV/ 1mA Accuracy: 0.2% Pulse Generator tR/tF Square Wave: < 20 ns tR/tF Triangle Wave: < 40ns Frequency: 20 ppm Jitter: < 25 ns 5 V RXD INH LIN GND VSUP Copyright © 2019, Texas Instruments Incorporated EN WAKE TXD Figure 8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10 Trigger Point Delta t = + 5 µs (tBIT = 50 µs) 2 * tBIT = 100 µs (20 kBaud) RX Copyright © 2019, Texas Instruments Incorporated Figure 8-2. RX Response: Operating Voltage Range Period T = 1/f Amplitude (signal range) Frequency: f = 20 Hz Symmetry: 50% LIN Bus Input Copyright © 2019, Texas Instruments Incorporated A Figure 8-3. LIN Bus Input Signal www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TLIN2021A-Q1

O-scope: DMM Power Supply Resolution: 10mV/ 1mA Accuracy: 0.2% Pulse Generator tR/tF Square Wave: < 20 ns tR/tF Triangle Wave: < 40ns Frequency: 20 ppm Jitter: < 25 ns 5 V RXD EN INH LIN GND VSUP Copyright © 2019, Texas Instruments Incorporated WAKE TXD Figure 8-4. LIN Receiver Test with RX access Param 17, 18, 19, 20 Measurement Tools O-scope: DMM Power Supply 1 Resolution: 10mV/ 1mA Accuracy: 0.2% VPS1 5 V EN INH LIN GND VSUP Power Supply 2 Resolution: 10mV/ 1mA Accuracy: 0.2% VPS2 D RBUS Copyright © 2019, Texas Instruments Incorporated RXD WAKE TXD Figure 8-5. VSUP_NON_OP Param 11 TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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Square Wave: < 20 ns tR/tF Triangle Wave: < 40ns Frequency: 20 ppm Jitter: < 25 ns 5 V TXD EN INH LIN GND VSUP RMEAS Power Supply 1 Resolution: 10mV/ 1mA Accuracy: 0.2% VPS1 Power Supply 2 Resolution: 10mV/ 1mA Accuracy: 0.2% VPS2 Measurement Tools O-scope: DMM Copyright © 2019, Texas Instruments Incorporated WAKE RXD Figure 8-8. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30 TXD (Input) D = 50%TBIT THREC(MAX) THREC(MIN) THDOM(MAX) THDOM(MIN) tBUS_DOM(MAX) tBUS_REC(MIN) tBUS_DOM(MIN) tBUS_REC(MAX) LIN Bus Signal VSUP Thresholds RX Node 1 Thresholds RX Node 2 RXD: Node 1 D1 (20 kbps) D3 (10.4 kbps) RXD: Node 2 D2 (20 kbps) D4 (10.4 kbps) D112: 0.744 * VSUP D312: 0.778 * VSUP D112: 0.581 * VSUP D312: 0.616 * VSUP D212: 0.422 * VSUP D412: 0.389 * VSUP D212: 0.284 * VSUP D412: 0.251 * VSUP D124: 0.710 * VSUP D324: 0.744 * VSUP D124: 0.554 * VSUP D324: 0.581 * VSUP D224: 0.446 * VSUP D424: 0.422 * VSUP D224: 0.302 * VSUP D424: 0.284 * VSUP Figure 8-9. Definition of Bus Timing Parameters TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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tMODE_CHANGE tMODE_CHANGE Transition Sleep Floating Transition EN MODE RXD Wake Request RXD = Low Wake Event Normal Normal Mirrors Bus Mirrors Bus Indeterminate Ignore Indeterminate Ignore tNOMINT Figure 8-12. Mode Transitions VSUP EN RXD LIN MODE TXD Weak Internal Pulldown Floating Sleep Weak Internal Pulldown Normal Copyright © 2019, Texas Instruments Incorporated Figure 8-13. Wake-up Through EN TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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TXD Weak Internal Pull-down Floating Sleep Normal Standby t < tLINBUS tLINBUS 0.4 x VSUP 0.4 x VSUP 0.6 x VSUP0.6 x VSUP Copyright © 2019, Texas Instruments Incorporated Figure 8-14. Wake-up through LIN www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLIN2021A-Q1

9 Detailed Description

9.1 Overview

The TLIN2021A-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602-1, SAE J2602-2, ISO 17987–4, and ISO 17987–7 standards. LIN is a low-speed universal asynchronous receiver transmitter (UART) communication protocol focused on automotive in-vehicle networking. The device transmitter supports data rates from 2.4-kbps to 20-kbps and the receiver supports data rates up to 100-kbps for end-of-line programming. The device controls the state of the LIN bus through the TXD pin and reports the state of the bus through its open-drain RXD output pin. The LIN protocol data stream on the TXD input is converted by the device into a LIN bus signal using an optimized electromagnetic emissions current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data stream to logic-level signals that are sent to the microcontroller through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the transceivers internal pull-up resistor (45-k Ω) and a series diode. No external pull-up components are required for responder node applications. Commander node applications require an external pull-up resistor (1-kΩ) as well as a series diode per the LIN specification. The device is designed to support 12-V and 24-V applications with a wide input voltage operating range and also supports low-power sleep mode. The device supports wake-up from low-power mode through wake over LIN, the WAKE pin, or the EN pin. The device allows for system-level reductions in battery current consumption by selectively enabling the various power supplies that may be present on a node through the INH output pin. The TLIN2021A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required external components in the applications. In the event of a ground shift or supply voltage disconnection, the device prevents back-feed current through LIN to the supply input. The TLIN2021A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground protection. In the event of a fault condition, the transmitter is immediately switched off and remains off until the fault condition is removed. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 LIN

This high voltage input/output pin is the single-wire LIN bus transmitter and receiver. The LIN pin can survive transient voltages up to 60-V. Reverse currents from the LIN to supply (V SUP) are minimized with blocking diodes, even in the event of a ground shift or loss of supply (VSUP).

9.3.1.1 LIN Transmitter Characteristics

The LIN transmitter has thresholds and AC switching parameters according to the LIN specification. The transmitter is a low-side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to V SUP, so no external pull-up components are required for LIN responder node applications. An external pull-up resistor and series diode to V SUP must be added when the device is used in a commander node application per the LIN specification.

9.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are proportional to the device supply pin in accordance to the LIN specification. The receiver is capable of receiving higher data rates, > 100 kbps, than supported by LIN or SAEJ2602 specifications. This allows the TLIN2021A-Q1 to be used for high-speed downloads at the end-of-line production or other applications. The actual data rate achievable depends on system time constants (bus capacitance and pull-up resistance) and driver characteristics used in the system. www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLIN2021A-Q1

9.3.1.2.1 Termination

There is an internal pull-up resistor with a serial diode structure to V SUP, so no external pull-up components are required for the LIN responder node applications. An external pull-up resistor (1-k Ω) and a series diode to V SUP must be added when the device is used for commander node applications as per the LIN specification. Figure 9-1 shows a commander node configuration and how the voltage levels are defined Simplified Transceiver Filter VSUP LIN RXD TXD VSUP/2 350 kQ 45 kQ Receiver Transmitter with slope control GND 1 kQ VSUP LIN Bus VLIN_Dominant VLIN_Recessive VBattery VSUP t VLIN_Bus Voltage drop across the diodes in the pull-up path Copyright © 2019, Texas Instruments Incorporated Figure 9-1. Commander Node Configuration with Voltage Levels

9.3.2 TXD

TXD is the interface to the MCU LIN protocol controller or SCI and UART that is used to control the state of the LIN output. When TXD is low the LIN output is dominant (near ground) and when TXD is high the LIN output is recessive (near VSUP), see Figure 9-1. The TXD input structure is compatible with 3.3-V and 5-V microcontrollers and integrates a weak pull-down resistor. The LIN bus is protected from being stuck dominant through a system failure driving TXD low through the dominant state time-out timer. When a change of state on the WAKE pin initiates a local wake-up event, the TXD pin is pulled hard to ground indicating a local wake-up event. The hard pull to ground is released upon the rising edge on the EN pin. If an external pull-up resistor is added to the TXD pin to the microcontroller's IO voltage then TXD is pulled high to indicate a remote wake-up event.

9.3.3 RXD

RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN bus voltage. LIN recessive (near V SUP) is represented by a high level on the RXD and LIN dominant (near ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to be used with 3.3-V and 5-V microcontrollers. If the microcontroller's RXD pin does not have an integrated pull-up, an external pull-up resistor to the microcontroller's IO supply voltage is required. In standby mode, the RXD pin is driven low to indicate a wake-up request.

9.3.4 VSUP

VSUP is the power supply pin. V SUP is connected to the battery through an external reverse-blocking diode, see Figure 9-1. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).

9.3.5 GND

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift does not reduce the V SUP below the minimum operating voltage. If there is a loss of ground at the ECU level, TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied). 9.3.6 EN EN controls the operational modes of the device. When EN is high the device is in normal operating mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep mode and there are no transmission paths available. The device can enter normal mode only after wake-up. EN has an internal pull-down resistor to ensure the device remains in low power mode even if EN floats.

9.3.7 WAKE

The WAKE pin is a high-voltage input used for the local wake-up (LWU) function. This function is explained further in Section 9.4.4.1 section. The pin is defaulted to bidirectional edge trigger, meaning it recognizes a local wake-up (LWU) on a rising or falling edge of WAKE pin transition.

9.3.8 INH

The TLIN2021A-Q1 inhibit, INH, output pin can be used to control the enable of system power-management devices allowing for a significant reduction in battery quiescent current consumption while the application is in sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high, the terminal shows VSUP minus a diode voltage drop. In the high impedance state the output is left floating. The INH pin is high in the normal and standby modes and is low when in sleep mode. A 100 k Ω load can be added to the INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin low when left floating. The INH terminal should be considered a high-voltage logic terminal and not a power output. Thus should be used to drive the EN terminal of the systems power-management device and not used as a switch for the power-management supply itself. This terminal is not reverse battery protected and thus should not be connected outside the system module.

9.3.9 Local Faults

The TLIN2021A-Q1 has several protection features that are described as follows.

9.3.10 TXD Dominant Time-Out (DTO)

While the LIN driver is in active mode a TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the time-out period t TXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before the time-out constant of the circuit, t TXD_DTO, expires the LIN driver is disabled releasing the bus line to the recessive level. This keeps the bus free for communication between other nodes on the network. The LIN driver is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time-out. During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains on, and the LIN receiver and RXD terminal remain active reflecting the LIN bus data. The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. If EN pin is high at power-up, the TLIN2021A-Q1 enters normal mode. With the internal TXD connected low, the DTO timer starts. To avoid a t TXD_DTO fault, a recessive signal should be put onto the TXD pin before the t TXD_DTO timer expires, or the device should be into sleep mode by connecting EN pin low.

9.3.11 Bus Stuck Dominant System Fault: False Wake-Up Lockout

The TLIN2021A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus clears the bus stuck dominant fault, preventing excessive current use, see Figure 9-2 and Figure 9-3. www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLIN2021A-Q1

< tLINBUS < tLINBUS tLINBUS RXD Figure 9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up EN LIN Bus < tCLEAR tLINBUS tLINBUS tLINBUS tCLEAR RXD Figure 9-3. Bus Fault: Entering Sleep Mode With Bus Stuck Dominant Fault, Clearing, and Wake-up

9.3.12 Thermal Shutdown

The TLIN2021A-Q1 transmitter is protected by limiting the current. If the junction temperature, T J, of the device exceeds the thermal shutdown threshold, TJ > TSDR, the device puts the LIN transmitter into the recessive state. Once the over temperature fault condition has been removed and the junction temperature has cooled beyond the hysteresis temperature, the transmitter is re-enabled. During this fault, the transceiver remains in normal mode, the integrated LIN bus pull-up termination remains on, the LIN receiver and RXD terminal remain active reflecting the LIN bus data.

9.3.13 Under Voltage on VSUP

The device contains a power on reset circuit to avoid false bus messages during under voltage conditions when VSUP is less than UVSUP.

9.3.14 Unpowered Device

In automotive applications, some LIN nodes in a system can be unpowered, ignition supplied, while others in the network remains powered by the battery. The device has extremely low unpowered leakage current from the bus so an unpowered node does not affect the network or load it down.

9.4 Device Functional Modes

The TLIN2021A-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections describe these modes and how the device transitions between the different modes. Figure 9-4 graphically shows the relationship while Table 9-1 shows the state of pins. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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Table 9-1. Operating Modes MODE EN TXD RXD INH LIN BUS TERMINATION TRANSMITTE R COMMENT Sleep Low Weak pull-down Floating Floating Weak current pull-up Off Standby Low Weak pull-down if LIN bus wake- up; Strong pull-down if a local wake-up event (WAKE pin) Low High 45-kΩ Off Wake-up event detected, waiting on MCU to set EN Normal High High: recessive state Low: dominant state LIN Bus Data High 45-kΩ On LIN transmission up to 20 kbps Unpowered System VSUP < UVSUP Standby Mode Driver: Off RXD: Low TXD: weak pull-down for LIN bus wake Hard pull-down for WAKE pin wake INH: On LIN termination: 45 k Sleep Mode Driver: Off RXD: Floating TXD: Weak pull-down INH: Off LIN termination: Weak pull-up Normal Mode Driver: On RXD: LIN Bus Data TXD: High for recessive Low for dominant INH: On LIN termination: 45 k VSUP > UVSUP EN = High VSUP > UVSUP EN = Low VSUP < UVSUP EN = High VSUP < UVSUP VSUP < UVSUP EN = High EN = Low LIN bus wake up or WAKE pin wake up Figure 9-4. Operating State Diagram

9.4.1 Normal Mode

The EN pin controls the mode of the device. If the EN pin is high at power-up the device powers up in normal mode, if the EN is low at power-up the device powers up in standby mode. In normal mode the receiver and transmitter fully operational. The LIN transmitter transmits data from the LIN controller to the LIN bus up to the LIN specified maximum data rate of 20-kbps. The LIN receiver detects the data stream on the LIN bus up to data rates of 100-kbps and outputs the data on RXD output for the LIN controller. Upon an EN pin transition from low to high the TLIN2021A-Q1 transitions from sleep mode to normal mode in t ≥ tNOMINT.

9.4.2 Sleep Mode

Sleep mode is the lowest power mode of the TLIN2021A-Q1 and is only entered from normal mode when the EN pin transitions from high to low for t > t MODE_CHANGE. In sleep mode, the LIN driver and receiver are switched off, the LIN bus is weakly pulled up, and the transceiver cannot send or receive data. The INH pin is switched to a floating output in sleep mode causing any system power elements controlled by the INH pin to be switched off thus reducing the system power consumption. While the device is in sleep mode, the following conditions exist: www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLIN2021A-Q1

The LIN bus driver is disabled and the internal LIN bus termination is switched off to minimize power loss if LIN is short circuited to ground.
A weak current pull-up is active to prevent false wake-up events in case an external connection to the LIN bus is lost.
The normal receiver is disabled.
EN input, WAKE pin and LIN wake-up receiver are active. The TLIN2021A-Q1 supports three methods for wake-up from sleep mode:
Wake-up over the LIN bus via the LIN wake-up receiver.
Local wake-up via the WAKE pin.
Local wake-up via the EN pin. The EN pin must be set high for t > tNOMINT in order for the device to wake-up.

9.4.3 Standby Mode

Standby mode is entered whenever a wake-up event occurs through LIN bus or the WAKE pin while the device is in sleep mode. In standby mode, the LIN bus responder termination circuit, 45-k Ω, is on. When a wake-up event occurs and the TLIN2021A-Q1 enters standby mode the RXD pin is driven low signaling the wake-up event to the LIN controller. The TLIN2021A-Q1 exits standby mode and transitions to normal mode when the EN pin is set high for longer than tMODE_CHANGE where the normal LIN transmitter and receiver are fully operational and bi-directional communication is possible.

9.4.4 Wake-Up Events

There are three ways to wake-up the TLIN2021A-Q1 from sleep mode:

Remote wake-up initiated by the falling edge of a recessive-to-dominant state transition on the LIN bus where the dominant state is held longer than tLINBUS filter time. After the tLINBUS filter time has been met a rising edge on the LIN bus going from dominant-to-recessive initiates a remote wake-up event. The pattern and tLINBUS filter time used for the LIN wake-up prevents noise and bus stuck dominant faults from causing false wake requests.
A local wake-up event due to the EN pin being set high for t > tMODE_CHANGE.
A local wake-up event due to a change in voltage level on the WAKE pin for t > tWAKE

9.4.4.1 Local Wake-Up (LWU) via WAKE Input Terminal

The WAKE terminal is a bi-directional high-voltage input which can be used for local wake-up (LWU) requests via a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low transition since it has bi-directional input thresholds. The WAKE pin could be used with a switch to V SUP or to ground. If the terminal is unused it should be pulled to V SUP or ground to avoid unwanted parasitic wake-up events. When a LWU event takes place the TXD pin is pulled hard to GND letting the LIN controller know that the wake-up event was due to the WAKE pin and not a wake over LIN event. The LWU circuitry is active in standby mode and sleep mode. If a valid LWU event occurs in standby mode, the device remains in standby mode and drive the RXD output low. If a valid LWU event occurs in sleep mode, the device transitions to standby mode and drives the RXD output low. The LWU circuitry is not active in normal mode. To minimize system-level current consumption, the internal bias voltages of the terminal follows the state on the terminal with a delay of t WAKE(MIN). A constant high level on WAKE has an internal pull-up to V SUP, and a constant low level on WAKE has an internal pull-down to GND. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

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WWWAKE No Wake UP Wake Wake Threshold Not Crossed Local Wake Request WWWAKE Wake UP Mode Sleep Mode Standby Mode RXD TXD Pull-down Latched Low Figure 9-5. Local Wake-Up – Rising Edge INH WWWAKE No Wake UP Wake Wake Threshold Not Crossed Mode Sleep Mode Standby Mode Local Wake Request RXD WWWAKE Wake UP Copyright © 2019, Texas Instruments Incorporated TXD Pull-down Latched Low Figure 9-6. Local Wake-Up – Falling Edge

9.4.4.2 Wake-Up Request (RXD)

When the TLIN2021A-Q1 encounters a wake-up event from the WAKE pin or the LIN bus, the RXD output is driven low until EN is asserted high, the device enters normal mode. Once the device enters normal mode, the wake-up event is cleared, and the RXD output is released. The RXD output is fully operational and reflects the receiver output from the LIN bus. www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TLIN2021A-Q1

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

The TLIN2021A-Q1 can be used in both a responder node application and a commander node application in a LIN network.

10.2 Typical Application

The device integrates a 45-kΩ pull-up resistor and series diode for responder node applications. For commander node applications, an external 1-k Ω pull-up resistor with series blocking diode can be used. Figure 10-1 shows the device being used in both commander node and responder node applications. TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

Product Folder Links: TLIN2021A-Q1

SCI/UART(1) TLIN2021A VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pull-up(2) VSUP MCU GND I/O VREG LIN 1 k LIN Bus Commander Node Commander Node Pullup(3) 3 78 VBAT = 24 V LIN Controller Or SCI/UART(1) TLIN2021A VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pull-up(2) VSUP MCU GND I/O VREG LIN Responder Node 220 pF 220 pF (1) If RXD on MCU or LIN responder node has internal pull-up; no external pull-up resistor is needed. (2) If RXD on MCU or LIN responder node does not have an internal pull-up requires external pull-up resistor. (3) Commander node applications require and external 1 kpull-up resistor and serial diode. (4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and 10 µF (4) (4) INH WAKE GND 3 k SW 33 k INH WAKE GND 3 k SW 33 k EN EN Figure 10-1. Typical LIN Bus www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TLIN2021A-Q1

10.2.1 Design Requirements

The RXD output structure is an open-drain output stage which allows the TLIN2021A-Q1 to be used with 3.3-V and 5-V controllers. If the RXD pin of the controller does not have an integrated pull-up, an external pull-up resistor to the controller's IO voltage is required. The external pull-up resistor value should be between 1-k Ω to 10-kΩ. The V SUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the VSUP supply pin. The system should include additional decoupling on the VSUP line as needed per the application requirements.

10.2.2 Detailed Design Procedures

10.2.2.1 Normal Mode Application Note

When using the TLIN2021A-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period between states as the receivers are switched. The application software should not look for an edge on the RXD pin indicating a wake-up request until tMODE_CHANGE has been met. This is shown in Figure 8-12

10.2.2.2 TXD Dominant State Time-Out Application Note

The maximum dominant TXD time allowed by the TXD dominant state time-out limits the minimum possible data rate of the device. The LIN protocol has different constraints for commander node and responder node applications thus there are different maximum consecutive dominant bits for each application case thus different minimum data rates.

10.2.2.3 Standby Mode Application Note

If the TLIN2021A-Q1 detects an under voltage on V SUP the RXD pin transitions low signaling to the controller that the TLIN2021A-Q1 is in standby mode. The transceiver should be returned to sleep mode for the lowest power state.

10.2.3 Application Curves

Figure 10-2 and Figure 10-3 show the propagation delay from the TXD pin to the LIN pin for the dominant to recessive and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1 kΩ) and 680 pF bus capacitance. Figure 10-2. Dominant To Recessive Propagation Delay Figure 10-3. Recessive to Dominant Propagation Delay TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

Product Folder Links: TLIN2021A-Q1

11 Power Supply Recommendations

The TLIN2021A-Q1 was designed to operate directly from a car battery, or any other DC supply ranging from 4.5-V to 45-V. The VSUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the VSUP supply pin. The system should include additional decoupling on the VSUP line as needed per the application requirements. Device has been designed and tested to support supply ramp rates equal to or slower than 0.5 V/µs.

12 Layout

For the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz, high-frequency layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the PCB and system.

12.1 Layout Guidelines

Pin 1(RXD): The RXD pin is an open-drain output and requires and external pull-up resistor in the range of 1-kΩ and 10-kΩ to function properly. If the controller paired with the transceiver does not have an integrated pull-up, an external resistor should be placed between RXD and the supply voltage for the controller.
Pin 2 (EN): EN is an input pin that is used to place the device in low-power sleep mode. If this feature is not used, the pin should be connected to the supply voltage for the controller through a series resistor using a pull-up value between 1-kΩ and 10-kΩ. Additionally, a series resistor may be placed on the pin to limit current on the digital lines in the case of an over voltage fault.
Pin 3 (WAKE): SW1 is oriented in a low-side configuration which is used to implement a local WAKE event. The series resistor R5 is needed for protection against over current conditions as it limits the current into the WAKE pin when the ECU has lost its ground connection. The pull-up resistor R4 is required to provide sufficient current during stimulation of a WAKE event. In this layout example R4 is set to 3-kΩ and R5 is set to 33-kΩ.
Pin 4 (TXD): The TXD pin is the transmit input signal to the device from the controller. A series resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to help filter noise.
Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
Pin 6 (LIN): The LIN pin connects to the TLIN2021A-Q1 to the LIN bus. For responder node applications a 220 pF capacitor to ground is implemented. For commander node applications an additional series resistor and blocking diode should be placed between the LIN pin and the VSUP pin, see Typical LIN Bus.
Pin 7 (VSUP): This is the supply pin for the device. A 100-nF capacitor should be placed close to the VSUP supply pin for local power supply decoupling.
Pin 8 (INH):The INH pin is used for system power-management. A 100-kΩ load can be added to the INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin low when left floating. Note All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance. www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TLIN2021A-Q1

12.2 Layout Example

Figure 12-1. Layout Example TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 www.ti.com

Product Folder Links: TLIN2021A-Q1

13 Device and Documentation Support

13.1 Documentation Support

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TLIN2021A-Q1 SLLSFK7A – MARCH 2021 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TLIN2021A-Q1

www.ti.com 10-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLIN2021ADDFRQ1 ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2JJF Samples TLIN2021ADRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL021A Samples TLIN2021ADRQ1 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T2021A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 10-Jul-2024 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLIN2021ADRBRQ1 SON DRB 8 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 2.95

2.65 TYP

1.1 MAX 6X 0.65 8X 0.38 0.22 1.95 0.20

0.08 TYP

0 - 8 0.1 0.0 0.25 GAGE PLANE 0.6 0.3 A 2.95 2.85 NOTE 3 B 1.65 1.55 4222047/D 04/2024 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 4.000 ALTERNATIVE PACKAGE SINGULATION VIEW

www.ti.com EXAMPLE BOARD LAYOUT (2.6)

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 8X (1.05) 8X (0.45) 6X (0.65) (R0.05) TYP 4222047/D 04/2024 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X 4 5 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) 6X (0.65) 8X (0.45) 8X (1.05) (R0.05) TYP 4222047/D 04/2024 SOT-23 - 1.1 mm max heightDDF0008A PLASTIC SMALL OUTLINE NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225036/A 06/2019 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRB0008J A 0.08 C 0.05 C B SYMM SYMM PIN 1 INDEX AREA 3.1 2.9 3.1 2.9

1 MAX

0.05 0.00 SEATING PLANE C SECTION A-A TYPICAL (0.13)

0.1 MIN

1.75 1.55 (0.2) TYP (0.19) 8X 0.36 0.26 2.5 2.3 6X 0.65 1.95 8X 0.5 0.3 PIN 1 ID (OPTIONAL)

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

0.07 MAX

0.07 MIN

(1.65) (2.4) (2.8) (0.95) (0.575) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP (Ø 0.2) VIA TYP

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (1.51) (1.06) (2.8) (0.63) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP METAL TYP

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Product Information

TLIN2021ADDFRQ1 specifications and overview.

Summary

TLIN2021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake APRIL 2022

Description

TLIN2021A-Q1 Fault-Protected LIN Transceiver with Inhibit and Wake APRIL 2022

Source title TLIN2021ADDFRQ1 Datasheet(PDF) - Texas Instruments

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