TLIN1029A-Q1 TI | Alldatasheet
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TLIN1029A-Q1 Fault Protected LIN Transceiver with Dominant State Timeout
1 Features
- AEC-Q100 (Grade 1) Qualified for automotive
applications
- Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4 electrical physical layer (EPL) specification
- Conforms to SAE J2602-1 LIN network for vehicle
- Supports 12 V applications
- LIN transmit data rate up to 20-kbps
- LIN receive data rate up to 100 kbps
- Wide operational supply voltage range from 4-V to 36-V
- Sleep mode: ultra-low current consumption allows wake-up event from: – LIN bus – Local wake up through EN
- Power up and down glitch free operation on LIN bus and RXD output
- Protection features: – ±45-V LIN bus fault tolerant – Under voltage protection on V SUP – TXD Dominant time out protection (DTO) – Thermal shutdown protection – Unpowered node or ground disconnection failsafe at system level.
- Available in SOIC (8) and leadless VSON (8) with wettable flanks
2 Applications
- Body electronics and lighting
- Infotainment and cluster
- Hybrid electric vehicles and power train systems
- Passive safety
- Appliances
3 Description
The TLIN1029A-Q1 is a local interconnect network (LIN) physical layer transceiver with integrated wake- up and protection features, compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2 A and ISO/DIS 17987–4 standards. LIN is a single-wire bidirectional bus typically used for in-vehicle networks using data rates up to 20 kbps. The TLIN1029A-Q1 is designed to support 12-V applications with wider operating voltage and additional bus-fault protection. The LIN receiver supports data rates up to 100 kbps for faster in-line programming. The TLIN1029A-Q1 converts the data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open- drain RXD pin. Ultra-low current consumption is possible using the sleep mode which allows wake-up via LIN bus or EN pin. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TLIN1029A-Q1 SOIC (D) (8)(2) 4.90 mm x 3.91 mm VSON (DRB) (8) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Product preview LIN Controller Or SCU/UART VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pullup VSUP MCU GND I/O VREG LIN NC 1 k LIN Bus Commander Node Pullup 3 78 VBAT 220 pF NC Simplified Schematics, Commander Mode(1) LIN Controller or SCI/UART VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pullup VSUP MCU GND I/O VREG LIN LIN Bus 3 78 220 pF VBAT NC NC Simplified Schematics, Responder Mode(2) 1. Commander represents industry norm 'master'. 2. Responder represents industry norm 'slave'. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: TLIN1029A-Q1 TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
13.2 Receiving Notification of Documentation Updates..31
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2020 * Initial Release
5 Description (continued)
The TLIN1029A-Q1 integrates a resistor for LIN responder node applications, ESD protection, and fault protection which allow for a reduced amount of external components in the applications. The device prevents back-feed current through LIN to the supply input in case of a ground shift or supply voltage disconnection. The TLIN1029A-Q1 also includes undervoltage detection, temperature shutdown protection, and loss-of-ground protection. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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6 Pin Configuration and Functions
Figure 6-1. D Package, 8-Pin (SOIC), Top View 1RXD 8 NC 2EN 7 V SUP 3NC 6 LIN 4TXD 5 GND Not to scale Thermal Pad Figure 6-2. DRB Package, 8-Pin (VSON), Top View Table 6-1. Pin Functions PIN Type DESCRIPTION Name No. RXD 1 DO RXD output (open-drain) interface reporting state of LIN bus voltage EN 2 DI Enable input - High puts the device in normal operation mode and low puts the device in sleep mode NC 3 – Not connected TXD 4 DI TXD input interface to control state of LIN output - Internally pulled to ground GND 5 GND Ground LIN 6 HV I/O LIN bus single-wire transmitter and receiver VSUP 7 HV Supply Device supply voltage (connected to battery in series with external reverse blocking diode) NC 8 – Not connected Thermal Pad - Can be connected to the PCB ground plane to improve thermal coupling (DRB package only) www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLIN1029A-Q1
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2) Symbol Parameter MIN MAX UNIT VSUP Supply voltage range (ISO 17987) –0.3 45 V VLIN LIN bus input voltage (ISO 17987) –45 45 V VLOGIC Logic pin voltage (RXD, TXD, EN) –0.3 6 V IO Digital pin output current 8 mA TJ Junction temperature range –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to ground terminal.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM) classification level 3A: TXD, RXD, EN Pins, per AEC Q100-002(1) ±4000 V Human body model (HBM) classification level 3B: LIN and VSUP Pin with respect to ground ±8000 Charged device model (CDM) classification level C5, per AEC Q100-011 All terminals ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings - IEC
ESD and Surge Protection Ratings VALUE UNIT V(ESD) Electrostatic discharge, LIN, VSUP to GND(1) IEC 62228-2 per ISO 10605 Contact discharge R = 330 Ω, C = 150 pF ±8000 V VTRAN ISO 7637-2 and IEC 62228-2 per IEC 62215-3 transients according to IBEE LIN EMC test specifications(2) (LIN , VSUP to GND ) Pulse 1 –100 V Pulse 2 75 V Pulse 3a –150 V Pulse 3b 100 V (1) Results given here are specific to the IEC 62228-2 Integrated circuits – EMC evaluation of transceivers – Part 2: LIN transceivers. Testing performed by OEM approved independent 3rd party, EMC report available upon request. (2) ISO 7637 is a system level transient test. Different system level configurations may lead to diffrent results
7.4 Thermal Information
THERMAL METRIC(1) TLIN1029AD-Q1 TLIN1029ADRB-Q1 UNITD (SOIC) DRB (VSON) 8-PINS 8-PINS RΘJA Junction-to-ambient thermal resistance 115.5 48.5 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 58.7 55.5 °C/W RΘJB Junction-to-board thermal resistance 58.9 22.2 °C/W ΨJT Junction-to-top characterization parameter 14.1 1.2 °C/W ΨJB Junction-to-board characterization parameter 58.2 22.2 °C/W TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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7.4 Thermal Information (continued)
THERMAL METRIC(1) TLIN1029AD-Q1 TLIN1029ADRB-Q1 UNITD (SOIC) DRB (VSON) 8-PINS 8-PINS RΘJC(bot) Junction-to-case (bottom) thermal resistance 4.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
7.5 Recommended Operating Conditions
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER - DEFINITION MIN NOM MAX UNIT VSUP Supply voltage 4 36 V VLIN LIN Bus input voltage 0 36 V VLOGIC Logic Pin Voltage (RXD, TXD, EN) 0 5.25 V TA Ambient temperature range -40 125 ℃ TSD Thermal shutdown temperature 165 °C TSD(HYS) Thermal shutdown hysteresis 15 °C
7.6 Electrical Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply VSUP Operational supply voltage (ISO/DIS
17987 Param 10)
Device is operational beyond the LIN defined nominal supply voltage range See Figure 8-1 and Figure 8-2 4 36 V VSUP Nominal supply voltage (ISO/DIS 17987 Param 10) Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 4 36 V Sleep Mode 4 36 V UVSUP Under voltage VSUP threshold Min is falling edge and Max is rising edge 2.9 3.85 V UVHYS Delta hysteresis voltage for VSUP under voltage threshold 0.2 V ISUP Supply current Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF 1 5 mA Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF 1 2.1 mA ISUP Supply current Normal Mode: EN = high, bus recessive (LIN = VSUP) 300 650 µA Standby Mode: EN = low, bus recessive (LIN = VSUP) 10 30 µA Sleep Mode: 4.0 V < VSUP ≤ 14 V, LIN = VSUP, EN = 0 V, TXD and RXD floating 8 12 µA Sleep Mode: 14 V < VSUP ≤ 36 V, LIN = VSUP, EN = 0 V, TXD and RXD floating 20 µA TSD Thermal shutdown 165 ℃ TSD(HYS) Thermal shutdown hysteresis 15 ℃ RXD Output Pin (Open Drain) VOL Output low voltage Based upon external pull-up to VCC (4) 0.6 V www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TLIN1029A-Q1
7.6 Electrical Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA IILG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 µA TXD Input Pin VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.25 V IILG Low level input leakage current TXD = low –5 0 5 µA RTXD Internal pull-down resistor value 125 350 800 kΩ LIN PIN VOH LIN recessive high-level output voltage (3) TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 36 V 0.85 VSUP VOH LIN recessive high-level output voltage (1) (2) TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 18 V 0.8 VSUP VOH LIN recessive high-level output voltage (3) TXD = high, IO = 0 mA, 4 V ≤ VSUP < 7 V 3 V VOL LIN dominant low-level output voltage (3) TXD = low, 7 V ≤ VSUP ≤ 36 V 0.2 VSUP VOL LIN dominant low-level output voltage (1) (2) TXD = low, 7 V ≤ VSUP ≤ 18 V 0.2 VSUP VOL LIN dominant low-level output voltage (3) TXD = low, 4 V ≤ VSUP < 7 V 1.2 V VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open LIN = 4 V to 45 V –0.3 45 V IBUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 18 V, VSUP = 18 V 40 90 200 mA IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13) LIN = 0 V, VSUP = 12 V Driver off/ recessive Figure 8-6 –1 mA IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) LIN > VSUP, 4 V ≤ VSUP ≤ 36 V Driver off; Figure 8-7 20 µA IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) LIN = VSUP, Driver off; Figure 8-7 –5 5 µA IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, VSUP = 18 V, RMeas = 1 kΩ, 0 V < VLIN < 18 V; Figure 8-8 –1 1 mA Ileak gnd(dom) Leakage current, loss of ground (5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RLeader = 1 kΩ, CL = 1 nF RFollower = 20 kΩ, CL = 1 nF LIN = dominant -1 1 mA Ileak gnd(rec) Leakage current, loss of ground (5) VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RLeader = 1 kΩ, CL = 1 nF RFollower = 20 kΩ, CL = 1 nF LIN = recessive -100 100 µA IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16) LIN = 18 V, VSUP = GND; Figure 8-9 5 µA VBUSdom Low level input voltage (ISO/DIS 17987 Param 17) (3) LIN dominant (including LIN dominant for wake up) See Figure 8-4, Figure 8-3 0.4 VSUP VBUSrec High level input voltage (ISO/DIS 17987 Param 18) (3) LIN recessive See Figure 8-4, Figure 8-3 0.6 VSUP VIH LIN recessive high-level input voltage (1) (2) 7 V ≤ VSUP ≤ 18 V 0.47 0.6 VSUP VIL LIN dominant low-level input voltge (1) (2) 7 V ≤ VSUP ≤ 18 V 0.4 0.53 VSUP VBUS_CNT Receiver center threshold (ISO/DIS
17987 Param 19)
VBUS_CNT = (VBUSrec + VBUSdom)/2 See Figure 8-4, Figure 8-3 0.475 0.5 0.525 VSUP TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VHYS Hysteresis voltage (ISO/DIS 17987 Param 20) VHYS = (VBUSrec - VBUSdom) See Figure 8-4, Figure 8-3 0.175 VSUP VHYS Hysteresis voltage (SAE J2602) VHYS = VIH - VIL See Figure 8-4, Figure 8-3 0.07 0.175 VSUP VSERIAL_DIODE Serial diode LIN termination pull-up path ISERIAL_DIODE = 10 μA 0.4 0.7 1 V RPU Internal pull-up resistor to VSUP Normal and standby modes 20 45 60 kΩ IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND –20 –2 µA CLINPIN Capacitance of the LIN pin VSUP = 14 V 25 pF EN Input Pin VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.25 V VIT Hysteresis voltage By design and characterization 50 500 mV IILG Low level input current EN = low –5 0 5 µA REN Internal pull-down resistor 125 350 800 kΩ (1) SAE 2602 leader node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ (2) SAE 2602 follower node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω (3) ISO 17987 bus load conditions (C LINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω. (4) RXD uses open drain output structure therefore V OL level is based upon microcontroller supply voltage VCC. (5) I leak gnd = (VBAT - VLIN)/RLoad
7.7 Duty Cycle Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) (3) THREC(MAX) = 0.744 x VSUP THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.396 D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) (3) THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.396 D1 Duty cycle 1 (1) (2) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 μs D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.396 D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) (3) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.581 D212V Duty Cycle 2 (3) THREC(MIN) = 0.546 x VSUP, THDOM(MIN) = 0.4 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.581 D2 Duty Cycle 2 (1) (2) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 μs D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.581 www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TLIN1029A-Q1
7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) (3) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.417 D312V Duty Cycle 3 (3) THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.417 D3 Duty Cycle 3 (1) (2) THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP VSUP = 7 V to 18 V, tBIT = 96 μs D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.417 D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) (3) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.59 D412V Duty Cycle 4 (3) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.59 D4 Duty Cycle 4 (1) (2) THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP VSUP = 7 V to 18 V, tBIT = 96 μs D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10, Figure 8-11) 0.59 D1LB Duty cycle 1 at low battery (1) (2) THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 52 μs 0.396 D2LB Duty cycle 2 at low battery (1) (2) THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 52 μs 0.581 D3LB Duty cycle 3 at low battery (1) (2) THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 μs 0.396 D4LB Duty cycle 4 at low battery (1) (2) THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 96 μs 0.581 Tr-d max Transmitter propagation delay timings for the duty cycle(1) (2) Recessive to dominant THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 52 μs
tREC(MAX)_D1 - tDOM(MIN)_D1 10.8 µs Td-r max Transmitter propagation delay timings for the duty cycle(1) (2) Dominant to recessive THREC(MAX) = 0.422 x VSUP, THDOM(MAX) = 0.284 x VSUP tDOM(MAX)_D2 - tREC(MIN)_D2 8.4 µs Tr-d max Transmitter propagation delay timings for the duty cycle(1) (2) Recessive to dominant THREC(MAX) = 0.778 x VSUP THDOM(MAX) = 0.616 x VSUP
7 V ≤ VSUP ≤ 18 V, tBIT = 96 μs
tREC(MAX)_D3 - tDOM(MIN)_D3 15.9 µs Td-r max Transmitter propagation delay timings for the duty cycle(1) (2) Dominant to recessive THREC(MIN) = 0.389 x VSUP THDOM(MIN) = 0.251 x VSUP tDOM(MAX)_D4 - tREC(MIN)_D4 17.28 µs TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Tr-d max_low Low battery transmitter propagation delay timings for the duty cycle(1) (2) Recessive to dominant THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP
5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tREC(MAX)_low - tDOM(MIN)_low 10.8 µs Td-r max_low Low battery transmitter propagation delay timings for the duty cycle(1) (2) Dominant to recessive THREC(MAX) = 0.496 x VSUP THDOM(MAX) = 0.361 x VSUP
6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 μs
tDOM(MAX)_low - tREC(MIN)_low 8.4 µs (1) SAE 2602 leader node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ (2) SAE 2602 follower node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω (3) ISO 17987 bus load conditions (C LINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
7.8 Switching Characteristics
parameters valid across -40℃ ≤ TA ≤ 125℃ (unless otherwise noted) SYMBOL DESCRIPTION TEST CONDITIONS MIN NOM MAX UNIT trx_pdr, trx_pdf Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 8-12 and Figure 8-13 ) 6 µs trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 8-12 and Figure 8-13 ) –2 2 µs tLINBUS LIN wakeup time (Minimum dominant time on LIN bus for wakeup) See Figure 8-16, Figure 9-2, and Figure 9-3 25 65 150 µs tCLEAR Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) See Figure 9-3 8 25 50 µs tDST Dominant state time out 20 45 80 ms tMODE_CHANGE Mode change delay time Time to change from standby mode to normal mode or normal mode to sleep mode through EN pin: (See Figure 8-14 and Figure 9-4) 2 15 µs tNOMINT Normal mode initialization time Time for normal mode to initialize and data on RXD pin to be valid. See Figure 8-14 35 µs tPWR Power up time Upon power up time it takes for valid data on RXD 1.5 ms www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TLIN1029A-Q1
7.9 Typical Characteristics
Supply voltage (V) High-level Output Voltage (V) 0 5 10 15 20 25 30 35 40 -55°C 25°C 125°C Figure 7-1. VOH vs VSUP and Temperature Supply voltage (V) Low-level Output Voltage (V) 0 5 10 15 20 25 30 35 40 0.6 0.8 1.2 1.4 1.6 1.8 -55°C 25°C 125°C Figure 7-2. VOL vs VSUP and Temperature Supply voltage (V) ISUP (mA) 0 5 10 15 20 25 30 35 40 0.25 0.5 0.75 1.25 1.5 1.75 2.25 2.5 -55°C 25°C 125°C Figure 7-3. Dominant ISUP vs VSUP and Temperature Supply voltage (V) ISUP (PA) 0 5 10 15 20 25 30 35 40 150 200 250 300 350 400 450 500 -55°C 25°C 125°C Figure 7-4. Recessive ISUP vs VSUP and Temperature Supply voltage (V) ISUP (mA) 0 5 10 15 20 25 30 35 40 0.2 0.4 0.6 0.8 -55°C 25°C 125°C Figure 7-5. Standby Dominant ISUP vs VSUP and Temperature Supply voltage (V) ISUP (PA) 0 5 10 15 20 25 30 35 40 -55°C 25°C 125°C Figure 7-6. Standby Recessive ISUP vs VSUP and Temperature TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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Supply voltage (V) ISUP (PA) 0 5 10 15 20 25 30 35 40 -55°C 25°C 125°C Figure 7-7. Sleep Current vs VSUP and Temperature www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TLIN1029A-Q1
8 Parameter Measurement Information
Square Wave: < 20 ns tR/tF Triangle Wave: < 40ns Frequency: 20 ppm Jitter: < 25 ns Measurement Tools O-scope: DMM Power Supply Resolution: 10mV/1mA Accuracy: 0.2% VPS 5 V RXD TXD EN NC NC LIN GND VSUP Copyright © 2017, Texas Instruments Incorporated Figure 8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10 Trigger Point Delta t = + 5 µs (tBIT = 50 µs) 2 x tBIT = 100 µs (20 kBaud) RX Figure 8-2. RX Response: Operating Voltage Range Period T = 1/f Amplitude (signal range) Frequency: f = 20 Hz Symmetry: 50% LIN Bus Input Figure 8-3. LIN Bus Input Signal TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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O-scope: DMM Power Supply Resolution: 10mV/1mA Accuracy: 0.2% VPS RXD TXD EN NC NC LIN GND VSUP RMEAS = 499 Copyright © 2017, Texas Instruments Incorporated Figure 8-6. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Param 13 Measurement Tools O-scope: DMM Power Supply 1 Resolution: 10mV/ 1mA Accuracy: 0.2% VPS1 RXD TXD EN NC NC LIN GND VSUP Power Supply 2 Resolution: 10mV/1mA Accuracy: 0.2% VPS2 1 k VPS2 2 V/s ramp [8 V Æ 36 V] V Drop across resistor < 20 mV Copyright © 2017, Texas Instruments Incorporated Figure 8-7. Test Circuit for IBUS_PAS_rec Param 14 TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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Square Wave: < 20 ns tR/tF Triangle Wave: < 40ns Frequency: 20 ppm Jitter: < 25 ns 5 V RXD TXD EN NC NC LIN GND VSUP RMEAS Power Supply 1 Resolution: 10mV/1mA Accuracy: 0.2% VPS1 Power Supply 2 Resolution: 10mV/1mA Accuracy: 0.2% VPS2 Measurement Tools O-scope: DMM Copyright © 2017, Texas Instruments Incorporated Figure 8-10. Test Circuit Slope Control and Duty Cycle Param 27, 28, 29, 30 TXD (Input) D = 50%TBIT THREC(MAX) THREC(MIN) THDOM(MAX) THDOM(MIN) tBUS_DOM(MAX) tBUS_REC(MIN) tBUS_DOM(MIN) tBUS_REC(MAX) LIN Bus Signal VSUP Thresholds RX Node 1 Thresholds RX Node 2 RXD: Node 1 D1 (20 kbps) D3 (10.4 kbps) RXD: Node 2 D2 (20 kbps) D4 (10.4 kbps) D112: 0.744 * VSUP D312: 0.778 * VSUP D112: 0.581 * VSUP D312: 0.616 * VSUP D212: 0.422 * VSUP D412: 0.389 * VSUP D212: 0.284 * VSUP D412: 0.251 * VSUP Figure 8-11. Definition of Bus Timing Parameters TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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tMODE_CHANGE tMODE_CHANGE Transition Sleep Floating Transition Indeterminate Ignore EN MODE RXD Wake Request RXD = Low Wake Event Normal Normal Mirrors Bus Mirrors Bus tNOMINT Figure 8-14. Mode Transitions VSUP EN RXD LIN MODE TXD Weak Internal Pulldown Floating Sleep Weak Internal Pulldown Normal Figure 8-15. Wakeup Through EN TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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TXD Weak Internal Pulldown Floating Sleep NormalStandby t < tLINBUS tLINBUS 0.4 x VSUP 0.4 x VSUP 0.6 x VSUP0.6 x VSUP Figure 8-16. Wakeup through LIN www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TLIN1029A-Q1
9 Detailed Description
9.1 Overview
The TLIN1029A-Q1 is a Local Interconnect Network (LIN) physical layer transceiver, compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards, with integrated wake-up and protection features. The LIN bus is a single-wire bidirectional bus typically used for low speed in-vehicle networks. The device transmitter supports data rates from 2.4-kbps to 20-kbps and the receiver works up to 100 kbps supporting in-line programming. The LIN protocol data stream on the TXD input is converted by the TLIN1029A-Q1 into a LIN bus signal using a current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data stream to logic-level signals that are sent to the microprocessor through the open- drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up components are required for responder node applications. commander node applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification. The device is designed to support 12-V applications with a wide input voltage operating range and also supports low-power sleep mode. The device also provides two methods to wake up: EN pin and from the LIN bus. The TLIN1029A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required external components in the applications. In the event of a ground shift or supply voltage disconnection, the device prevents back-feed current through LIN to the supply input. The device also includes undervoltage detection, temperature shutdown protection, and loss-of-ground protection.
9.2 Functional Block Diagram
& Protection Filter Wake Up State & Control EN NC VSUP LIN RXD TXD VSUP/2 45 N NC DR/ Slope CTL Comp 350 k 350 k TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This high voltage input/output pin is a single-wire LIN bus transmitter and receiver. The LIN pin can survive transient voltages up to 45 V. Reverse currents from the LIN to supply (V SUP) are minimized with blocking diodes, even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low- side transistor with internal current limitation and thermal shutdown. During a thermal shut-down condition, the transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are required for the LIN responder node applications. An external pull- up resistor and series diode to VSUP must be added when the device is used for a commander node application.
9.3.1.2 LIN Receiver Characteristics
The receiver’s characteristic thresholds are proportional to the device supply pin in accordance to the LIN specification. The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602 specifications. This allows the TLIN1029A-Q1 to be used for high speed downloads at the end-of-line production or other applications. The actual data rate achievable depends on system time constants (bus capacitance and pull-up resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to V SUP, so no external pull-up components are required for the LIN responder node applications. An external pull-up resistor (1 k Ω) and a series diode to V SUP must be added when the device is used for commander node applications as per the LIN specification. Figure 9-1 shows a commander node configuration and how the voltage levels are defined Simplified Transceiver Filter VSUP LIN RXD TXD VSUP/2 350 N 45 N Receiver Transmitter with slope control GND 1 N VSUP LIN Bus VLIN_Dominant VLIN_Recessive VBattery VSUP t VLIN_Bus Voltage drop across the diodes in the pullup path Copyright © 2017, Texas Instruments Incorporated Figure 9-1. Commander Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input and Output)
TXD is the interface to the MCU’s LIN protocol controller or SCI and UART that is used to control the state of the LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is recessive (near VBattery). See Figure 9-1. The TXD input structure is compatible with microcontrollers with 3.3 V and 5 V I/O. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TLIN1029A-Q1
9.3.3 RXD (Receive Output)
RXD is the interface to the MCU’s LIN protocol controller or SCI and UART, which reports the state of the LIN bus voltage. LIN recessive (near V Battery) is represented by a high level on the RXD and LIN dominant (near ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to be used with 3.3 V and 5 V I/O microcontrollers. If the microcontroller’s RXD pin does not have an integrated pull-up, an external pull-up resistor to the microcontroller I/O supply voltage is required. In standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. V SUP is connected to the battery through an external reverse-blocking diode (Figure 9-1). If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift does not reduce the V SUP below the minimum operating voltage, as well as ensuring the input and output voltages are within their appropriate thresholds. If there is a loss of ground at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).
9.3.6 EN (Enable Input)
EN controls the operational modes of the device. When EN is high the device is in normal operating mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN has an internal pull-down resistor to ensure the device remains in low-power mode even if EN floats.
9.3.7 Protection Features
The TLIN1029A-Q1 has several protection features that will now be described.
9.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on the TXD pin. If the low signal remains on TXD for longer than t DST, the transmitter is disabled, thus allowing the LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus pull-up termination remains on.
9.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN1029A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears” the bus stuck dominant, preventing excessive current consumption. Figure 9-2 and Figure 9-3 show the behavior of this protection. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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< tLINBUS < tLINBUS tLINBUS RXD Figure 9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup EN LIN Bus < tCLEAR tLINBUS tLINBUS tLINBUS tCLEAR RXD Figure 9-3. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.10 Thermal Shutdown
The LIN transmitter is protected by current limiting circuitry; however, if the junction temperature of the device exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the over-temperature fault condition has been removed and the junction temperature has cooled beyond the hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal operation mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN), the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains on.
9.3.11 Under Voltage on VSUP
The TLIN1029A-Q1 contains a power-on reset circuit to avoid false bus messages during under voltage conditions when VSUP is less than UVSUP.
9.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the network remain powered by the battery. The TLIN1029A-Q1 has extremely low unpowered leakage current from the bus so an unpowered node does not affect the network or load it down. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TLIN1029A-Q1
9.4 Device Functional Modes
The TLIN1029A-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections will describe these modes as well as how the device moves between the different modes. Figure 9-4 graphically shows the relationship while Table 9-1 shows the state of pins. Table 9-1. Operating Modes MODE EN RXD LIN BUS TERMINATION TRANSMITTER COMMENT Sleep Low Floating Weak current pull-up Off Standby Low Low 45 kΩ (typical) Off Wake-up event detected, waiting on MCU to set EN Normal High LIN bus data 45 kΩ (typical) On LIN transmission up to 20 kbps Sleep Mode Driver: Off RXD: Floating Termination: Weak pull-up Unpowered System VSUP < UVSUP Standby Mode Driver: Off RXD: Low Termination: 45 k Normal Mode Driver: On RXD: LIN Bus Data Termination: 45 k VSUP > UVSUP EN = High VSUP > UVSUP EN = Low VSUP < UVSUP EN = High VSUP < UVSUP VSUP < UVSUP EN = High EN = Low LIN Bus Wake up Copyright © 2017, Texas Instruments Incorporated Figure 9-4. Operating State Diagram
9.4.1 Normal Mode
If the EN pin is high at power up, the device will power up in normal mode. If the EN pin is low, it will power up in standby mode. The EN pin controls the mode of the device. In normal operational mode the receiver and transmitter are active and the LIN transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a logic high and a dominant signal on the LIN bus is a logic low. The driver transmits input data from TXD to the LIN bus. Normal mode is entered as EN transitions high while the TLIN1029A-Q1 is in sleep or standby mode for > tMODE_CHANGE plus tNOMINT. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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9.4.2 Sleep Mode
Sleep mode is the power saving mode for the TLIN1029A-Q1. Sleep mode is only entered when the EN pin is low and from normal mode. Even with extremely low current consumption in this mode, the TLIN1029A-Q1 can still wake up from LIN bus through a wake-up signal or if EN is set high for ≥ tMODE_CHANGE. The LIN bus is filtered to prevent false wake up events. The wake-up events must be active for the respective time periods (tLINBUS). The sleep mode is entered by setting EN low for longer than tMODE_CHANGE. While the device is in sleep mode, the following conditions exist:
- The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events in case an external connection to the LIN bus is lost.
- The normal receiver is disabled.
- EN input and LIN wake up receiver are active.
9.4.3 Standby Mode
This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The LIN bus responder mode termination circuit is turned on when standby mode is entered. Standby mode is When EN is set high for longer than t MODE_CHANGE while the device is in standby mode, the device returns to normal mode. The normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
9.4.4 Wake Up Events
There are two ways to wake up from sleep mode:
- Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN bus where the dominant state is be held for tLINBUS filter time. After this tLINBUS filter time has been met and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up event, eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
- Local wake up through EN being set high for longer than t MODE_CHANGE.
9.4.4.1 Wake Up Request (RXD)
When the TLIN1029A-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal mode, the RXD pin releases the wake up request signal and the RXD pin then reflects the receiver output from the LIN bus.
9.4.4.2 Mode Transitions
When the TLIN1029A-Q1 is transitioning from normal to sleep or standby modes the device needs the time tMODE_CHANGE to allow the change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep or standby to normal mode the device needs tMODE_CHANGE plus tNOMINT. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TLIN1029A-Q1
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
10.1 Application Information
The TLIN1029A-Q1 can be used as both a responder node device and a commander node device in a LIN network. The device comes with the ability to support both remote wake up request and local wake up request.
10.2 Typical Application
The device integrates a 45 kΩ pull-up resistor and series diode for responder node applications. For commander applications an external 1 k Ω pull-up resistor with series blocking diode can be used. Figure 10-1 shows the device being used in both commander mode and responder mode applications. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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SCU/UART(1) TLIN1029A-Q1 VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pullup(2) VSUP MCU GND I/O VREG LIN NC 1 k LIN Bus COMMANDER NODE Commander Node Pullup(3) 3 78 VBAT LIN Controller Or SCU/UART(1) TLIN1029A-Q1 VDD VDD VDD VSUP VSUP VDD I/O EN RXD TXD MCU w/o pullup(2) VSUP MCU GND I/O VREG LIN RESPONDER NODE 3 78 220 pF 220 pF NC NC NC A. If RXD on MCU on LIN responder node has internal pullup; no external pullup resistor is needed. B. If RXD on MCU or LIN responder node does not have an internal pullup requires external pullup resistor. C. Commander node applications require and external 1 kΩ pullup resistor and serial diode. D. Decoupling capacitor values on V SUP are system dependent but usually have 100 nF, 1 µF and ≥ 10 µF. Figure 10-1. Typical LIN Bus
10.2.1 Design Requirements
The RXD output structure is an open-drain output stage. This allows the TLIN1029A-Q1 to be used with 3.3- V and 5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be between 1 k Ω to 10 k Ω, depending on supply used (See I OL in electrical characteristics). The V SUP pin of the device should be decoupled with a 100-nF capacitor by placing it close to the V SUP supply pin. The system should include additional decoupling on the VSUP line as needed per the application requirements. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TLIN1029A-Q1
10.2.2 Detailed Design Procedures
10.2.2.1 Normal Mode Application Note
When using the TLIN1029A-Q1 in systems which are monitoring the RXD pin for a wake up request, special care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period between states as the receivers are switched. The application software should not look for an edge on the RXD pin indicating a wake up request until tMODE_CHANGE. This is shown in Figure 8-14
10.2.2.2 Standby Mode Application Note
If the TLIN1029A-Q1 detects an under voltage on V SUP the RXD pin transitions low and would signal to the software that the TLIN1029A-Q1 is in standby mode and should be returned to sleep mode for the lowest power state.
10.2.3 Application Curves
The below figures show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive and recessive to dominant edges. Device was configured in commander mode with external pull-up resistor (1 kΩ) and 680 pF bus capacitance. Figure 10-2. Recessive to Dominant Propagation Figure 10-3. Dominant to Recessive Propagation
11 Power Supply Recommendations
The TLIN1029A-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V to 36 V. A 100 nF decoupling capacitor should be placed as close to the V SUP pin of the device as possible. It is good practice for some applications with noisier supplies to include 1 µF and 10 µF decoupling capacitor, as well. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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12 Layout
In order for your PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the PCB and system.
12.1 Layout Guidelines
- Pin 1 (RXD): The pin is an open-drain output and requires an external pull-up resistor in the range of 1 kΩ to 10 kΩ to function properly. Note that the minimum value will depend on the VIO supply used. See IOL in electrical specifications. If the microprocessor paired with the transceiver does not have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the microprocessor.
- Pin 2 (EN): EN is an input pin that is used to place the device in a low-power sleep mode. If this feature is not used the pin should be pulled high to the regulated voltage supply of the microprocessor through a series resistor between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit current on the digital lines in the case of an over voltage fault.
- Pin 3 (NC): Not Connected.
- Pin 4 (TXD): The TXD pin is used to transmit the input signal from the microcontroller. A series resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
- Pin 5 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
- Pin 6 (LIN): This pin connects to the LIN bus. For responder mode applications a 220 pF capacitor to ground is implemented. For commander mode applications an additional series resistor and blocking diode should be placed between the LIN pin and the VSUP pin. See Figure 10-1.
- Pin 7 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close to the device as possible.
- Pin 8 (NC): Not Connected. Note All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TLIN1029A-Q1
12.2 Layout Example
Figure 12-1. Layout Example TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
- LIN Standards: – ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use case definition – ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer (EPL) specification 12V/24V – SAEJ2602-1: LIN Network for Vehicle Applications – LIN Specifications LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A
- EMC requirements: – SAEJ2962-1: Communication Transceivers Qualification Requirements - LIN – ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge – ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband radiated electromagnetic energy - Part 4: Harness excitation methods – ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions and general considerations – ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines – IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4: Direct RF power injection method – IEC 61000-4-2 – IEC 61967-4 – CISPR25
- Conformance Test requirements: – ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL) conformance test specification – SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. www.ti.com TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TLIN1029A-Q1
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TLIN1029A-Q1 SLLSFK8 – DECEMBER 2020 www.ti.com
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www.ti.com 25-Dec-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLIN1029ADRBRQ1 ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 (TL029, TL029A) TLIN1029ADRQ1 PREVIEW SOIC D 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 TL029 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Dec-2020 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLIN1029ADRBRQ1 SON DRB 8 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Dec-2020 Pack Materials-Page 2
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225036/A 06/2019 www.ti.com VSON - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD DRB0008J A 0.08 C
0.1 C A B
0.05 C B SYMM SYMM PIN 1 INDEX AREA 3.1 2.9 3.1 2.9
1 MAX
0.05 0.00 SEATING PLANE C SECTION A-A TYPICAL (0.13)
0.1 MIN
1.75 1.55 (0.2) TYP (0.19) 8X 0.36 0.26 2.5 2.3 6X 0.65 1.95 8X 0.5 0.3 PIN 1 ID (OPTIONAL)
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
0.07 MAX
0.07 MIN
(1.65) (2.4) (2.8) (0.95) (0.575) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP (Ø 0.2) VIA TYP
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225036/A 06/2019 www.ti.com VSON - 1 mm max heightDRB0008J PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (1.51) (1.06) (2.8) (0.63) 8X (0.6) 8X (0.31) 6X (0.65) (1.95) 4 5 (R0.05) TYP METAL TYP
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