TLIN10285SDRQ1

TLIN1028S-Q1 TI1 | Alldatasheet

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Technical content

3,PAD 200 pF VBAT Vcc nRTS 1 kQ MASTER NODE Master Node Pullup 10 µF 100 nF LIN Controller Or SCI/UART VDD VSUP VDD I/O EN RXD TXD MCU w/o pullup Low Power MCU GND I/O LIN LIN Bus Slave Node 3,PAD 200 pF VBAT Vcc nRTS 10 µF 100 nF Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLIN1028S-Q1 SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 TLIN1028S-Q1AutomotiveLocalInterconnectNetwork(LIN)Transceiver70-mASystem BasisChip(SBC)

1 Features

1• AEC-Q100 (Grade 1): Qualified for automotive

applications

• Local interconnect network (LIN) physical layer specification ISO/DIS 17987–4.2 compliant and conforms to SAE J2602 recommended practice for LIN
• Supports 12 V applications
• Wide Operating Ranges – ±58 V LIN bus fault protection – LDO output supporting 3.3 V or 5 V – Sleep mode: ultra-low current consumption allows wake up event from: – LIN bus or local wake through EN pin – Power up and down glitch-free operation
• Protection Features: – ESD protection – Under voltage protection on VSUP – TXD dominant time out (DTO) protection – Thermal shutdown protection – Unpowered node or ground disconnection failsafe at system level
• VCC sources up to 70 mA
• Available in SOIC (8) package

2 Applications

• Body electronics and lighting
• Hybrid, electric & powertrain systems
• Automotive infotainment and cluster
• Appliances

3 Description

The TLIN1028S-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.2A ISO/DIS 17987–4.2 standards, with an integrated low dropout (LDO) voltage regulator. LIN is a single-wire bidirectional bus typically used for low speed in-vehicle networks using data rates up to 20 kbps. The LIN receiver supports data rates up to 100 kbps for end-of-line programming. The TLIN1028S-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal. The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open- drain RXD pin. The TLIN1028S-Q1 reduces system complexity by providing a 3.3 V or 5 V rail with up to 70 mA of current to power microprocessors, sensors or other devices. The TLIN1028S-Q1 has an optimized current-limited wave-shaping driver which reduces electromagnetic emissions (EME). Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLIN1028S-Q1 SOIC (8) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematics, Master Mode Simplified Schematics, Slave Mode

SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLIN1028S-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents

13.2 Receiving Notification of Documentation Updates 33

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES November 2019 * Initial release

www.ti.com SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 Product Folder Links: TLIN1028S-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) HV - High Voltage, DI - Digital Input, DO - Digital Output, HV I/O - High Voltage Input/Output (2) When the thermal pad is present, it must be soldered to ground plane.

5 Description (continued)

Ultra-low current consumption is possible using the sleep mode which allows wake up via LIN bus or pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up components are required for slave applications. Master applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification.

6 Pin Configuration and Functions

8-Pin (SOIC) Top View Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 VSUP HV Supply In Device supply voltage (connected to battery in series with external reverse blocking diode)

2 EN D I Enable input

3 GND GND Ground (2)

4 LIN HV I/O LIN bus single-wire transmitter and receiver

5 RXD D O RXD output (open-drain) interface reporting state of LIN bus voltage

6 TXD D I TXD input interface to control state of LIN output

7 nRST D O Reset output (active low)

8 VCC Supply Out Output voltage from integrated LDO

SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLIN1028S-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Device will enter thermal shutdown prior to hitting this limit but if the limit is reach the device may sustain permanent damage.

7 Specifications

7.1 ABSOLUTE MAXIMUM RATINGS

VSUP Supply voltage range –0.3 42 V VLIN LIN Bus input voltage –58 58 V VCC50 Regulated 5 V Output Supply –0.3 6 V VCC33 Regulated 3.3 V Output Supply –0.3 4.5 V VnRST Reset output voltage –0.3 VCC + 0.3 V VLOGIC_INPUT Logic input voltage –0.3 6 V VLOGIC_OUTPUT Logic output voltage –0.3 6 V IVCC VCC supply current(2) 300 mA IO Digital pin output current –8 8 mA IO(nRST) Reset output current –5 5 mA TJ Junction temperature –40 165 °C Tstg Storage temperature range –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD RATINGS

V(ESD) Electrostatic discharge Human body model (HBM) classification level H2: VSUP, LIN, and WAKE with respect to ground ±8000 VHuman body model (HBM) classification level 3A: all other pins, per AEC Q100- 002(1) ±4000 Charged device model (CDM) classification level C5, per AEC Q100-011 All pins ±750 (1) IEC 62228-2 ESD testing performed at third party. Different system-level configurations may lead to different results. Test reports availabel upon request. (2) SAE J2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.

7.3 ESD RATINGS, IEC SPECIFICATION

V(ESD) Electrostatic discharge per IEC 62228-2 (1), LIN, VSUP terminal to GND Contact discharge ±15000 V Indirect ±15000 V V(ESD) Powered electrostatic discharge per SAE J2962- 1(2) Contact discharge ±8000 V Air discharge ±25000 Transient ISO 7637-2 and IEC 62215-3 transients per IEC 62228-2(1) Pulse 1 -100 V Pulse 2a 75 Pulse 3a -150 Pulse 3b 100

7.4 RECOMMENDED OPERATING CONDITIONS

VSUP Supply voltage 5.5 28 V VLIN LIN bus input voltage 0 28 V VLOGIC5 Logic pin voltage 0 5.25 V VLOGIC33 Logic pin voltage 0 3.465 V IOH(DO) Digital terminal HIGH level output current -2 mA IOL(DO) Digital terminal LOW level output current 2 mA C(VSUP) VSUP supply capacitor 100 nF

www.ti.com SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 Product Folder Links: TLIN1028S-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT C(VCC) VCC supply capacitor 10 µF ESRCO Output ESR requirements 0.001 2 Ω (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 THERMAL INFORMATION

THERMAL METRIC(1) TLIN1028x UNITD

8 PINS

RθJA Junction-to-ambient thermal resistance 119.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.5 °C/W RθJB Junction-to-board thermal resistance 64.9 °C/W ψJT Junction-to-top characterization parameter 9.6 °C/W ψJB Junction-to-board characterization parameter 63.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) RXD pin is an open drain output. In standby mode RXD is pulled low which has the device pulling current through VSUP through the pull-up resisitor to VCC. The value of the pull-up resistor impacts the standby mode current. A 10 kΩ resistor value can add as much at 500 µA of current.

7.6 POWER SUPPLY CHARACTERISTICS

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT VSUP Operational supply voltage (ISO/DIS 17987 Param 10) Device is operational beyond the LIN defined nominal supply voltage range. See Figure 5 and Figure 6 5.5 36 V VSUP Nominal supply voltage (ISO/DIS 17987 Param 10): Normal and Standby Modes: Ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and swing between 5.5 V ≤ VLIN ≤ 28 V. See Figure 5 and Figure 6 5.5 28 V Sleep Mode 5.5 28 V UVSUPR Under voltage VSUP threshold Ramp Up 3.5 4.2 V UVSUPF Under voltage VSUP threshold Ramp Down 1.8 2.1 2.5 V UVHYS Delta hysteresis voltage for VSUP under voltage threshold 1.5 V ISUP Transceiver and LDO supply current Transceiver normal mode dominant plus LDO output 80 mA ISUPTRXDOM Supply current transceiver only Normal Mode: EN = VCC, bus dominant: total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF 1.2 5 mA Standby Mode: EN = 0 V, bus dominant: total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF 1 1.8 mA ISUPTRXREC Supply current transceiver only Normal Mode: EN = VCC, Bus recessive: LIN = VSUP, 450 775 µA Standby Mode: EN = 0 V, LIN = recessive = VSUP, IOZH from processor ≤ 1 µA 38 55 µAAdded Standby Mode current through the RXD pull-up resistor with a value of 100 kΩ: EN = 0 V, LIN = recessive = VSUP, RXD = GND(1) ISUPTRXSLP Sleep mode supply current transceiver only 5.5 V < VSUP ≤ 28 V, LIN = VSUP, EN = 0 V, TXD and RXD floating 17 33 µA REGULATED OUTPUT VCC VCC Regulated output VSUP = 5.5 to 28 V, ICC = 1 to 70 mA –2 2 % ∆VCC(∆VSUP) Line regulation VSUP = 5.5 to 28 V, ΔVCC, ICC = 10 mA 50 mV ∆VCC(∆VSUPL) Load regulation ICC = 1 to 70 mA, VSUP = 14 V, ΔVCC 50 mV

SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLIN1028S-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated POWER SUPPLY CHARACTERISTICS (continued) parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Specified by design VDROP Dropout voltage (5 V LDO) VSUP – VCC, ICC = 70 mA; 300 600 mV VDROP Dropout voltage (3.3 V LDO) VSUP – VCC, ICC = 70 mA; 350 700 mV UVCC5R Under voltage 5 V VCC threshold Ramp Up 4.7 4.86 V UVCC5F Under voltage 5 V VCC threshold Ramp Down 4.2 4.45 V UVCC33R Under voltage 3.3 V VCC threshold (2) Ramp Up 2.9 3.1 V UVCC33F Under voltage 3.3 V VCC threshold (2) Ramp Down 2.5 2.75 V tDET(UVCC) VCC undervoltage deglitch time. An UVCC event will not be recognized unless it last longer than this. (2) CnRST = 20pF 1 15 µs ICCOUT Output current VCC in regulation with 12 V VSUP 0 70 mA ICCOUTL Output current limit VCC short to ground 275 mA PSRR Power supply rejection ripple rejection VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100 Hz, CO = 10 μF 60 dB TSDR Thermal shutdown temperature Internal junction temperature - rising 165 °C TSDF Thermal shutdown temperature Internal junction temperature - falling 150 °C TSDHYS Thermal shutdown hysteresis 10 °C

7.7 ELECTRICAL CHARACTERISTICS

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RXD OUTPUT TERMINAL (OPEN DRAIN) VOL Output low voltage Based upon a 2 kΩ to 10 kΩ external pull-up to VCC

0.2 VCC

IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA ILKG Leakage current, high-level LIN = VSUP, RXD = VCC –5 0 5 µA TXD INPUT TERMINAL VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.5 V IIH High level input leakage current TXD = high –5 0 5 µA RTXD Internal pull-up resistor value 125 350 800 kΩ LIN TERMINAL (REFERENCED TO VSUP) VOH HIGH level output voltage LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 36 V 0.85 VSUP VOL LOW level output voltage LIN dominant, TXD = low, VSUP = 5.5 V to 36 V 0.2 VSUP VSUP_NON_OP VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open, VLIN = 5.5 V to 42 V, Bus Load = 60 kΩ + diode and 1.1 kΩ + diode –0.3 42 V I BUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 36 V, RMEAS = 440 Ω, VSUP = 36 V, VBUSdom < 4.518 V; Figure 9 40 90 200 mA I BUS_PAS_dom Receiver leakage current, dominant (ISO/DIS

17987 Param 13)

VLIN = 0 V, VSUP = 12 V Driver off/recessive, RMEAS = 499 Ω; Figure 10 –1 mA I BUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS

17987 Param 14)

VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off, RMEAS = 1 kΩ; Figure 11 20 µA I BUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS VLIN = VSUP, Driver off, RMEAS = 1 kΩ; Figure 11 –8 8 µA I BUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V, RMEAS = 1 kΩ; Figure 12 –1 1 mA IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS 17987 Param 16)

0 V ≤ VLIN ≤ 28 V, VSUP = GND, RMEAS = 10

kΩ; Figure 13 8 µA VBUSdom Low level input voltage (ISO/DIS 17987 Param 17) LIN dominant (including LIN dominant for wake up); Figure 7, Figure 8 0.4 VSUP VBUSrec High level input voltage (ISO/DIS 17987 Param 18) LIN recessive; Figure 7, Figure 8 0.6 VSUP

www.ti.com SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 Product Folder Links: TLIN1028S-Q1 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated ELECTRICAL CHARACTERISTICS (continued) parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBUS_CNT Receiver center threshold (ISO/DIS 17987 Param 19) VBUS_CNT = (VIL + VIH)/2; Figure 7, Figure 8 0.475 0.5 0.525 VSUP VHYS Hysteresis voltage (ISO/DIS 17987 Param 20) VHYS = (VIL - VIH); Figure 7, Figure 8 0.175 VSUP VSERIAL_DIODE Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) By design and characterization 0.4 0.7 1.0 V RSLAVE Pull-up resistor to VSUP (ISO/DIS 17987 Param 26) Normal and Standby modes 20 45 60 kΩ IRSLEEP Pull-up current source to VSUP Sleep mode, VSUP = 12 V, LIN = GND –20 –2 µA CLIN,PIN Capacitance of the LIN pin 55 pF EN INPUT TERMINAL VIH High level input voltage 2 5.5 V VIL Low level input voltage –0.3 0.8 V VHYS Hysteresis voltage By design and characterization 30 500 mV IIL Low level input current EN = Low –5 0 5 µA REN Internal pull-down resistor 125 350 800 kΩ ILKG Leakage current, high-level LIN = VSUP, nRST = VCC –5 5 µA VOL Low-level output voltage Based upon external pull up to VCC 0.2 VCC IOL Low-level output current, open drain LIN = 0 V, nRST = 0.4 V 1.5 mA DUTY CYCLE CHARACTERISTICS D112V Duty Cycle 1 (ISO/DIS 17987 Param 27) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 14, Figure 15) 0.396 D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 14, Figure 15) 0.581 D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 14, Figure 15) 0.417 D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 14, Figure 15) 0.59

7.8 AC SWITCHING CHARACTERISTICS

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DEVICE SWITCHING CHARACTERISTICS trx_pdr trx_pdf Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 16, Figure 17 and Figure 21) 6 µs trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS

17987 Param 32)

Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (Figure 16, Figure 17 and Figure 21) –2 2 µs tLINBUS LIN wakeup time (minimum dominant time on LIN bus for wakeup) See Figure 20, Figure 24 and Figure 25 25 100 150 µs tCLEAR Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) See Figure 25 8 17 50 µs tTXD_DTO Dominant state time out 20 34 80 ms

SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLIN1028S-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated AC SWITCHING CHARACTERISTICS (continued) parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN Enable pin deglitch time Time enable pin state change before initiating mode change or sampling TXD pine: See Figure 18 3 12 µs tMODE_CHANGE Mode change delay time normal mode to sleep or standby mode Time to change from normal mode to sleep or standby after TXD pin sampling after EN pin set low: See Figure 18 20 µs tMODE_CHANGE Mode change delay time sleep mode to normal mode Time to change from sleep mode to normal mode through EN pin and not due to a wake event; RXD pulled up to VCC: See Figure 18 400 µs tNOMINT Normal mode initialization time Time for normal mode to initialize and data on RXD pin to be valid after tEN See Figure 18 35 µs tPWR Power up time Upon power up time it takes for valid data on RXD 1.5 ms

7.9 Typical Characteristics

Figure 1. ICC vs VSUP vs Temperature Figure 2. ICC vs VSUP vs Temperature Figure 3. Sleep Mode Current Across VSUP and Temperature Figure 4. Sleep Mode Current Across VSUP and Temperature

8 Parameter Measurement Information

8.1 Test Circuit: Diagrams and Waveforms

Figure 5. Test System: Operating Voltage Range with RX and TX Access Figure 6. RX Response: Operating Voltage Range Figure 7. LIN Bus Input Signal

Figure 18. Mode Transitions

Figure 19. Wakeup Through EN

9 Detailed Description

9.1 Overview

bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. from VSUP providing 5 V ±2% or 3.3 V ±2% with up to 70 mA of current depending upon system implementation. nRST is asserted high when VCC increases above UVCC and stays high as long as VCC is above this threshold.

9.2 Functional Block Diagram

Figure 22. Functional Block Diagram

9.3 Feature Description

9.3.1 LIN (Local Interconnect Network) Bus

even in the event of a ground shift or loss of supply (VSUP).

9.3.1.1 LIN Transmitter Characteristics

resistor and series diode to VSUP must be added when the device is used for a master node application.

9.3.1.2 LIN Receiver Characteristics

pull-up resistance) and driver characteristics used in the system.

9.3.1.2.1 Termination

be added when the device is used for master node applications as per the LIN specification. Figure 23. Master Node Configuration with Voltage Levels

9.3.2 TXD (Transmit Input and Output)

system failure driving TXD low through the dominant state time-out timer.

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9.3.3 RXD (Receive Output)

RXD is the interface to the processors LIN protocol controller, which reports the state of the LIN bus voltage. LIN recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to be used with 3.3 V and 5 VI/O processors. If the processors RXD pin does not have an integrated pull-up, an external pull-up resistor to the processors I and O supply voltage is required. In standby mode, the RXD pin is driven low to indicate a wake up request from the LIN bus from sleep mode. When going from normal mode to standby mode the RXD pin is released and pulled up to the voltage rail the external pull-up resistor is connected.

9.3.4 VSUP (Supply Voltage)

VSUP is the power supply pin. VSUP is connected to the battery through an external reverse battery-blocking diode. The VSUP pin is a high-voltage-tolerant pin. Decoupling capacitor with a value of 100 nF is recommended to be connected close to this pin to better the transient performance. If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied). When VSUP drops low enough the regulated output drops out of regulation. The LIN bus works with a VSUP as low as 5.5 V, but at a lower voltage, the performance is indeterminate and not ensured. If VSUP voltage level drops enough, it triggers the UVSUP, and if it keeps dropping, at some point it passes the POR threshold.

9.3.5 GND (Ground)

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).

9.3.6 EN (Enable Input)

EN controls the operational modes of the device. When EN is high, the device is in normal operating mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep mode and there are no transmission paths available. EN has an internal pull-down resistor to ensure the device remains in low power mode even if EN is left floating. EN should be held low until VSUP reaches the expected system voltage level. 9.3.7 nRST (Reset Output) The VCC pin is monitored for under voltage events. This pin is internally pulled up to VCC and when an undervoltage event takes place, this pin is pulled low. The pin returns to VCC once the voltage on VCC exceeds the under voltage threshold. nRST is only dependent upon UVCC and not dependent upon the operational mode. If UVCC takes place for longer than tDET(UVCC) nRST is pulled low. If a thermal shutdown event takes place, this pin is pulled to ground.

9.3.8 VCC (Supply Output)

The VCC terminal can provide 5 V or 3.3 V with up to 70 mA to power up external devices when using high-k boards and thermal management best practices.

9.3.9 Protection Features

The device has several protection features that are described as follows.

9.3.9.1 TXD Dominant Time Out (DTO)

9.3.9.2 Bus Stuck Dominant System Fault: False Wake Up Lockout

preventing excessive current use. Figure 24 and Figure 25 show the behavior of this protection. Figure 24. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup Figure 25. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup

9.3.9.3 Thermal Shutdown

cools, the device enters standby mode as per the state diagram.

9.3.9.4 Under Voltage on VSUP

9.3.9.5 Unpowered Device and LIN Bus

so an unpowered node does not affect the network or load it down.

9.4 Device Functional Modes

shows the relationship while Table 1 shows the state of pins. Table 1. Operating Modes nRST comes on to VCC once thresholds are met. means UVCC threshold has been met.

Figure 26. Operating State Diagram

• RXD is latched low due to a wake event from sleep mode once entering standby mode
• RXD is high when entering standby mode from other modes and is not latch low for a wake event

9.4.1 Normal Mode

device enters normal mode after tMODE_CHANGE and tNOMINIT times.

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9.4.2 Sleep Mode

Sleep Mode is the power saving mode for the TLIN1028S-Q1. Even with extremely low current consumption in this mode, the device can still wake up from the LIN bus through a wake-up signal or if EN is set high for > . The wake-up events must be active for the respective time periods (tLINBUS). While the device is in sleep mode, the following conditions exist:

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake up receiver are active.

9.4.3 Standby Mode

Standby mode is entered either by a wake up event through LIN bus while the device is in sleep mode or by the EN pin from normal or standby init modes. From normal mode EN must be low for > tEN and TXD and nRST are high. RXD pin in standby mode is dependent upon how standby mode was entered. If entered from normal mode or power up, RXD is high. If entered from sleep mode, RXD is pulled low to indicate a wake event. During power up, if EN is low the device goes into standby mode, and if EN is high, the device goes into normal mode. EN has an internal pull-down resistor ensuring EN is pulled low if the pin is left floating in the system.

9.4.4 Wake Up Events

There are ways to wake up from sleep mode:

• Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the LIN bus where the dominant state is held for the tLINBUS filter time. After this tLINBUS filter time has been met and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake up event eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake up through EN being set high for longer than .

9.4.4.1 Wake Up Request (RXD)

When the TLIN1028S-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal mode, the RXD pin releases the wake up request signal and the RXD pin then reflects the receiver output from the LIN bus.

9.4.5 Mode Transitions

When the device is transitioning between modes, the device needs the time tMODE_CHANGE and tNOMINT to allow the change to fully propagate from the EN pin through the device into the new state.

9.4.6 Voltage Regulator

The device has an integrated high-voltage LDO that operates over a 5.5 V to 28 V input voltage range for both 3.3 V and 5 V VCC. The device has an output current capability of 70 mA and support fixed output voltages of 3.3 V (TLIN10283S-Q1) or 5 V (TLIN10285S-Q1). It features thermal shutdown and short-circuit protection to prevent damage during over-temperature and over-current conditions

9.4.6.1 VCC

The VCC pin is the regulated output based on the required voltage. The regulated voltage accuracy is ± 2%. The output is current limited. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVSUP threshold, the regulator shuts down until the input voltage returns above the UVSUPR level. The device monitors situations where VCC may drop below the UVCC level thus causing the nRST pin to be pulled low.

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9.4.6.2 Output Capacitance Selection

For stable operation over the full temperature range and with load currents up to 70 mA on VCC a certain capacitance is expected and depends upon the minimum load current. To support no load to full load a value of 10 µF and ESR smaller than 2 Ω is needed. For 500 µA to full load an 1 µF capacitance can be used. The low ESR recommendation is to improve the load transient performance.

9.4.6.3 Low-Voltage Tracking

At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage based on the load current (IL) and power switch resistor. This tracking allows for a smaller input capacitance and can possibly eliminate the need for a boost converter during cold-crank conditions.

9.4.6.4 Power Supply Recommendation

The device is designed to operate from an input-voltage supply range between 5.5 V and 28 V. This input supply must be well regulated. If the input supply is located more than a few inches from the device. The recommended minimum capacitance at the pin is 100 nF . The max voltage range is for the LIN functionality. Exceeding 24V for the LDO reduces the effective current sourcing capability due to thermal considerations.

(1) If RXD on MCU or LIN slave has internal pullup; no external pullup resistor is needed. (2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor. validate and test their design implementation to confirm system functionality.

10.1 Application Information

comes with the ability to support a remote wake up requests. It can provide the power to the local processor.

10.2 Typical Application

Figure 27. Typical LIN Bus

SLLSFG0 –NOVEMBER 2019–REVISED NOVEMBER 2019 www.ti.com Product Folder Links: TLIN1028S-Q1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Application (continued)

10.2.1 Design Requirements

10.2.1.1 Normal Mode Application Note

When using the TLIN1028S-Q1 in systems which are monitoring the RXD pin for a wake up request, special care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period between states as the receivers are switched. The application software should not look for an edge on the RXD pin indicating a wake up request until tMODE_CHANGE. This is shown in when transitioning to normal mode there is an initialization period shown as tNOMINIT.

10.2.1.2 TXD Dominant State Timeout Application Note

The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data rate of the device. The LIN protocol has different constraints for master and slave applications; thus, there are different maximum consecutive dominant bits for each application case and thus different minimum data rates.

10.2.1.3 Brownout

Figure 35 and show the behavior of the LIN, nRST and VCC pins during a brownout condition. For the TLIN10283S-Q1, VSUP down to ~ 2.24 V has results as shown. For the TLIN10285S-Q1, VSUP down to ~ 2.63 V has results as shown. When VSUP drops below these levels the signals are indeterminate.

10.2.2 Detailed Design Procedures

RXD on processors or LIN slave has internal pull-up; no external pull-up resistor is need. RXD on processors or LIN slave without internal pull-up requires external pull-up resistor. Master node applications require and external 1 kΩ pull-up resistor and serial diode.

10.2.3 Application Curves

Characteristic curves below show the LDO performance ramping between 0 V and up to 7 V. Figure 28. ISUP vs VSUP vs Temperature Figure 29. ISUP vs VSUP vs Temperature Figure 30. ISUP vs VSUP vs Temperature Ramp-down Figure 31. ISUP vs VSUP vs Temperature Ramp-down Figure 32. LIN Bus Performance Figure 33. Dominant to Recessive Propagation Delay

Figure 34. Recessive to Dominant Propagation Delay Figure 35. TLIN10283S-Q1 Brownout Figure 36. TLIN10285S-Q1 Brownout

11 Power Supply Recommendations

to 28 V . A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.

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12 Layout

PCB design should start with understanding that frequency bandwidth from approximately 3 MHz to 3 GHz is needed thus high frequency layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the PCB and system.

12.1 Layout Guidelines

• Pin 1 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close to the device as possible.
• Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit current on the digital lines in the event of an over voltage fault.
• Pin 3 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
• Pin 4 (LIN): This pin connects to the LIN bus. For slave applications, a 200 pF capacitor to ground is implemented. For master applications, an additional series resistor and blocking diode should be placed between the LIN pin and the VSUP pin. See Figure 27
• Pin 5 (RXD): The pin is an open drain output and requires and external pull-up resistor in the range of 1 kΩ to 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated pull-up, an external pull-up resistor should be placed on RXD. If RXD is connected to the VCC pin a higher pull-up resistor value can be used to reduce standby current.
• Pin 6 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor can be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
• Pin 7 (nRST): This pin connects to the processors as a reset out.
• Pin 8 (VCC): Output source, either 3.3 V or 5 V depending upon the version of the device. NOTE All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance.

12.2 Layout Example

Figure 37. Layout Example

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13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following: LIN Standards:

• ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use case definition
• ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer (EPL) specification 12V/24V
• SAE J2602-1: LIN Network for Vehicle Applications
• LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification EMC requirements:
• SAE J2962-2: TBD
• HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN
• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband radiated electromagnetic energy - Part 4: Harness excitation methods
• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions and general considerations
• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines
• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4: Direct RF power injection method
• IEC 61967-4
• CISPR25 Conformance Test requirements:
• ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL) conformance test specification
• SAE J2602-2: LIN Network for Vehicle Applications Conformance Test TLINx441 LDO Performance, SLLA427

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

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13.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-Dec-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLIN10285SDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL085 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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