Logic IC

TLIN1022DRQ1

Texas Instruments

Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout

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SCU/UART (1) TLIN1022 VDD VDD VDD VSUP VSUP VDD I/O EN1 RXD1 TXD1 MCU w/o pullup(2) VSUP MCU GND I/O VREG LIN1 LIN Bus SLAVE NODE 14 106 220 pF VBAT NC NC VDD I/O EN2 RXD2 TXD2 MCU w/o pullup(2) I/O LIN2 LIN Bus 220 pF4 NC NC Copyright © 2017, Texas Instruments Incorporated LIN Controller Or SCU/UART (1) TLIN1022 VDD VDD VDD VSUP VSUP VDD I/O EN1 RXD1 TXD1 MCU w/o pullup(2) VSUP MCU GND I/O VREG LIN1 1 N LIN Bus MASTER NODE Master Node Pullup 14 106 220 pF VBAT NC NC VDD I/O EN2 RXD2 TXD2 MCU w/o pullup(2) I/O LIN2 LIN Bus9 220 pF4 NC NC Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. TLIN1022-Q1 SLLSEZ8 –DECEMBER 2017 TLIN1022-Q1DualLocalInterconnectNetwork(LIN)TransceiverwithDominantState Timeout

1 Features

1• AEC-Q100 Qualified for Automotive Applications – Device Temperature: –40°C to 125°C Ambient – Device HBM Certification Level: ±8 kV – Device CDM Certification Level: ±1.5 kV

Compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2
Conforms to SAEJ2602 Recommended Practice for LIN
Supports 12 V Battery Applications
LIN Transmit Data Rate up to 20 kbps.
Wide Operating Ranges – 4 V to 36 V Supply Voltage – ±45 V LIN Bus Fault Protection
Sleep Mode: Ultra-Low Current Consumption Allows Wake-Up Event From: – LIN Bus – Local Wake up through EN
Power Up and Down Glitch Free Operation
Protection Features: – Under Voltage Protection on VSUP – TXD Dominant Time Out Protection (DTO) – Thermal Shutdown Protection – Unpowered Node or Ground Disconnection Failsafe at System Level.
Available in SOIC (14) Package and Leadless VSON (14) Package with Improved Automated Optical Inspection (AOI) Capability

2 Applications

Body Electronics and Lighting
Hybrid, Electric and Power Train Systems
Infotainment and Cluster
Appliances

3 Description

The TLIN1022-Q1 device is a Dual Local Interconnect Network (LIN) physical layer transceiver with integrated wake-up and protection features, complaint to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2 standards. LIN is a single wire bidirectional bus typically used for low speed in- vehicle networks using data rates up to 20 kbps. The TLIN1022-Q1 is designed to support 12 V applications with wider operating voltage and additional bus-fault protection. The LIN receiver supports data rates up to 100 kbps for in-line programming. The TLIN1022-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. Ultra-low current consumption is possible using the sleep mode which allows wake-up via LIN bus or pin. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLIN1022-Q1 SOIC (14) (D) 5.00 mm x 8.65 mm VSON (14) (DMT)(2) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Product Preview Spacer Simplified Schematics, Master Mode Simplified Schematics, Slave Mode

12.2 Receiving Notification of Documentation Updates 28

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2017 * Initial release.

5 Pin Configuration and Functions

14-Pin (SOIC) Top View 14-Pin (VSON) Top View (1) Product Preview Pin Functions PIN Type DESCRIPTION NO. NAME

1 RXD1 O Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage

2 EN1 I Channel 1 Enable Input

3 TXD1 I Channel 1 TXD input interface to control state of LIN output

4 RXD2 O Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage

5 EN2 I Channel 2 Enable Input

7 TXD2 I Channel 2 TXD input interface to control state of LIN output

8 GND GND Ground

9 LIN2 HV I/O Channel 2 High voltage LIN bus single-wire transmitter and receiver

10 VSUP Supply Device Supply Voltage (connected to battery in series with external reverse blocking diode)

13 LIN1 HV I/O Channel 1 High voltage LIN bus single-wire transmitter and receiver

6, 11, 12,

14 NC – Not Connected

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) Symbol Parameter MIN MAX UNIT VSUP Supply voltage range (ISO/DIS 17987 Param 10) –0.3 45 V VLIN LIN Bus input voltage (ISO/DIS 17987 Param 82) –45 45 V VLOGIC Logic Pin Voltage (RXD, TXD, EN) –0.3 5.5 V TA Ambient temperature range –40 125 °C TJ Junction Temp –55 150 °C

SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) LIN bus a stressed with respect to GND.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM) per AEC Q100-002(1) Pins RXD, RXD, EN (1) ±4000 VPins LIN Bus (2) and VSUP ±8000 Charged device model (CDM), per AEC Q100-011 All pins ±1500 (1) IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different system level configurations may lead to different results (2) Testing performed at 3rd party IBEE Zwickau test house, test report available upon request (3) SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request (4) ISO7637 is a system level transient test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different system level configurations may lead to different results.

6.3 ESD Ratings - IEC

ESD and Surge Protection Ratings VALUE UNIT V(ESD) IEC 61000-4-2 contact discharge electrostatic discharge(1) LIN bus and VSUP pin to GND(2) ±6000 V V(ESD) IEC 61000-4-2 air-gap discharge electrostatic discharge(1) LIN bus and VSUP pin to GND(2) ±15000 V(ESD) Powered ESD Performance, per SAEJ2962-1(3) contact discharge ±8000 V V(ESD) Powered ESD Performance, per SAEJ2962-1(3) air-gap discharge ±15000 ISO7637-2(4) & IEC 62215-3 Transients according to IBEE LIN EMC test spec LIN bus pin and VSUP Pulse 1 –100 V Pulse 2 75 V ISO7637-2(4) & IEC 62215-3 Transients according to IBEE LIN EMC test spec LIN bus pin and VSUP Pulse 3a –150 V Pulse 3b 100 V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TLIN1022D-Q1 TLIN1022DMT-Q1 UNITD (SOIC) DMT (VSON) 14-PINS 14-PINS RΘJA Junction-to-ambient thermal resistance 82.3 35.5 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 41.5 18.1 °C/W RΘJB Junction-to-board thermal resistance 38.4 13.1 °C/W ΨJT Junction-to-top characterization parameter 8.9 0.6 °C/W ΨJB Junction-to-board characterization parameter 38.1 13.1 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance n/a 2.5 °C/W

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER - DEFINITION MIN NOM MAX UNIT VSUP Supply voltage 4 36 V VLIN LIN Bus input voltage 0 36 V VLOGIC Logic Pin Voltage (RXD, TXD, EN) 0 5.25 V TSD Thermal shutdown edge 165 °C TSD(HYS) Thermal shutdown hysteresis 15 °C

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply VSUP Operational supply voltage (ISO/DIS

17987 Param 10)

Device is operational beyond the LIN defined nominal supply voltage range See Figure 8 and Figure 9 4 36 V VSUP Nominal supply voltage (ISO/DIS 17987 Param 10): Normal Mode: Ramp VSUP while LIN signal is a 10 kHZ Square Wave with 50 % duty cycle and 18V swing. Normal and Standby Modes: Ramp VSUP while LIN signal is a 10 kHZ Square Wave with 50 % duty cycle and 36V swing. See Figure 8 and Figure 9 4 36 V Sleep Mode 4 36 V UVSUP Under voltage VSUP threshold 2.9 3.85 V UVHYS Delta hysteresis voltage for VSUP under voltage threshold 0.2 V ISUP Supply Current Normal Mode: EN = High, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF See Figure 14 1.2 7.5 mA ISUP Supply Current Standby Mode: EN = Low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF See Figure 14 1.1 3.75 mA ISUP Supply Current Normal Mode: EN = High, Bus Recessive: LIN = VSUP, 670 1300 µA ISUP Supply Current Standby Mode: EN = Low, Bus Recessive: LIN = VSUP, 20 40 µA ISUP Supply Current Sleep Mode: 4.0 V < VSUP < 14 V, LIN = VSUP, EN = 0 V, TXD and RXD Floating 10 20 µA ISUP Supply Current Sleep Mode: 14 V < VSUP < 36 V, LIN = VSUP, EN = 0 V, TXD and RXD Floating 30 µA RXD OUTPUT PIN (OPEN DRAIN) VOL Output Low voltage Based upon External pull up to VCC 0.6 V IOL Low level output current, open drain LIN = 0 V, RXD = 0.4 V 1.5 mA IILG Leakage current, high-level LIN = VSUP, RXD = 5 V –5 0 5 µA TXD INPUT PIN VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.5 V VHYS Input threshold voltage, normal modes& selective wake modes 50 500 mV IILG Low level input leakage current TXD = Low –5 0 5 µA RTXD Interal pulldown resitor value 125 350 800 kΩ EN INPUT PIN VIL Low level input voltage –0.3 0.8 V VIH High level input voltage 2 5.5 V VHYS Hysteresis voltage By design and characterization 50 500 mV IILG Low level input current EN = Low –5 0 5 µA REN Internal Pulldown resistor 125 350 800 kΩ LIN PIN VOH High level output voltage LIN recessive, TXD = high, IO = 0 mA, VSUP = 7 V to 36 V 0.85 VSUP LIN recessive, TXD = high, IO = 0 mA, VSUP = 4 V ≤ VSUP < 7 V 3.0 V VOL Low level output voltage LIN dominant, TXD = low, VSUP = 7 V to 36 V 0.2 VSUP LIN dominant, TXD = low, VSUP = 4 V ≤ VSUP < 7 V 1.2 V

SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSUP_NON_OP VSUP where Impact of recessive LIN Bus < 5% (ISO/DIS 17987 Param 11) TXD & RXD open LIN = 4 V to 45 V –0.3 36 V IBUS_LIM Limiting current (ISO/DIS 17987 Param 12) TXD = 0 V, VLIN = 18 V, RMEAS = 440 Ω, VSUP = 18 V, VBUSdom < 4.518 V See Figure 13 40 90 200 mA IBUS_PAS_dom Receiver leakage current, dominant (ISO/DIS 17987 Param 13) LIN = 0 V, VSUP = 24 V Driver off/recessive See Figure 14 –1 mA IBUS_PAS_rec1 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) LIN > VSUP, 4 V < VSUP < 45 V Driver off; See Figure 15 20 µA IBUS_PAS_rec2 Receiver leakage current, recessive (ISO/DIS 17987 Param 14) LIN = VSUP, Driver off; See Figure 15 –5 5 µA IBUS_NO_GND Leakage current, loss of ground (ISO/DIS 17987 Param 15) GND = VSUP, 0 V ≤ VLIN ≤ 18 V, VSUP =

12 V; See Figure 16 –1 1 mA

IBUS_NO_BAT Leakage current, loss of supply (ISO/DIS

17987 Param 16) LIN = 36 V, VSUP = GND; See Figure 17 5 µA

Low level input voltage (ISO/DIS 17987 Param 17) LIN dominant (including LIN dominant for wake up) See Figure 10 and Figure 11 0.4 VSUP VBUSrec High level input voltage (ISO/DIS 17987 Param 18) Lin recessive See Figure 10 and Figure 11 0.6 VSUP VBUS_CNT Receiver center threshold (ISO/DIS

17987 Param 19)

VBUS_CNT = (VIL + VIH)/2 See Figure 10 and Figure 11 0.475 0.5 0.525 VSUP VHYS Hysteresis voltage (ISO/DIS 17987 Param 20) VHYS = (VIL - VIH) See Figure 10 and Figure 11 0.05 0.175 VSUP VSERIAL_DIODE Serial diode LIN term pullup path (ISO/DIS 17987 Param 21) By design and characterization 0.4 0.7 1 V RSLAVE Pullup resistor to VSUP (ISO/DIS 17987 Param 26) Normal and Standby modes 20 45 60 kΩ IRSLEEP Pullup current source to VSUP Sleep mode, VSUP = 14 V, LIN = GND –20 –2 µA CLINPIN Capacitance of LIN pin 45 pF (1) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The TLIN1029 also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D112V Duty Cycle 1 (ISO/DIS 17987 Param 27)(1) THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 18 and Figure 19) 0.396 D112V Duty Cycle 1 THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 18 and Figure 19) 0.396 D212V Duty Cycle 2 (ISO/DIS 17987 Param 28) THREC(MAX) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 4.6 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 18 and Figure 19) 0.581 D312V Duty Cycle 3 (ISO/DIS 17987 Param 29) THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 18 and Figure 19) 0.417

www.ti.com SLLSEZ8 –DECEMBER 2017 Product Folder Links: TLIN1022-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D312V Duty Cycle THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 18 and Figure 19) 0.417 D412V Duty Cycle 4 (ISO/DIS 17987 Param 30) THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 4.6 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 18 and Figure 19) 0.59

6.8 Timing Requirements

SYMBOL DESCRIPTION TEST CONDITIONS MIN NOM MAX UNIT trx_pdr Receiver rising propagation delay time (ISO/DIS 17987 Param 31) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 20 and Figure 21) 6 µs trx_pdf Receiver falling propagation delay time (ISO/DIS 17987 Param 31) 6 µs trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS 17987 Param 32) Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 20 and Figure 21) –2 2 µs tLINBUS LIN wakeup time (Minimum dominant time on LIN bus for wakeup) See Figure 24, Figure 27 and Figure 28 25 100 150 µs tCLEAR Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bust stuck dominant fault) See Figure 28 8 17 50 µs tDST Dominant state time out 20 34 80 ms tMODE_CHANGE Mode change delay time Time to change from standby mode to normal mode or normal mode to sleep mode through EN pin: See Figure 22 and Figure 29 2 15 µs tNOMINT Normal mode initialization time Time for normal mode to initialize and data on RXD pin to be valid See Figure 22 35 µs tPWR Power up time Upon power up time it takes for valid data on RXD 1.5 ms

6.9 Typical Characteristics

Figure 1. VOH vs VSUP and Temperature Figure 2. VOL vs VSUP and Temperature Figure 3. Supply Current vs Voltage Supply Across Figure 4. Supply Current vs Voltage Supply Across Figure 5. Supply Current vs Voltage Supply and Figure 6. Supply Current vs Voltage Supply and

Figure 7. Supply Current vs Voltage Supply and Temperature

7 Parameter Measurement Information

Figure 8. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10 Figure 9. RX Response: Operating Voltage Range

Figure 25. Test Circuit for AC Characteristics

Copyright © 2017, Texas Instruments Incorporated Comp DR/ Slope CTL Dominant State Timeout Fault Detection & Protection Filter Wake Up State & Control EN1 NC LIN1 RXD1 TXD1 VSUP /2 350 k 45 N NC Comp DR/ Slope CTL Dominant State Timeout Fault Detection & Protection Filter Wake Up State & ControlEN2 VSUP LIN2 RXD2 TXD2 VSUP /2 350 k 45 N NC NC VSUP GND VSUP TLIN1022-Q1 SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TLIN1022-Q1 device is a Dual Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks using data rates from 2.4 kbps to 20 kbps. The TLIN1022-Q1 LIN receiver works up to 100 kbps supporting in-line programming. The LIN protocol data stream on the TXD input is converted by the TLIN1022-Q1 into a LIN bus signal using a current-limited wave-shaping driver as outlined by the LIN physical layer specification. The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up components are required for slave applications. Master applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification. The TLIN1022-Q1 provides many protection features such as ESD, EMC and high bus standoff voltage. The device also provides three methods to wake up, EN and from the LIN bus.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 LIN (Local Interconnect Network) Bus

even in the event of a ground shift or loss of supply (VSUP).

8.3.1.1 LIN Transmitter Characteristics

resistor and series diode to VSUP must be added when the device is used for a master node application.

8.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are proportional to the device supply pin according to the LIN specification. up resistance) and driver characteristics used in the system.

8.3.1.2.1 Termination

be added when the device is used for master node applications as per the LIN specification. Figure 26. Master Node Configuration with Voltage Levels

8.3.2 TXD (Transmit Input and Output)

system failure driving TXD low through the dominant state timer-out timer.

8.3.3 RXD (Receive Output)

RXD is the interface to the processors LIN protocol controller or SCI and UART, which reports the state of the LIN bus voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This allows the device to be used with 3.3 V and 5 V I/O processors. If the processors RXD pin does not have an integrated pull-up, an external pull-up resistor to the processors I/O supply voltage is required. In standby mode the RXD pin is driven low to indicate a wake up request from the LIN bus.

8.3.4 VSUP (Supply Voltage)

VSUP is the power supply pin. VSUP is connected to the battery through and external reverse battery blocking diode (See Figure 26). If there is a loss of power at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).

8.3.5 GND (Ground)

GND is the device ground connection. The device can operate with a ground shift as long as the ground shift does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the device has extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).

8.3.6 EN (Enable Input)

EN controls the operational modes of the device. When EN is high the device is in normal operating mode allowing a transmission path from TXD to LIN and from LIN to RXD. When EN is low the device is put into sleep mode and there are no transmission paths available. The device can enter normal mode only after wake up. EN has an internal pull-down resistor to endure the device remains in low power mode even if EN floats.

8.3.7 Protection Features

The TLIN1022-Q1 has several protection features.

8.3.8 TXD Dominant Time Out (DTO)

During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no change of stated request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus pull-up termination remains on.

8.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout

The TLIN1022-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus is dominant, the wake up logic is locked out until a valid recessive on the bus “clears” the bus stuck dominant, preventing excessive current use. Figure 27 and Figure 28 show the behavior of this protection.

Figure 27. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup Figure 28. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup

8.3.10 Thermal Shutdown

is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains on.

8.3.11 Under Voltage on VSUP

when VSUP is less than UVSUP.

8.3.12 Unpowered Device and LIN Bus

so an unpowered node does not affect the network or load it down.

8.4 Device Functional Modes

shows the relationship while Table 1 shows the state of pins. Table 1. Operating Modes

Figure 29. Operating State Diagram

8.4.1 Normal Mode

8.4.2 Sleep Mode

the respective time periods (tLINBUS). Sleep mode is entered by setting EN low for longer than tMODE_CHANGE. While the device is in sleep mode, the following conditions exist.

The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake up events in case an external connection to the LIN bus is lost.
The normal receiver is disabled.
EN input and LIN wake up receiver are active.

8.4.3 Standby Mode

This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The LIN bus slave termination circuit is turned on when standby mode is entered. Standby mode is signaled through a low level on RXD. See Standby Mode Application Note for more application information. When EN is set high for longer than tMODE_CHANGE while the device is in standby mode, the device returns to normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.

8.4.4 Wake Up Events

There are two ways to wake up from sleep mode:

Remote wake up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN bus where the dominant state is held for tLINBUS filter time. After this tLINBUS filter time has been met and a rising edge on the LIN bus going from dominate state to recessive state initiates a remote wake up event, eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
Local wake up through EN being set high for longer than tMODE_CHANGE.

8.4.4.1 Wake Up Request (RXD)

When the TLIN1022-Q1 encounters a wake up event from the LIN bus, RXD goes low and the device transitions to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal mode, the RXD pin is releasing the wake up request signal and the RXD pin then reflects the receiver output from the LIN bus.

8.4.4.2 Mode Transitions

When the TLIN1022-Q1 is transitioning between modes, the device needs the time, tMODE_CHANGE, to allow the change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep or standby mode to normal mode, the transition time is the sum of tMODE_CHANGE and tNOMINT

Copyright © 2017, Texas Instruments Incorporated(1) If RXD on MCU or LIN slave has internal pullup; no external pullup resistor is needed. (2) If RXD on MCU or LIN slave does not have an internal pullup requires external pullup resistor.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

with the ability to support both remote wake up request and local wake up request.

9.2 Typical Application

device being used in both master and slave applications. Figure 30. Typical LIN Bus

9.2.1 Design Requirements

as per each application requirements.

9.2.2 Detailed Design Procedures

9.2.2.1 Normal Mode Application Note

9.2.2.2 Standby Mode Application Note

that the TLIN1022-Q1 is in standby mode and should be returned to sleep mode for the lowest power state.

9.2.2.3 TXD Dominant State Timeout Application Note

different maximum consecutive dominant bits for each application case and thus different minimum data rates.

9.2.3 Application Curves

recessive and recessive to dominant stated under lightly loaded conditions. Figure 31. Dominant to Recessive Propagation Figure 32. Recessive to Dominant Propagation

10 Power Supply Recommendations

36 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.

11 Layout

In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be applied during PCB design. Placement at the connector also prevents these noisy events from propagating further into the PCB and system.

11.1 Layout Guidelines

Pin 1, 4 (RXD1/2): The pin is an open drain outputs and require an external pull-up resistor in the range of 1 kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the microprocessor.
Pin 2, 5 (EN1/2): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pinto limit current on the digital lines in the event of an over voltage fault.
Pin 6 (NC): Not Connected.
Pin 3, 7 (TXD1/2): The TXD pins are the transmitter input signals to the device from the processor. A series resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.
Pin 8 (GND): This is the ground connection for the device. This pin should be tied to the ground plane through a short trace with the use of two vias to limit total return inductance.
Pin 9, 13 (LIN1/2): This pin connects to the LIN bus. For slave applications, a 220 pF capacitor to ground is implemented. For maser applications and additional series resistor, a blocking diode should be placed between the LIN pin and the VSUP pin. See Figure 30.
Pin 10 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close to the device as possible.
Pin 11, 12 and 14 (NC): Not Connected. NOTE All ground and power connections should be made as short as possible and use at least two vias to minimize the total loop inductance.

11.2 Layout Example

Figure 33. Layout Example

12 Device and Documentation Support

This device will conform to the following LIN standards. The core of what is needed is covered within this system spec, however reference should be made to these standards and any discrepancies pointed out and discussed. This document should provide all the basics of what is needed.

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: LIN Standards:

ISO/DIS 17987-1.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use case definition
ISO/DIS 17987-4.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer (EPL) specification 12V/24V
SAEJ2602-1: LIN Network for Vehicle Applications
LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification EMC requirements:
SAEJ2962-2: TBD
ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband radiated electromagnetic energy - Part 4: Harness excitation methods
ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions and general considerations
ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines
IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4: Direct RF power injection method
IEC 61000-4-2
IEC 61967-4
CISPR25 Conformance Test requirements:
ISO/DIS 17987-7.2: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL) conformance test specification
SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.4 Trademarks (continued)

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 1.800 TLIN1022-Q1 SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SYMM SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED TLIN1022-Q1 www.ti.com SLLSEZ8 –DECEMBER 2017 Product Folder Links: TLIN1022-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE SCALE:8X TLIN1022-Q1 SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

www.ti.com PACKAGE OUTLINE C 14X 0.35 0.25 4.2 0.1 14X 0.45 0.35 3.9 1.6 0.1 12X 0.65

0.9 MAX

0.05 0.00 B 3.1 2.9 A 4.6 4.4 (0.2) TYP

0.1 MIN

(0.05) VSON - 0.9 mm max heightDMT0014A PLASTIC SMALL OUTLINE - NO LEAD 4223033/B 10/2016 PIN 1 INDEX AREA SEATING PLANE 0.08 C 7 8 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM15 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.200 SCALE 30.000SECTION A-A SECTION A-A TYPICAL TLIN1022-Q1 www.ti.com SLLSEZ8 –DECEMBER 2017 Product Folder Links: TLIN1022-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP 14X (0.3) (4.2) (2.8) 12X (0.65) (1.6) ( 0.2) VIA TYP 14X (0.6) (0.69) TYP (0.55) TYP (1.85) VSON - 0.9 mm max heightDMT0014A PLASTIC SMALL OUTLINE - NO LEAD 4223033/B 10/2016 SYMM 7 8 SYMM LAND PATTERN EXAMPLE SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) TLIN1022-Q1 SLLSEZ8 –DECEMBER 2017 www.ti.com Product Folder Links: TLIN1022-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.3) 14X (0.6) (1.47) (1.18) (2.8) (R0.05) TYP 12X (0.65) (1.38) VSON - 0.9 mm max heightDMT0014A PLASTIC SMALL OUTLINE - NO LEAD 4223033/B 10/2016 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 15 77.4% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 7 8 SYMM METAL TYP TLIN1022-Q1 www.ti.com SLLSEZ8 –DECEMBER 2017 Product Folder Links: TLIN1022-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

www.ti.com 23-Dec-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLIN1022DMTRQ1 PREVIEW VSON DMT 14 3000 TBD Call TI Call TI -40 to 125 TLIN1022DMTTQ1 PREVIEW VSON DMT 14 250 TBD Call TI Call TI -40 to 125 TLIN1022DRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 TL022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 23-Dec-2017 Addendum-Page 2

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Product Information

TLIN1022DRQ1 specifications and overview.

Summary

Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout

Description

Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout

Source title TLIN1022DRQ1 Datasheet(PDF) - Texas Instruments

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