TLFD500 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 38
Technical content
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Complies With ITU G.992.2 Standard /C006814-Bit Integrated A/D and D/A Converters /C00681.104 Msps Update Rate for the RX Channel /C0068276 ksps Update Rate for the TX Channel /C0068Minimum 50 dB Missing Tone Rejection for DMT Signals /C0068Integrated TX/RX Filters /C0068Integrated Digital Phase Lock Loop (DPLL) and VCXO DAC /C0068Integrated Equalizer for Receive Channel /C0068Integrated PGA in Receive, and PAA in Transmit Channels /C0068Direct Single Serial Interface to TI’s C54x or C6x DSP (Data and Control) /C0068Eight General-Purpose I/O Pins /C0068Software and Hardware Power-Down Modes /C0068Industrial Temperature Range (–40°C to 85°C) /C0068Integrated Auxiliary Amplifiers for System Flexibility /C0068Single 3.3 V Supply /C006880-Pin LQFP (PN) Package /C00682s Complement Data Format
description
The TLFD500PN is a high-speed analog front end for a remote terminal-side ADSL G.Lite modem. The device is designed to perform transmit encoding (D/A conversion), receive decoding (A/D conversion), transmit and receive filtering functions, and receive equalizer functions for a frequency division multiplex (FDM) G.Lite application. The receive channel has an update rate of 1.104 Msps, while the transmit channel has an update rate of 276 ksps. Both channels use 2s complement data format. When used in a G.Lite system, the TLFD500PN requires a minimum number of external components. The device incorporates integrated filtering, DPLL, VCXO DAC (uses 2s complement data format), and 8 general-purpose I/O ports. The general-purpose I/O ports provide a means of reading or writing status bits in the system. Four auxiliary amplifiers on the chip can be configured (external components may be required) to provide additional onboard filtering and amplification. A simple serial interface for data transfer on the digital side reduces system component count. The interface can be connected directly to the TI C6x and C54x families of DSPs. The TLFD500PN device is available in an 80-pin PN LQFP package. Copyright 2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DVSS_IO DVDD_IO DVDD GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 FSX FSR AMP4OUTP AMP4OUTM NC AMP3OUTP AMP3INM AMP3INP AMP3OUTM AVDD_RX AVSS_RX RXINP RXINM HPF2OUTP HPF2INM HPF2INP HPF2OUTM HPF1OUTP HPF1INM HPF1INP HPF1OUTM VSS 5678 PN PACKAGE (TOP VIEW) VMID_RX 59 58 57 56 5560 54 NC DVSS_RX DVSS_RX DVSS_RX DVSS_RX NC DVSS_RX AMP1INP VCXOCNTL AMP2INM AMP2OUTP TXOUTP TXOUTM AVDD_TX AVSS_TX AMP1OUTP 52 51 5053 9 10 11 12 13 49 48 1AMP2OUTM AVDD_RX 47 46 45 44 14 15 16 17 TXBANDGAP COMPDAC2 COMPDAC1 PWRDN AVDD_REF REFP REFM AVSS_REF AMP4INM AMP4INP SDX SCLK 18 19 20 RXBANDGAP PLLSEL 43 42 41 DVDD_RX AVSS_RX DVSS AMP1INM AMP2INP AMP1OUTM SDR NC – No connection TLFD500PN
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram MCLKIN Serial Interface and Control General Purpose I/O Digital HPF Digital LPF TX DAC TX LPF RX LPF Equalizer+ RX LPF HPF2 HPF1 INTERNAL REFERENCE Clock Generator VCXO DAC External VCXO PAA SCLK SDX SDR FSX FSR TXOUTP/ TXOUTM RXINP/ RXINM HPF2OUTP/ HPF2OUTM HPF2INP/ HPF2INM AMPOUTP/ AMPOUTM HPF1OUTP/ HPF1OUTM HPF1INP/ HPF1INM AMPINP/ AMPINM TXBANDGAP/ RXBANDGAP REFM REFP VMID_RX VCXOCNTL 30 kHz to 138 kHz 30 kHz 138 kHz AUX Amps(4) GPI00–GPI07 138 kHz
14 Bit
4.416 MSPS
0 to –24 dB (–1 dB/step) TX PAA
4.416 MSPS 552 kHz
(0.25 dB/Step) RX PGA3 0 to 18 dB (6 dB/step) RX PGA2 180 kHz 0 to 12 dB (3 dB/Step) RX PGA1 180 kHz
35.328 MHz
NOTE: Refer to Figure 17 for application details.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NAME NO. I/O DESCRIPTION AMP1INP– AMP4INP 11,2,66,59 I Auxiliary amplifier 1–4 positive input AMP1INM– AMP4INM 10,3,65,60 I Auxiliary amplifier 1–4 negative input AMP1OUTP– AMP2OUTP 9,4 O Auxiliary amplifier 1–2 positive output. Outputs are self-biased to AVDD_TX/2. AMP3OUTP– AMP4OUTP 64, 61 O Auxiliary amplifier 3–4 positive output. Outputs are self-biased to AVDD_RX/2. AMP1OUTM– AMP2OUTM 12,1 O Auxiliary amplifier 1–2 negative output. Outputs are self-biased to AVDD_TX/2. AMP3OUTM– AMP4OUTM 67,62 O Auxiliary amplifier 3–4 negative output. Outputs are self-biased to AVDD_RX/2. AVDD_REF 47 I Analog supply for reference circuit AVDD_RX 48,68 I RX channel analog supply AVDD_TX 7 I TX channel analog supply AVSS_REF 44 I Analog supply return for reference(analog ground) AVSS_RX 49,69 I RX channel analog supply return (analog ground) AVSS_TX 8 I TX channel analog supply return (analog ground) COMPDAC1 16 I TX channel decoupling cap input A. Add 1 mF capacitor to AVDD_TX COMPDAC2 15 I TX channel decoupling cap input B. Add 1 mF capacitor to AVDD_TX DGPO 35 O Direct general-purpose output. This pin reflects the last value written to the DGPO bit location in the SDR data stream. It is a general-purpose output that does not require a secondary transfer to control. DVDD 31,39 I Digital power supply DVDD_IO 32 I Digital I/O buffer supply DVDD_RX 51 I RX channel digital supply DVSS 34,40,41 I Digital ground DVSS_IO 33 I Digital I/O buffer supply return (digital ground) DVSS_RX 52,54,55, 56,57 I RX channel digital supply return (digital ground) FSX 22 O Serial port frame sync transmit signal FSR 21 O Serial port frame sync receive signal GPIO0–GPIO7 23–30 I/O General-purpose I/O HPF1INP 78 I RX channel stage 1 amplifier positive input. Input signal needs to have AVDD_RX/2 common mode voltage. HPF1INM 77 I RX channel stage 1 amplifier negative input. Input signal needs to have AVDD_RX/2 common mode voltage. HPF2INP 74 I RX channel stage 2 positive input. Input signal need to have AVDD_RX/2 common mode voltage. HPF2INM 73 I RX channel stage 2 negative input. Input signal need to have AVDD_RX/2 common mode voltage. HPF1OUTP 76 O RX channel stage 1 amplifier positive output. Used to connect external components to obtain stage 1 HPF. HPF1OUTM 79 O RX channel stage 1 amplifier negative output. Used to connect external components to obtain stage 1 HPF. HPF2OUTP 72 O RX channel stage 2 positive output. Output signal has AVDD_RX/2 common mode voltage. HPF2OUTM 75 O RX channel stage 2 negative output. Output signal has AVDD_RX/2 common mode voltage. MCLKIN/PLLCLKIN 37 I Multiplexed pin based on value of PLLSEL. Selects master clock input, or clock input for PLL mode.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION NC 36,53, 58, No connection. Keep floating. PLLSEL 42 I Selects between VCXO mode and DPLL mode. If the pin is tied high PLL mode is selected. Pin should be tied low for VCXO mode. Cannot be left floating. PWRDN 17 I Power-down pin. When PWRDN is pulled low the device goes into power-down mode. The default state of this pin is low. REFM 45 O Negative reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 mF (tantalum) and 0.1 mF (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 0.5 V. REFP 46 O Positive reference filter node. This terminal is provided for low-pass filtering of the internal band-gap reference. The optimal ceramic capacitor value is 10 mF (tantalum) 0.1 mF (ceramic), connected to analog ground. The nominal dc voltage at this terminal is 2.5 V. RESET 38 I Device reset input pin. Initializes all the device’s internal registers to their default values. The default state of this pin is low. RXBANDGAP 43 O RX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 mF (tantalum) and 0.1 mF (ceramic). This node should not be used as a voltage source. RXINP 70 I RX channel stage 3 positive input. The input is self-biased at AVDD_RX/2. RXINM 71 I RX channel stage 3 negative input. The input is self-biased at AVDD_RX/2. SCLK 19 O Serial port shift clock (transmit and receive) SDR 20 I Serial data receive from DSP SDX 18 O Serial data transmit to DSP TXBANDGAP 14 O TX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V band-gap reference. The optimal capacitor value is 10 mF (tantalum) and 0.1 mF (ceramic). This node should not be used as a voltage source. TXOUTP 5 O TX channel positive output TXOUTM 6 O TX channel negative output VCXOCNTL 13 O DAC output to control onboard VCXO VMID_RX 50 I/O Decoupling Vmid for ADC. Add 10 mF (tantalum) and 0.1 mF (ceramic) capacitors to analog ground. VSS 80 I Substrate. Connect to analog ground. detailed description transmit The transmit channel is powered by a high performance DAC. The transmit channel update rate is 276 kHz. The DAC is a 14-bit DAC at 4.416-MHz. This provides 16X oversampling. A band-pass filter limits the output of the transmitter to a frequency range of 30 kHz to 138 kHz. A differential amplifier drives the output into the external line driver. The differential amplifier has programmable attenuation for added flexibility. The transmitter high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (BCR). The output spectrum of the DAC complies with the nonoverlapped power spectrum density (PSD) mask specified in the ITU draft recommendation G.992.2 for G.Lite. The TXPAA is a programmable-attenuation amplifier. It provides 0 dB to 24 dB of attenuation in1-dB steps. The TXPAA is controlled via the PAA control register (PCR). For details about register programming see the register programming section.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued) receive The receive channel consists of a high-pass filter, a programmable gain amplifier, an ADC, and filters. In addition, it has an equalizer to attain maximum system performance. The input of the receiver is fully differential. The ADC in the receive channel is a 14-bit converter which samples at 4.416 Msps for 4X oversampling. An on-chip decimator reduces the sampling frequency to 1.104 MHz. The low pass filtering of the receive channel limits the converted data to frequencies below 552 kHz. The high-pass analog filter is used to reject the near-end echo to maximize the dynamic range of the ADC. The high-pass filter consists of two stages: (1) a second order high-pass filter (HPF1) and, (2) a third order elliptic high-pass filter (HPF2). Both stages have a cutoff at 180 kHz. The filter is divided into two stages to minimize the noise from a single stage being amplified throughout. Together, the two high-pass filters typically attenuate the echo power by 30 dB. There is a programmable gain amplifier (PGA) between the two filters for coarse gain adjustments of 0-dB –12-dB in 3-dB steps. After the high-pass filter stage, the receiver channel has a 0-dB –18-dB PGA that can be adjusted in 6-dB steps. HPF2 and PGAs are integrated in one block. Figure 1(a), 1(b), and 1(c) show the frequency response of HPF1 and HPF2 (with PGAs). The PGA is followed by a 552-kHz low-pass filter with a programmable 25-dB/MHz slope (5-dB/MHz step) equalizer incorporated. After the equalizer, there is a fine-gain adjustment PGA of 0-dB to 9-dB in 0.25-dB steps. All the RX PGAs are controlled via the PGA control registers (PCR–RX1 and PCR–RX2). See the register programming section for details about register programming.
Figure 1. RX Stage HPF1 and HPF2 Frequency Response use of 16 bits to obtain a 12-bit number. register is updated. VCR-L[7:4] must always be zero.
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MHz) goes to a programmable frequency divider to generate sampling clock for the ADC and DAC converters. will enable the DPLL mode. Refer to DPLL section for detail. clocks generated are produced from the CLKIN signal. 3.3-V supply, 35.328 MHz ±50 PPM center frequency, and input control voltage range of 0 V–3 V. The recommended duty cycle is 50/50. at the same speed, there is no fixed phase relationship between them. connection diagram is shown in Figure 2. Figure 2. Typical Serial Port Connection and example data transfers are shown in Table 1.
Table 1. SDR LSB Control Function
0 No secondary transfer requested
1 Secondary transfer requested
a 1 is written to this bit, the host is requesting a secondary data transfer. Figure 3. Primary Transfer Data Bit Mapping D10–D14. The eight bits of SDX always reflect the status of GPI00–7. D0–D7 on SDX will be all zeroes.
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1 A4 A3 A2 A1 A0
0 A4 A3 A2 A1 A0
Figure 4. Secondary Transfer Data Bit Mapping
- FS is set high and remains high during one SCLK period, then returns to low.
- A 16-bit word is transmitted from the ADC (SDX), and a 16-bit word is received for DAC conversion (SDR).
Figure 6(a) and 6(b) shows the timing relationship with secondary request.
input buffer delay (for SDR) to around 17 ns. As a consequence the SDR data can not be latched at the negative edge of SCLK. Figure 5. Data Transfers
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
48 SCLKs
16 SCLKs
128 SCLKs
32 SCLKs
Figure 6. Data Transfers
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) general purpose I/O port (GPIO) The general-purpose I/O port provides eight input/output pins and one output-only pin for control of external circuitry, or for reading the status of external devices. The eight input/output pins are labeled GPIO0 –GPIO7. The output-only pin is labeled DGPO (direct general-purpose output). This pin is labeled as direct because a secondary transfer is not required to write to this pin. The GPIO pins are controlled and read in the GPR-D register. The GPR-C register is used to configure the GPIO pins as input or output pins. The default reset condition is 11111111b, indicating that all are configured as inputs. For further details on register programming see the register programming section. The DGPO pin does not need configuring and is controlled by the D1 bit in the SDR data stream (that is, from the DSP to the TLFD500PN) during primary data transfers. In addition, a secondary transfer is not required to read GPIO0 and GPIO1 when they are configured as inputs. Their values can be mapped into the lower two bits of the SDX data stream (that is, from TLFD500PN to DSP) during primary data transfers. To map the values of GPIO0 and GPIO1 into the lower two bits of the SDX ADC data stream, set the appropriate bit in the MCR register. For more flexibility, the values of GPIO0 – GPIO7 are mapped into the upper eight data bits of the SDX data stream on secondary data transfers. This allows the host processor to read the values of the GPIO pins and the contents of another control register during the same secondary data transfer. When a GPIO pin is being configured as an output, its corresponding status bit in the SDX data stream will be the last value written to the output pin. Each output is capable of driving 2 mA. reference system The integrated reference provides voltage and current to the internal analog blocks. It is also brought out to external pins for noise decoupling. They should not be used as dc voltage source. When the internal reference is being used by the device, the device may be powered down by writing the appropriate reference control bit in the main control register (MCR) to achieve power savings during periods of device inactivity. auxiliary amplifiers Four auxiliary high-performance operational amplifiers on the chip allow for additional onboard filtering and amplification with minimal component count. Each op-amp has differential inputs and outputs, with 2 input pins and 2 output pins. Each op-amp can be enabled by register programming. The typical specifications for the operational amplifiers are as follows: DC Gain: 126 dB Bandwidth: 116 MHz PSRR: 100 dB at dc, 70 dB at 1 MHz, and 40 dB at 4 MHz Output common-mode: AVDD_RX/2 (auxiliary amplifier 3,4) or AVDD_TX/2 (auxiliary amplifier 1,2) Input interface: AC coupled device power-up sequence All digital and analog supplies must be properly biased. All supply pins are mandatory. The power supply can not be switched, even when the codec has been powered down or parts of the codec are in power-down mode. Reset must be held at least 20 ms after power up. To reset the reference circuit and registers requires 100 ms. When the chip is woken up from hardware power-down mode, it takes100 ms to reset the reference circuit before the chip works in normal mode. When the chip is woken up from software power-down mode, only 20 ms is needed before valid data comes out (reference must be kept on). Register values will not change in either wake-up operation.
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The codec registers are listed in Table 2, with each bit of each register defined. All registers are 8-bit wide. is not guaranteed. During a write, only zeroes can be written to reserved bits. Table 2. Codec Registers VCR-M 00110 R/W D[7:0] = VCXO DAC control Bit[11:4]. VCR-L 00111 R/W D[3:0] = VCXO DAC control Bit[3:0]. D[7:4] must always be zero. Reserved 01010 R/W For future use. Read or write of register not allowed.
Table 3. EQR Bit Definition data buffer and does not exercise the RX or TX channel.
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 4. PCR-RX1 Gain
Table 4. PCR-RX1 Gain (Continued) Similarly one can compute the RXPGA3 [5:0] bit combination needed, given the gain in dB. will saturate to a maximum or minimum value or wrap around to a valid combination.
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 5. PCR-RX2 Gain Similarly the needed RXPGA2[1:0] bit combination can be computed, given the gain in dB.
- The formula to convert bit value to RXPGA1 gain in dB is
Similarly the needed RXPGA1[2:0] bit combination can be computed, given the gain in dB. will saturate to a maximum or minimum value or wrap around to a valid combination.
Table 6. PCR-TX Attenuation Similarly one can compute the TXPAA[4:0] bit combination needed, given the attenuation in dB. will saturate to a maximum or minimum value or wrap around to a valid combination.
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 7. EQR Slope and Gain Similarly one can compute the EQPGA[2:0] bit combination needed, given the gain in dB.
- The formula to convert bit value to EQ slope in dB is
Similarly one can compute the EQ[2:0] bit combination needed, given the slope in dB/MHz. will saturate to a maximum or minimum value or wrap around to a valid combination.
Table 8 shows some representative analog outputs. Table 8. Representative Analog Outputs Where step–size, D = (3/4095) V. if 0x539 is desired, VCR-M and VCR-L should be set to 0x53 and 0x09.
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 9. GPR-C Direction Control NOTE 8: A particular GPIOC control bit configures direction for the corresponding GPIOD data bit. GPIOD[7:0] corresponds to pins GPIO7–GPIO0 respectively.
Table 10. Auxiliary Amplifier-Control combinations should not be used. The default condition is with the amplifiers switched off. Table 11. NCO Default Value Table
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 12. NCO Default Value NOTES: 9. The formula to convert NCDLY[7:0] to delay is straightforward. Delay (number of ADCLK periods) = NDCLK[7:0] (except for 0 and 1).
- ADCLK–A/D converter sampling clock
its value. All the others store them unless RESET.
- NCDEF[7:0] = 64 (dec.), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 5. This shows a default division
samples. The jitter will take effect 5 ADCLK sample periods after writing to NCDLY .
- NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 0, NCRPT[2:0] = 2, NCDLY[7:0] = 5. Here the jitter will not be
observed, since the delta register is zero.
- NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 0, NCDLY[7:0] = 5. Here the jitter will not be
observed, since the repeat register is zero.
- NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2, NCDLY[7:0] = 0. This is invalid and not
recommended. NCDLY[7:0] can not be 0 or 1.
- NCDEF[7:0] = 64 (decimal), NCDEL[4:0] = 1, NCRPT[2:0] = 2. Here the jitter will not occur since there was
not writing to NCDLY . The other registers will retain their values as in all other cases.
Table 13. NCO_DELTA – DELTA and REPEAT
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 14. MCR Control Show GPIO 1 and 2 in SDX primary. done by forcing pin logic levels.
- Analog loop-back means looping back of the analog TX output to the RX input. This way the codec can be tested without need of
- Digital loop-back means looping back the digital RX output to the TX input. Here we can test the code without the need for a DSP
All power downs of VCXODAC, RX, and TX channels occur with the reference still on. phase shift. The ratio is controlled by the DSP through register programming.
Figure 7. DPLL Internal Function Block Diagram NCO_DIV_DELAY is needed if further adjustment is required. used in the VCXO mode) and the DAC clock will continue to work at 4.416 MHz.
16 SCLKs 16 SCLKs 16 SCLKs 16 SCLKs
2 ADCLK Over Jitter is Done
1 ADCLK Over
Figure 8. ADCLK Jitter Example
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
no-toggle zone varies with the ADCLK. Figure 9 illustrates an example.
2.208 MHz
4.416 MHz
Figure 9. Relation of SCLK With ADCLK/DACLK in DPLL Mode implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (continued) clock MIN NOM MAX UNIT Input clock frequency 35.328 MHz Input clock duty cycle 50% electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX =
3.3 V, (unless otherwise noted)
TX channel (measured differentially) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gain error –1.5 1.5 dB PAA step gain error ±0.25 dB DC offset 50 100 mV Cross-talk RX to TX channel –70 dB Idle channel noise 65 mVrms Group delay 30 ms Power supply rejection ratio (PSRR) 200 mVp-p at 75 kHz 70 dB Analog output voltage Load = 2000 W 3 Vp-p AC Performance SNR Signal-to-noise ratio 70 dB THD Total harmonic distortion ratio 70 kHz at –1 dB (see Note 14) 75 dB TSNR Signal-to-noise + harmonic distortion ratio 68 dB 30.1875 kHz –71 MT Missing-tone test (see Note 15) 81.9375 kHz –71 dB 129.375 kHz –71 Channel Frequency Response (Refer to Figure 13) 30 kHz –1.5 1.5 Filter gain relative to gain at 77.625 kHz Pass-band (ripple) –1 1 dB 180 kHz –70 NOTES: 14. The input signal is the digital equivalent of a sine wave (digital full scale = 0 dB). The normal differential output with this input condition is 3 Vpp. 15. 27 tones, 25.875 to 138 kHz, 4.3125 kHz/step, 0 dB reference outputs MIN NOM MAX UNIT REFP 2.2 2.5 2.8 V REFM 0.3 0.5 0.7 V TXBANDGAP AVDD_REF = 3.3 V 1.4 1.5 1.6 V RXBANDGAP 1.4 1.5 1.6 V VMID_RX 1.5 V digital outputs MIN NOM MAX UNIT VOH High-level output voltage IOH = 2 mA 2.4 V VOL Low-level output voltage IOL = –2 mA 0.6 V
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX =
3.3 V, (unless otherwise noted) (continued)
RX channel (measured differentially) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gain error –1.5 1.5 dB PGA 1 (0 to 12 dB in 3-dB steps) ±1 PGA step gain error PGA 2 (0 to 18 dB in 6-dB steps) ±1 dB PGA 3 (0 to 9 dB in 0.25-dB steps) ±0.15 DC offset 50 100 mV Cross-talk TX to RX channel –55 dB Group delay 25 ms Idle-channel noise 100 mVrms Common-mode rejection ratio (CMRR) 70 dB Power supply rejection ratio (PSRR) 200 mVp-p at 75 kHz 70 dB Analog input self-bias dc voltage 1.5 V RXINP/M 7 kW Input impedance HPF1INP/M 70 pF HPF2INP/M 70 pF AC Performance SNR Signal-to-noise ratio 72 THD Total harmonic distortion ratio 270 kHz at –1 dB (see Note 16) 82 dB TSNR Signal-to-noise + harmonic distortion ratio 72 163.875 kHz –57 MT Missing-tone test (see Note 17) 301.875 kHz –57 dB 508.875 kHz –57 Channel Frequency Response (EQ[2:0] = 0 dB/MHz) (Refer to Figures 15 and 16) 180 kHz –1.5 1.5 Filter gain relative to gain at 276 kHz Pass-band (ripple) –1 1 dB 800 kHz –25 NOTES: 16. The analog input test signal is a sine wave with 0 dB = 3 Vp-p as the reference level. 17. 123 tones, 25.875 kHz to 552 kHz, 4.3125 kHz/step, –6 dB.
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, fMCLKIN = 35.328 MHz, AVDD_RX/AVDD_TX/AVDD_REF = 3.3 V, DVDD = DVDD_IO = DVDD_RX = PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bits DNL Differential nonlinearity ±1 LSB INL Integral nonlinearity ±4 LSB Monotonicity 12 Bits Channel gain error dB Offset error –100 100 mV Analog Output Full scale output voltage Load = 50 kW, VDD = 3.3 V 3 V Output load 50 kW power dissipation MIN TYP MAX UNIT Active mode 700 850 mW Hardware power down 50 100 mW Power dissipation Power down mode TX only Pow er-dow n mode Software power down RX only mW TX + RX + Reference
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 10. Data Transfers From DSP to TLFD500PN Figure 11. Data Transfers From TLFD500PN to DSP
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Figure 14. Transfer Characteristic of the Transmit Filters With HP Filter Bypassed Figure 15. Transfer Characteristic of the Receive Filters (including out of band 0–1.6 MHz)
Figure 16. Transfer Characteristic of the Receive Filters (in-band 0–0.6 MHz)
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
5 TXOUP
DVDD 31, 39 0.1 mF VCXOCNTL 13 RESET 38 PWRDN 17 PLLSEL 42 MCLKIN/PLLCLKIN 37 GPIO0-GPIO7 23-30 DGPO 35 Input signal need to have AVDD_RX/2 common mode voltage DVDD_RX 51 DVDD_IO 18 VSS 80 AVSS_REF 44 AVSS_TX 8 AVSS_RX 49 AVSS_RX 69 Analog Ground AVDD_REF 47 AVDD_RX 48 AVDD_RX 68 AVDD_TX 7 Analog Power Supply mF 1.0 mF 1.0 mF Analog Power Supply Analog Ground
6 TXOUM
70 RXINP
71 RXINM
75 HPF2OUTM
72 HPF2OUTP
74 HPF2INP
79 HPF1OUTM
76 HPF1OUTP
77 HPF1INM
78 HPF1INP
73 HPF2INM
0.1 mF 0.1 mF 0.1 mF 0.1 mF
16 COMPDAC1
15 COMPDAC2
50 V MID_RX
14 TXBANDGAP
43 RXBANDGAP
45 REFM
46 REFP
DVSS 34,40,41 DVSS_IO 33 DVSS_RX 52,54,57 Digital Ground FSX 22 FSR 21 SDR 20 SCLK 19 SDX 18 Digital Interface to DSP Figure 17. Typical Application Circuit
3.3 V INTEGRATED G.LITE ANALOG FRONT END SLAS207B – JUNE 1999 – REVISED MAY 2000 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 4040135 /B 11/96 0,17 0,27 0,13 NOM 0,25 0,45 0,75 0,05 MIN Seating Plane Gage Plane 4160 SQ SQ 13,80 14,20 12,20 9,50 TYP 11,80 1,45 1,35 1,60 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated