TLF50281EL

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Rev. 1.01, 2013-04-30 TLF50281EL

2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current

Data Sheet 2 Rev. 1.01, 2013-04-30 TLF50281EL Table of Contents Table of Contents

TLF50281EL PG-SSOP-14 TLF50281 PG-SSOP-14 Data Sheet 3 Rev. 1.01, 2013-04-30

2.2 MHz Step-Down Regulator 500 mA, 5 V

• 500 mA step down voltage regulator
• 5 V Output voltage
• ± 2% output voltage tolerance
• Low quiescent current (less than 45µA at nominal battery voltage)
• Integrated power transistor
• Current mode PWM regulation
• PFM mode for light load current
• Input voltage range from 4.75V to 45V
• 2.2 MHz switching frequency
• 100% Duty cycle
• Synchronization input
• Very low shutdown current consumption (<2 µA)
• Soft-start function
• Reset generator
• Watchdog
• Input undervoltage lockout
• Suited for automotive applications: Tj = -40 °C to +150 °C
• Green Product (RoHS compliant)
• AEC Qualified

Description

The TLF50281EL is a high frequency PWM step-down DC/DC converter with an integrated PMOS power switch, packaged in a small PG-SSOP-14 with exposed pad. The wide input voltage range from 4.75 to 45 V makes the TLF50281EL suitable for a wide variety of applications. The device is designed to be used under harsh automotive environmental conditions. The switching frequency of nominal 2.2 MHz allows the use of small and cost-effective inductors and capacitors, resulting in a low, predictable output voltage ripple and in minimized consumption of board space. In light load condition the device operates in Pulse Frequency Modulation (PFM) to optimize the efficiency. Between the single pulses, all internal controlling circuitry is switched off to reduce the internal power consumption.

Data Sheet 4 Rev. 1.01, 2013-04-30 TLF50281EL Overview The TLF50281EL includes protection features such as a cycle-by-cycle current limitation, over-temperature shutdown and input under voltage lockout. The enable f unction, in shutdown mode with less than 2 µA current consumption, enables easy power management in battery-powered systems. The voltage regulation loop provides an excellent line and load regulation, t he stability of the loop is ensured by an internal compensation network. This compensation network combined with a current mode regulation control guarantees a highly effective line transient rejection. Du ring start-up the integrated soft-start limits the inrush current peak and prevents from an output voltage overshoot.

Data Sheet 5 Rev. 1.01, 2013-04-30

2 Block Diagram

5 FREQ

INT. SUPPLY 2WO

6 RTADJ

4 SYNC

N.C.

Data Sheet 6 Rev. 1.01, 2013-04-30 TLF50281EL Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration

3.2 Pin Definitions and Functions

Provides the reset output signal. Open collector output, connect a pull up resistor to VCC or another voltage source, if feature is used, if not, leave open. Might be connected in parallel with pin WO, if necessary. 2W O Watchdog Output Provides the watchdog output signal. Open collector output, connect a pull up resistor to VCC or another voltage source, if feature is used, if not, leave open. Might be connected in parallel with pin RO, if necessary. 3W I Watchdog Input Connect Watchdog Input signal, if feature is used. If not used, connect to GND 4S Y N C Synchronization Input Connect to an external clock signal in order to synchronize/adjust the switching frequency. This feature is not functionally in PFM mode. 5F R E Q Frequency Adjustment Pin Connect an external resistor to GND to adjust the switching frequency, do not leave open. In case the synchronization option is used, the resistor must be dimensioned close to the desired synchronization frequency. 6R T A D J Reset Threshold Adjust Pin Connect an external resistor divider to adjust the Reset threshold. If function is not used, connect to VCC . 7F B Feedback Input Connect this pin directly to the output capacitor. Also input for internal power supply. The internal power supply is taken from the output voltage. WO N.C.WI SWO EN 2 13 1 14 SYNC TLF50281ELRO GND5FREQ 6RTADJ 7FB GND WMSEL8 PG-SSOP14 VS

Data Sheet 7 Rev. 1.01, 2013-04-30 8W M S E L Watchdog Mode Select Pin Connect to VCC for Watchdog slow mode or to GND for Watchdog fast mode. If not used, connect to GND to avoid EMC related influence to Watchdog function. 9G N D Ground Connect this pin directly with low inductive and broad trace to ground, do not leave open.

10 GND Ground

Connect this pin directly with low inductive and broad trace to ground, do not leave open.

11 SWO Buck Switch Output

Drain of the integrated power-PMOS transistor. Connect directly to the cathode of the catch diode and the buck circuit inductance. 12 N.C. Not Connected. Internally not connected. Leave open or connect to GND.

13 VS Supply Voltage Input

Connect to supply voltage source.

14 EN Enable Input

Switch to high level to enable the device, switch to low level to disable the device. Exposed Pad Connect to heatsink area and GND by low inductance wiring. Pin Symbol Function

Data Sheet 8 Rev. 1.01, 2013-04-30 TLF50281EL General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings1) Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) 1) Not subject to production test, specified by design Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. Voltages

4.1.1 Enable input VEN -40 45 V –

4.1.2 Synchronization input VSYNC -0.3 5.5 V – 4.1.3 6.2 V t < 10s 2) 2) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001. 4.1.4 Frequency adjustment pin VFREQ -0.3 5.5 V – 4.1.5 6.2 V t < 10s 2) 4.1.6 Watchdog input VWI -0.3 5.5 V – 4.1.7 6.2 V t < 10 2) 4.1.8 Watchdog output VWO -0.3 5.5 V – 4.1.9 6.2 V t < 10s 2) 4.1.10 Watchdog mode selection pin VWMSEL -0.3 5.5 V – 4.1.11 6.2 V t < 10s 2) 4.1.12 Reset threshold adjust pin VRTADJ -0.3 5.5 V – 4.1.13 6.2 V t < 10s 2) 4.1.14 Reset output VRO -0.3 5.5 V – 4.1.15 6.2 V t < 10s 2) 4.1.16 Feedback Input VFB -0.3 5.5 V – 4.1.17 6.2 V t < 10s 2) 4.1.18 Buck switch output VSWO -2.0 VVS + 0.3 V – 4.1.19 Supply voltage input VVS -0.3 45 V – Temperatures

4.1.20 Junction temperature Tj -40 150 °C–

4.1.21 Storage temperature Tstg -55 150 °C–

4.1.22 ESD resistivity VESD -2 2 kV HBM

4.1.23 ESD resistivity to GND VESD -500 500 V CDM 3)

3) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1

4.1.24 ESD resistivity corner pins to GND VESD -750 750 V CDM 3)

General Product Characteristics Data Sheet 9 Rev. 1.01, 2013-04-30 Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

4.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal Resistance

Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. 4.2.1 Supply voltage VS 4.75 45 V – 4.2.2 Buck inductor LBU 3.3 22 µH –

4.2.3 Buck capacitor CBU1 10 50 µF –

4.2.4 Buck capacitor ESR ESRBU1 0.015 0.100 Ω – 1) 1) See section “ “Application Information” on Page 31” for loop compensation requirements and refer to Application Note for dimensioning the output filter.

4.2.5 Junction temperature Tj -40 150 °C–

Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

4.3.1 Junction to case 1)

1) Not subject to production test, specified by design. RthJC –1 0 –K / W –

4.3.2 Junction to ambient 1) 2)

2) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board. RthJA –4 7 –K / W 2 s 2 p

4.3.3 RthJA – 54 – K/W 1s0p + 600 mm 2

4.3.4 RthJA – 64 – K/W 1s0p + 300 mm 2

Data Sheet 10 Rev. 1.01, 2013-04-30 TLF50281EL Buck Regulator

5 Buck Regulator

5.1 Description

The TLF50281EL is a monolithic current mode step do wn converter with adjustable switching frequency fOSC. It is capable to operate either in Pulse Width Modulation (PWM) or in Pulse Frequency Modulation (PFM) Mode.

5.1.1 Regulator Loop

Power stage: The supply voltage is connected to pin VS. Between pin VS and pin SWO there is an internal shunt resistor and the internal PMOS power stage. The PMOS is driven by the driver stage. Regulator Block: The feedback signal VFB is connected to pin FB. Between pin FB and pi n GND is an internal resistor divider. An error amplifier and a comparator are connected to this resistor divider: The error amplifier EA-gmV, which is controlling the output voltage in PWM mode, and the PFM comparator, which will switch the TLF50281EL into PFM mode and trigger the pulses. The error amplifier EA-gmV is connected to the PWM comparator. The regulation loop operates in current mode: The output current of EA-gm V is subtracted from the sum of the current loop CS- gmI and the slope compensation ISLOPE. The result is evaluated by PWM Comp (a current comparator). The output of PWM Comp defines duty cycle (pulse-width-modulated signal) in PWM mode. The Slope Compensation added to the signal from the error amplifier EA-gmV to the PWM Comparator ensures that no sub harmonics will occur on the input current. The PWM comparator output and the PFM comparator output are connected to the PWM /PFM logic. An external resistor at pin FREQ is required to set the switching frequency (for details please refer to chapter 8 Module Oscillator). The TLF50281EL may also be synchronized to an external frequency. In this case an external clock signal should be connected to pin SYNC. The frequency setting resistor at pin FREQ is still necessary, it has to be selected according to the desired synchron ization frequency (for details please refer to Chapter 8, Oscillator. The TLF50281EL can only be synchronized to an external frequency source in PWM mode, this function does not work in PFM mode. The clock manager is clocking the PWM/PFM logic. The PWM/PFM logic is triggering the driver to apply pulses to the internal PMOS power stage. Safety Features: The shunt resistor in line with the internal PMOS power stage (between pin VS and the power stage) is connected to a current sense amplifier CS-gml. It detects the voltage above the shunt resistor. The amplifier creates a signal which shuts the pulse down in case that the shunt voltage exceeds the reference limit. The current limitation acts as a cycle-by-cycle limitation. Cycle-by -cycle limitation means, t hat every pulse is switched off as soon as the current through the PMOS exceeds the buck peak over current limit IBUOC. The next pulse starts and will also be switched off as soon as the current limit is exceeded a gain. This results in a lowe red output voltage whilst the output current is limited to a certain value.

Data Sheet 11 Rev. 1.01, 2013-04-30 Input undervoltage shutdown: If the input voltage is below the input undervoltage shutdown threshold VS,off the device will shut down. Output overvoltage protection: If the output voltage exceeds the PFM threshold the device will switch from PWM to PFM. Pulses will then be generated only depending on the value of the output voltage VCC. Soft start function: An integrated soft start function of duration tstart ensures, that the inrush current will be limited. After an over-temperature shutdown the regulator always restarts with a soft start. Over-temperature shutdown: An internal temperat ure sensor detects the temperat ure of the device. It will be switched off if the junction temperature exceeds the over temperature shutdown threshold Tj,sd and restart with a certain hysteresis Tj,sd_hyst (for details please refer to Chapter 7, Enable and Thermal Shutdown). Biasing: The internal biasing is taken from pin VS as well as from pin FB (connected to VCC) (for details please refer to Chapter 7, Enable and Thermal Shutdown ). Thus the power consumption from the supply voltage VS can be minimized. Figure 3 Block Diagram Buck Regulator Driver CS-gmI EA-gmV PWM PFM Logic Clock Manager PWM Comp SoftStart GateD VS SWO FB FREQ SYNC_IN GND PFM Comparator Slope Comp. VBG CLK CK_A

Data Sheet 12 Rev. 1.01, 2013-04-30 TLF50281EL Buck Regulator

5.1.2 PWM (Pulse Widt h Modulation) Mode

Under normal condit ions the TLF50281EL will operate wit h a constant swit ching frequency fOSC in PWM mode. The ratio between switch-on-time TON and switch-off-time TOFF is mainly determined by the ratio between the input voltage VS and the output voltage VCC and is influenced by the output current ICC. In PWM mode the device may operate with 100% duty cycl e, in this case the inte rnal PMOS is constantly conducting current. The current limitation feature is operating under this condition. If the switch-on-time TON should theoretically be below the minimum threshold TON,min (due to low load or due to the ratio between input voltage VS and output voltage VCC depending on the switching frequency), it will be reduced to the minimum value switch-on-time TON,min and stay there. As a cons equence the output voltage VCC will increase. The PFM comparator detects the PFM threshold and will then switch the device into PFM mode. There is no possibility to disable the PFM function.

5.1.3 PFM (Pulse Fre quency Modulation) Mode

To optimize the efficiency and to reduce the current consumption, the TLF50281EL automatically switches to PFM mode under low load conditions. In PFM mode the internal power stage including the driver stage is switched off and will only be switched on for applyi ng pulses to charge the output capacitor. The pulses will be created by monitoring the voltage of the output filter capacitor COUT. Thus in PFM mode the repetition time of pulses depend on the output current and/or the ratio between input voltage VS and output voltage VCC. Transition from PWM to PFM: Figure 4 is showing the transition from Pulse Width M odulation to Pulse Frequency Modulation under the assumption, that the input voltage VS will be constant and only the output current ICC will vary. The diagram shows the principle, in reality the signals mi ght look slightly different. The diagram is without scale in respect of time, voltage and current values. Starting from left of the figure a certain output current, here named i1, is applied to the regulator output. This results in a duty cycle D1 with the on-time TON1 of the internal power stage. The switching frequency fOSC is constant as set by the frequency setting resistor RFREQ. The regulator is in PWM mode, the output voltage is VREF_PWM which is equal to VFB in PWM mode. At point t1 the output current decreases from i1 to a lower i2. This results in a duty cycle D2 with the on-time TON2 of the internal power stage. Due to the reduced output load the on-time TON2 is shorter (the regulator is in Discontinuous Conduction Mode DCM) than TON1. The switching frequency fOSC is constant as set by the frequency setting resistor RFREQ. The regulator is still in PWM mode, the output voltage is VREF_PWM which is equal to VFB in PWM mode. In Continuous Conduction Mode CCM the variation from TON1 to TON2 will be very small due to smaller conduction losses. At point t2 the output current decreases again from i2 to a lower i3. As a consequence the on-time TON will be reduced also. The output current i3 is so low, that the on-time TON3 would be smaller than the TON,min. The regulator does not allow a on-time smaller than TON,min. Therefore we can say that the output current i3 is under the imaginary current threshold for transition from PWM to PFM iPWM/PFM. With the pulse staying at on-time TON,min the output voltage VCC will rise. The regulator is still in PWM mode, but the output voltage rises.

Data Sheet 13 Rev. 1.01, 2013-04-30 At point t3 after a normal time period TPWM as adjusted by the frequency setting resistor RFREQ, a further pulse of the duration TON,min is applied, the output voltage VCC keeps on rising. The regulator is still in PWM mode. At point t4 the output voltage VCC touches (or exceeds) the voltage thre shold for transition from PWM to PFM VPWM/PFM. The regulator is now switching in ternally from PWM to PFM. In PF M mode the power consumption of the internal blocks is reduced. The reference for the output voltage VCC is switched from VREF_PWM (which is equal to VFB in PWM mode) to VREF_PFM (which is equal to VFB in PFM mode). The reference for VFB in PFM mode is higher than the reference in PWM mode to avoid voltage dumps at the output voltage VCC due to sudden load steps and to give the regulator more reaction time to switch back to PWM mode. The regulator is now in PFM mode, the output voltage is VREF_PFM which is equal to VFB (or slightly higher) in PFM mode. The output voltage VCC is monitored and as soon as it touches the PFM reference voltage VREF_PFM a pulse of the on-time TON,min is triggered. The time between two pulses is depending on the discharging of the output capacitor COUT. Figure 4 PWM to PFM Transition (Timing Diagram) time Output current time Switching signal time Output voltage iPWM/PFM D1 D2 TPWM TPWM t1 t2 t3 t4 VREF_PWM VREF_PFM VPWM/PFM Switch to PFM mode TON1 TON2 TON,min TPWM

Data Sheet 16 Rev. 1.01, 2013-04-30 TLF50281EL Buck Regulator

5.2 Electrical Characteristics

Electrical Characteristics: Buck Regulator VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

7 V < VS < 12V

100 mA < ICC < 610 mA PWM Mode 10V < VS < 35V ICC = 100 µA PFM Mode 5.2.3 Power sta ge on-resistance Ron –1 . 5 2 . 3 Ω tested at 100 mA, VS = 7.0V 5.2.4 Buck peak over current limit IBUOC 0.85 – 1.7 A –

5.2.5 Current transition rise/fall time tR – 100 – mA/ns 1)

1) Specified by design. Not subject to production test.

5.2.6 Maximum duty cycle Dmax –– 1 0 0 % 2)

2) Consider “ Chapter 4.2, Functional Range”.

5.2.7 Minimum switch on-time TON,min –1 0 0 – n s 1)

5.2.8 Minimum switch off- Time TOFF,min –2 0 0 – n s 1) PFM mode

5.2.9 Soft start ramp tstart 300 450 750 µs VFB rising from 5% to

95% of VFB,nom

5.2.10 Input under voltage shutdown

VS,off 3.75 – – V VS decreasing 5.2.11 Input voltage startup threshold VS,on – – 4.75 V VS increasing

5.2.12 Input under voltage shutdown

VS,hyst 130 300 – mV –

5.2.13 Voltage thres hold for transition

VPWM/PFM –– 5 . 3 V 1)

5.2.14 Frequency ratio for transition from

–1 . 2 0 – – 1)

Data Sheet 17 Rev. 1.01, 2013-04-30

5.3 Performance Graphs

Typical Performance Characteristics Load Regulation PWM Mode VS = 12 V; TJ = - 43 °C Load Regulation PWM Mode VS = 12 V; TJ = + 25°C Load Regulation PWM Mode VS = 12 V; TJ = + 150°C 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA) 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA) 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA)

Data Sheet 18 Rev. 1.01, 2013-04-30 TLF50281EL Buck Regulator Typical Performance Characteristics Line Regulation PFM Mode ICC = 100 µA; TJ = - 43°C Line Regulation PFM Mode ICC = 100 µA; TJ = + 25°C Line Regulation PFM Mode ICC = 100 µA; TJ = + 150°C Power Stage On Resistance: Black TJ = + 25°C Light Grey TJ = - 43 °C, Dark Grey TJ = + 150 °C 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 0,600 0,800 1,000 1,200 1,400- Vswo (V) 0,000 0,200 0,400 0,1 0,2 0,3 0,4 0,5 0,6 0,7 VS - Iswo(A)

Data Sheet 19 Rev. 1.01, 2013-04-30 Efficiency for VS = 13 V, fOSC = 1.65 MHz, LOUT = 4.7 µH Efficiency for VS = 13 V, fOSC = 1.65 MHz, LOUT = 10 µH Efficiency for VS = 13 V, fOSC = 2.2 MHz, LOUT = 4.7 µH Efficiency for VS = 13 V, fOSC = 2.2 MHz, LOUT = 10 µH 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA)

Data Sheet 20 Rev. 1.01, 2013-04-30 TLF50281EL Reset and Watchdog

6 Reset and Watchdog

6.1 Description Reset Function

Principle: The reset function supervises the value of the regulator output voltage VCC. The result is monitored by the status of pin RO. A high level at pin RO means that the output voltage VCC is above the desired reset threshold. A low level at pin RO means th at the output voltage VCC is below the desired reset threshold. The reset function does not work, if the supply (VFB) voltage is below 1 V. Adjustment of reset threshold: The reset generator consists of an internal comparator with a reset threshold VRO,T. By adding an external resistor divider between the output voltage VCC and ground (GND) and connecting the point between the upper (R1) and lower (R2) resistor to pin RTADJ the desired reset threshold VRT (where the reset generator indicates an under voltage) might be adjusted. If reset function is not used please connect pin RTADJ to VCC. Operation mode (please refer to Figure 7): The reset generator starts operating as soon as the regu lator is activated by supplying the device with an input (battery) voltage higher than the input voltage startup threshold VS,ON and a valid high signal VEN,hi at pin EN. The pin RO is low at this time. When the regulator starts to operate, VCC ramps up and passes the desired reset threshold. The reset delay time tRD is the time duration between that point and pin RO turning to high level. The reset reaction time tRR is the maximum duration or time, the output voltage VCC may dip below the desired reset threshold, before a reset is indicated and pin RO is pulled to low level. This is implemented to avoid wrong reset triggering by short “glitches” on the output voltage VCC. If the output voltage VCC dips below the desired reset threshold VRT for more than tRR , tRR is also the time until pin RO is pulled below VRO,L. A voltage dip at the output voltage VCC leads to a low level at pin RO under the following condition: In case the pin RO is pulled to low level, it stays low for the time until the output voltage VCC is higher than the desired reset threshold VRT plus the reset delay time tRD. Desired reset threshold = VRO T, R1 R2+ ⎛⎞ VRT= VCC VRO T, R1 R2+ ⎛⎞ for t t RR>()<

Data Sheet 21 Rev. 1.01, 2013-04-30 Reset output pin (please refer to Figure 7): The reset output is an open collector structure. As soon as a reset condition occurs, the pin is pulled to ground. A pull up resistor (R4) connected to VCC or another voltage source is necessary. If the supply (VFB) voltage is below 1 V the open collector structure does no longer pull pin RO to ground. In this case pin RO goes up to the pull-up voltage (if not supplied by voltage VCC). The reset output pin RO might be connected in parallel to the watchdog output pin WO, if application requires this. Figure 7 Reset Function and Timing Diagram

• ROH:= Reset Output Hig h Level, depending on voltage sourcing the pull-up resistor at pin RO
• ROL:= Reset Output Low Level, Reset signal valid. The recommended maximum value for the sum of both resistors R1 and R2 of the external resistor divider is 1.2 MΩ V ( related to RTADJ) t VRT < tRR VRO t VROL VROH tRD tRR tRR tRD

Data Sheet 22 Rev. 1.01, 2013-04-30 TLF50281EL Reset and Watchdog

6.2 Electrical Character istics Reset Function

Electrical Characteristics: Reset VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Reset Output RO IRO = 1 mA 6.2.2 Sink current limit IR,S,MAX 1––m A VCC = 5V; VRTADJ < 0.9V, VRO = 0.4V

6.2.3 Leakage current IRO,L,MAX ––1µ A VRO = 5V

6.2.4 Output undervoltage

VRO,T 0.96 1.00 1.04 V –

6.2.5 Output undervoltage

VRO,T,Hyst 50 – 150 mV Output voltage decreasing 6.2.6 Pin RTADJ input current IRTADJ,MAX -1 0.1 1 µA VRTADJ = 1.2V

6.2.7 Delay time tRD 681 0 m s –

6.2.8 Reset reaction time tRR 2 – 10 µs Output voltage decreasing

Data Sheet 23 Rev. 1.01, 2013-04-30

6.3 Description Watchdog Function

Principle: The watchdog supervises the operation of the microprocessor. The result is monitored by the status of pin WO. A high level at pin WO means, that so far no microprocessor failure did occur. A low level at pin WO means, that a microprocessor failure did occur. The watchdog signal is only valid for input (battery) voltage higher than VS,off. The pin WO is also pulled to low, if the reset signal is pulled to low. Watchdog mode select WMSEL: The watchdog offers two operation modes: Slow watchdog timing and fast watchdog timing. For slow watchdog timing please connect pin WMSEL to output voltage VCC. For fast watchdog timing please connect WMSEL to ground (GND). The watchdog mode select pin WMSEL has an integrated pull-down resistor RWMSEL,INT. It is possible to change the time base during operation by switching the level at pin WMSEL from high to low or from low to high. The new timing is valid from the beginning of the new period (beginning of new trigger window). From this time on, the frequency of the microprocessor signal at pin WI has to be adapted, please refer to Figure 11 and Figure 12. If the watchdog function is not used, pl ease connect pin WMSEL to ground (GND) to avoid EMC related influence. Watchdog input pin WI: The watchdog input pin WI is connected to the microprocessor (only if watchdog is used). If watchdog is not used, please connect to ground (GND). Initialization: The watchdog initializes as soon as the reset signal at pin RO turns to high level. With a delay time equal to tRD after the rising edge of the reset signal, the so-called “Ignore Window” starts. The duration of the “Ignore Window” (IW) depends on the selected mode of the watchdog opera tion, either slow watchdog timing or fast watchdog timing. Within this “Ignore Window” the microprocessor must initialize; duri ng the “Ignore Window” any signal at watchdog input pin WI is ignored. The watchdog input pin WI has an integrated pull-down resistor RWI,INT. Normal operation (please refer to Figure 9 and Figure 10): After closing the “Ignore Window” the watchdog opens the first “Trigger Window” (duration: watchdog period tWD,p minus the watchdog sampling time tsam). Both watchdog period tWD,p and watchdog sampling time tsam are depending on the selected mode of the watchdog operation, either slow watchdog timing or fast watchdog timing. Within the “Trigger Window” a valid trigger signal must be applied to the watchdog input WI. A valid trigger signal is a falling edge from VWI,H to VWI,L. After receiving a valid trigger signal within the “Trigger Window” the watchdog immediately terminates the “Trigger Window” and opens the next “Trigger Window” after a time duration tsam. A trigger signal should not be applied during the time duration tsam before the beginning of the “Trigger Window”, because this will not be detected. The watchdog period tWD,p determines the frequency of the watchdog signal at pin WI coming from the microprocessor. The watchdog output WO stays high as long as the watchdog input WI is triggered correctly.

Data Sheet 24 Rev. 1.01, 2013-04-30 TLF50281EL Reset and Watchdog If no valid trigger signal is applied to the pin WI during th e “Trigger Window”, either a missing trigger signal or an invalid trigger signal (please refer to explanation below), the watchdog output pin WO will be pulled to ground with the falling edge of the “Trigger Window”. The watchdog pin WO stays at low level for the reset delay time tRD. Then the watchdog output pin WO turns back to high level ag ain. With the rising edge of the watchdog signal a new “Ignore Window” is opened. The watchdog signal WO does not influence the reset signal RO, but the reset signal RO influences the watchdog signal WO. If a reset condition occurs, the watchdog output pin WO is pulled to ground together with the reset output pin RO. The watchdog output pin stays at low le vel as long as the reset output pin RO is pulled to ground plus the reset delay time tRD; tRD is not depending on the selected mode of th e watchdog operation. Then the watchdog output pin WO turns back to high level again. With the risi ng edge of the watchdog signal a new “Ignore Window” is opened. Valid trigger signal (please refer to Figure 8): Watchdog input WI is periodically sampled with a period of tsam. The watchdog sampling time tsam depends on the selected mode of the watchdog operation, either slow watchdog timing or fast watchdog timing. A valid trigger signal is a falling edge from VWI,H to VWI,L. To improve immunity against noise or glitches on the watchdog input, at least two high samples followed by two low samples are re quired for a valid trigger signal. For example, if the first three samples (two high one low) of the trigger pulse at pin WI are inside the watchdog period tWD,p and only the fourth sample (the second low sample) is taken in the following period tWD,p, then the watchdog output WO will be pulled to low. The frequency of the triggering signal at watchdog input pin WI must be determined, so that valid triggering is ensured under all operating conditions. Figure 8 Valid triggering Watchdog output pin WO: The watchdog output is an open collector structure. As soon as the watchdog detects a microprocessor failure, the pin is pulled to ground. A pull up resistor (R3) connected to VCC or another voltage source is necessary. If the input (battery) voltage is below the in put under voltage shutdown threshold VS,off the pin RO is pulled to ground (GND) and consequently pin WO is also pulled to ground (GND). As soon as the internal supply of the chip drops down, the open collector structure is no longer able to pull pin WO to ground therefore pin WO goes up to the pull- up voltage (if not supplied by voltage VCC). The watchdog output pin WO might be connected in parallel to the reset output pin RO, if application requires this. Trigger Window 1 Trigger Window 2 Watchdog Output (WO) Invalid Valid WI WI Watchdog Decoder Sample Point

Data Sheet 27 Rev. 1.01, 2013-04-30

6.4 Electrical Character istics Watchdog Function

Electrical Characteristics: Watchdog VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Watchdog Mode Select WMSEL

6.4.1 Watchdog mode select,

VWMSEL,H 4.00 – – V – 6.4.2 Watchdog mode select, low VWMSEL,L ––0 . 8 0 V –

6.4.3 Watchdog mode select

IWMSEL –34 μA VWMSEL = 5V

6.4.4 Watchdog mode select,

RWMSEL,INT 1.25 1.67 – ΜΩ – Watchdog Input WI 6.4.5 High level input voltage VWI,H 4.00 – – V – 6.4.6 Low level input voltage VWI,L ––0 . 8 0 V –

6.4.7 High level input current IWI,H –34 μA VWI = 5V

6.4.8 Low level input current IWI,L –0 . 5 1 μA VWI = 0.4V; Tj < 105°C 0.80 1.00 1.20 ms slow watchdog timing 51.2 64.0 76.8 ms slow watchdog timing 6.4.11 Watchdog period tWD,p 25.6 32 38.4 ms fast watchdog timing 51.2 64 76.8 ms slow watchdog timing

6.4.12 Watchdog input, internal

RWI,INT 1.25 1.67 – ΜΩ – Watchdog Output WO 6.4.13 Output voltage low VWO,L –0 . 2 0 . 4 V VOUT =5V; IWO = 1mA 6.4.14 Sink current limit IWO,L,MAX 1––m A VOUT =5V; VWO = 0.4V

6.4.15 Leakage current IWO,H,MAX ––1µ A VWO = 5V

Data Sheet 28 Rev. 1.01, 2013-04-30 TLF50281EL Enable and Thermal Shutdown

7 Enable and Thermal Shutdown

7.1 Description

A valid high level at pin EN (VEN,hi) turns the regulator on, a valid low level at pin EN (VEN,lo) turns the regulator off. In off state the current consumption of the device is less than 2µA. An integrated pull down resistor at pin EN (REN,INT) ensures, that the device is switched off, if pin EN is left open. The integrated thermal shutdown function turns off the power switch in case of overtemperature. The typ. junction shutdown temperature is 175°C, with a min. of 155°C. After cooling down, the IC will automatically restart with a soft start into normal operation. The thermal shutdown is an integrated protection function designed to prevent IC destruction when operating under fault conditions. It should not be used for normal operation.

7.2 Electrical Character istics Module Enable, Bias and Thermal Shutdown

Electrical Characteristics: Enable, Bias and Thermal Shutdown VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Enable EN

7.2.1 Current consumption, shut

Iq,OFF –0 . 1 2µ A VEN = 0V; Tj < 105°C; VS = 16V 7.2.2 Current consumption of VCC Iq,ON,V_CC ––6 0 µ A VEN = 5.0V; VS = 16V; VCC = 5.4V; Tj < 105°C; PFM mode 7.2.3 Current consumption of VS Iq,ON,V_S – 1 52 0µ A VEN = 5.0V; VS = 16V; VCC = 5.4V; Tj < 105°C; PFM mode 7.2.4 Enable high signal valid VEN,hi 3.0 – – V – 7.2.5 Enable low signal valid VEN,lo ––0 . 8 V –

7.2.6 Enable hysteresis VEN,HY 50 200 400 mV –

7.2.7 Enable high input current IEN,hi ––3µ A VEN = 16V

7.2.8 Enable low input current IEN,lo –0 . 1 1µ A VEN = 0.5V

7.2.9 Enable, internal resistor to

REN,INT 71 2 2 0 ΜΩ VEN = 3V Internal Over Temperature Protection

7.2.10 Over temperature shutdown Tj,sd 155 175 195 °C 1)

1) Specified by design. Not subject to production test.

7.2.11 Over temperature shutdown

Tj,sd_hyst -1 5 – K 1)

Data Sheet 29 Rev. 1.01, 2013-04-30

8 Oscillator

8.1 Description

The oscillator supplies the device with a constant frequency. The power switch will be switched on and off with a constant frequency fOSC. The time period TPWM is derived from this frequency and some safety functions are synchronized to this frequency. The oscillator frequency can be set by connecting an external resistor RFREQ between pin FREQ and GND using the following table (selected values, for more precise setting please refer to Figure 13 below). Figure 13 Switching Frequency fOSC versus Frequency setting Resistor RFREQ. The turn-on frequency can optionally be set externally via the SYNC pin. In this case the synchronization of the PWM-on signal refers to the falling edge of the SYNC-pin input signal. In case the synchronization to an external clock signal is not needed, the SYNC pin should be connected to ground. The frequency setting resistor RFREQ is also necessary for SYNC option and must be dimensioned according to the desired synchronization frequency (the ratio between synchronization and internal frequency has to be less than or equal to 1). The synchronization function is not available in PFM mode. Frequency Setting Resistor

8.1.1 Frequency adjusting resistor RFREQ 39 43 56 82 100 k Ω

8.1.2 Oscillator frequency fosc 2400 2250 1800 1330 1100 kHz

1,15 1,3 1,45 1,6 1,75 1,9 2,05 2,2 2,35 2,5 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 Switching Frequency [MHz] Resistor at Freq pin [kΩ]

Data Sheet 30 Rev. 1.01, 2013-04-30 TLF50281EL Oscillator

8.2 Electrical Characteristics

Electrical Characteristics: Buck Regulator VS = 6.0 V to 40 V, Tj = -40 °C to +150 °C, all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limi t Values Unit Conditions Min. Typ. Max. Frequency Setting FREQ

8.2.1 Oscillator frequency spread

fosc 2025 2250 2475 kHz VSYNC = 0V; RFREQ = 43kΩ Synchronization SYNC

8.2.2 Synchronization capture range fsync 1500 – 2200 kHz –

8.2.3 SYNC signal high level valid VSYNC,H 2.9 – – V 1) 1) Synchronization of PWM-on signal to falling edge. 8.2.4 SYNC signal low level valid VSYNC,L ––0 . 8 V 1)

8.2.6 SYNC signal minimum high time tSYNC,H, min 25 – – ns –

8.2.7 SYNC signal minimum low time tSYNC,L,min 25 – – ns –

Application Information

Data Sheet 31 Rev. 1.01, 2013-04-30

9 Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 14 Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application Figure 15 Bill of Material for Application Diagram CIN3 DIN LIN Enable Oscillator Buck Converter FB SWO FREQ RO EN VS Soft Start Ramp Generator Bandgap Reference Reset Generator TLF50281EL Over Temperature Shutdown Watchdog WI WMSEL DCATCH COUT VS VCC LOUT INT. SUPPLY WO RTADJ To µPTo µP From µP VCC SYNC CIN2CIN1 LIN, CIN1 and CIN3 recommended for suppression of EME, DIN depending on application GND GND N.C. CIN2 CIN3 COUT LOUT DCATCH 100nF/50V 47µF/50V 10µF/25V Part-No. Value 1A/100V Type Manufacturer 10µH MSS1278 T AVX ceramic ceramic Remark Coilcraft 10BQ100 Schottky International Rectifier 43 kΩ 100 kΩ 100 kΩ 100 kΩ 330 kΩ VRT set to 4.3 V VRT set to 4.3 V0.25 W 0.25 W 0.25 W 0.25 W 0.25 W electrolytic 4.7 µH also possible fOSC set to 2.2 MHz For improving EME

1 A current capability

Data Sheet 32 Rev. 1.01, 2013-04-30 TLF50281EL

9.1 General Layout recommendations

Introduction: A switch mode step down converter is a potential source of electromagnetic disturbances which may affect the environment as well as the device itself and cause sporadic malfunction up to damages depending on the amount of noise. In principal we may consider the following basic effects:

• radiated magnetic fields caused by circular currents, occurring mostly with the switching frequency and their harmonics;
• radiated electric fields, often caused by (voltage) oscillations;
• conducted disturba nces (voltage spikes or oscillations) on the lines, mostly input and output lines. Radiated magnetic fields: Radiated magnetic fields are caused by circular currents occurring in so called “current windows”. These circular currents are alternating currents which are driven by th e switching transistor. The alternating current in these windows are driving magnetic fields. The amount of magnetic emissions is mainly depending on the amplitude of the alternating current and the size of the so-called “wi ndow” (this is the area, whic h is defined by the circular current paths. We can divide into two windows:
• the input current “window” (path consisting of C IN2, CIN3, LOUT and COUT): Only the alternate content of the input current IS is considered;
• the output current “window” (path consisting of D CATCH , LOUT and COUT): Output current ripple ΔI. The area of these “windows” has to be kept as small as possible, with the relating elements placed next to each others as close as possible. It is highly recommended to use a ground plane as a single layer which covers the complete regulator area with all components shown in the application diagram. All connections to ground shall be as short as possible. Radiated electric fields: Radiated electric fields are caused by voltage oscillations occurring by stray inductances and stray capacitances at the connection between internal power stage (pin SWO), freewheeling diode DCATCH, and output capacitor COUT. They are also of course influenced by the commutation of the current from the internal power stage to the freewheeling diode D CATCH. Their frequencies might be above 100 MHz. Therefore, it is recommended to use a fast Schottky diode and to keep the connections in this ar ea as low inductive as possible. This can be achieved by using short and broad connections and by arranging the related parts as close as possible. Following the recommendation of using a ground layer these low inductive connections will form together with the ground layer small capacitances which are desirable to damp the slope of these oscillations. The oscillations use connections or wires as antennas, this effect can also be minimized by the short and broad connections.

Data Sheet 33 Rev. 1.01, 2013-04-30 Conducted disturbances: Conducted disturbances are voltage spikes or voltage osc illations, occurring permanently or by occasion mostly on the input or output connections. Comparable to the radi ated electric fields they are caused by voltage stage, freewheeling diode DCATCH, and output capacitor COUT. Their frequencies might be above 100 MHz. They are super positioned to the input and output voltage and might therefore disturb other components of the application. The countermeasures against conducted disturbances are similar to the radiated electric fields:

• it is recommended to use short and thick connecti ons between the single parts of the converter;
• all parts shall be mounted close together;
• additional filter capacitors (ceramic, with low ESR i.e C IN3 in the application diagram) in parallel to the output and input capacitor and as close as possible to the switching parts. Input and load current must be forced to pass these devices, do not connect them via thin lines. Recommended values from 10nF to 220nF;
• for the input filter a so called π – Filter for maximum suppression might be necessary, which requires additional capacitors on the input.

9.1.1 Additional information

Please contact us:

• for information regarding the Pin FMEA;
• for existing application notes wit h more detailed information about the possibilities of this device;
• for further information you may contact http://www.infineon.com/

Data Sheet 34 Rev. 1.01, 2013-04-30 TLF50281EL Package Outlines Figure 16 Package Outline PG-SSOP-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Gree n products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad For further package information, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Revision History

Data Sheet 35 Rev. 1.01, 2013-04-30 Rev Version Date Changes Rev 1.01 2013-04-30 Editorial change: Pin FREQ added to chapter General Product Characteristics. Efficiengy graphs, Line Regulation graphs changed in chapter Buck Regulator. Table Frequency setting resistor actualized in chapter Oscillator. Bill of material updated in chapter Application Information. Pin 12 N.C. on chapter Pin Configuration. Electrical Characteristics change: table actualized in chapter Oscillator. Rev 1.0 2011-10-24 Initial data sheet

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© 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.