TLF11251EP INFINEON | Alldatasheet
Document overview
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Technical content
Features
- AEC-Q100 Grade 0 for high temperature mission profiles
- Integrated PMOS and NMOS complementary output bridge with 2.5 A current capability
- Integrated gate drivers
- Single control input with an integrated dead time logic for optimized control and high efficiency
- Output current sensing
- Output current limitation
- Overtemperature protection
- Low quiescent current
- No external dead time adjustment required
- Infineon automotive quality
- Green Product (RoHS compliant) Potential applications Companion for the OPTIREG™ PMIC TLF3558xxxx for core voltage regulation of AURIX™ TC3xx microcontroller in:
- Car powertrain and transmission applications
- Electric power steering
- Battery management
- Inverter applications
- Engine management
- Domain control Product validation Qualified for automotive applications with higher temperature requirements. Product validation according to AEC-Q100, Grade 0.
Description
The OPTIREG™ PMIC TLF11251EP is a 2.5 A half bridge with integrated driver and level shifter. It also contains a high side P-channel MOSFET and a low side N-channel MOSFET in a single package. The integrated level shifting stage allows for conversion of the input logic signals to the supply voltage level of the gate drivers. The input signal levels are CMOS compatible. The level shifter and the gate driver provide a dead time generation to simplify the interface with the embedded core voltage regulator of the AURIX™ TC3xx microcontroller. The Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document Rev. 1.03 www.infineon.com/OPTIREG-PMIC 2022-11-25
low propagation delay allows for use in closed loop control applications with limited requirements for timing. The output stage allows for a high switching frequency. The TLF11251EP integrates protection features against overcurrent at the high side MOSFET and at the low side MOSFET as well as against overtemperature events. Internal power-on reset releases the digital logic and ensures its operation for the supply voltage within the specified range. Type Package Marking TLF11251EP PG-TSDSO-14 TLF11251 OPTIREG™ PMIC TLF11251EP
2.5 A half bridge with integrated driver and level shifter
Datasheet 2 Rev. 1.03 2022-11-25
OPTIREG™ PMIC TLF11251EP Datasheet 3 Rev. 1.03 2022-11-25
OPTIREG™ PMIC TLF11251EP Datasheet 4 Rev. 1.03 2022-11-25
1 Block diagram
OPTIREG™ PMIC TLF11251EP Datasheet 5 Rev. 1.03 2022-11-25
2 Pin configuration
2.1 Pin assignment
Figure 2 Pin configuration OPTIREG™ PMIC TLF11251EP Datasheet 6 Rev. 1.03 2022-11-25
2.2 Pin definitions and functions
1 NC Not connected. This pin is not connected internally; leave it open. 2, 3 SW Switch node: Half bridge drains; typically connected to the input of the LC filter in buck circuits 4, 10 PGND Power ground: Half bridge low side source
5 GND Ground:
6 LSCON Bridge control scheme:
Defines the low side state during PWM input "high" . Switch to "high" enables synchronous control of high side and low side, based on PWM input state. Switch to "low" disables low side control.
7 NC Not connected:
This pin is not connected internally; leave it open.
8 PWM Control input:
Input for the logical signal that controls the state of the half bridge transistors. Switch to "high" opens the high side switch and closes the low side switch. Switch to "low" closes the high side switch and opens the low side switch.
9 VCC Supply voltage input:
Supply voltage for the PWM and LSCON inputs; typically the same as the supply of microcontroller output pins.
11 NC Not connected:
This pin is not connected internally; leave it open. 12, 13 VS Supply voltage input: Supply to gate drivers, connected to half bridge high side source
14 NC Not connected:
This pin is not connected internally; leave it open – Heat sink Connect to heat sink area. Connect to GND and PGND. OPTIREG™ PMIC TLF11251EP Datasheet 7 Rev. 1.03 2022-11-25
3 General product characteristics
3.1 Absolute maximum ratings
Table 1 Absolute maximum ratings 1) Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Voltages Supply voltage VS VS -0.3 – 7.0 V – P_3.1.1 Supply voltage VCC Vcc -0.3 – 7.0 V – P_3.1.2 Switch node SW VSW -0.3 – 7.0 V – P_3.1.3 Input PWM VPWM -0.3 – 7.0 V – P_3.1.4 Input LSCON VLSCON -0.3 – 7.0 V – P_3.1.5 Currents Continuous drain current high side IDHS -2.5 – – A PWM = off P_3.1.6 Continuous drain current low side IDLS – – 2.5 A PWM = on P_3.1.7 Pulsed drain current high side IDHS -4.4 – – A Valid during active overcurrent protection P_3.1.8 Pulsed drain current low side IDLS – – 4.4 A Valid during active overcurrent protection P_3.1.9 Temperatures Junction temperature Tj -40 – 150 °C – P_3.1.10 Storage temperature Tstg -55 – 150 °C – P_3.1.11 ESD susceptibility ESD susceptibility all pins VESD -2 – 2 kV 2) HBM P_3.1.12 ESD susceptibility all pins VESD -500 – 500 V 3) CDM P_3.1.13 ESD susceptibility (corner pins) VESD -750 – 750 V 3) CDM P_3.1.14 1) Not subject to production test, specified by design. 2) Human body model (HBM) robustness according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF). 3) Charged device model (CDM) robustness according to JEDEC JESD22-C101. Notes: 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation. OPTIREG™ PMIC TLF11251EP Datasheet 8 Rev. 1.03 2022-11-25
3.2 Functional range
Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Supply voltage range VS VS,nom 3.5 – 7.0 V – P_3.2.1 Supply voltage range VCC VCC,nom 2.35 – 7.0 V – P_3.2.2 Supply voltage VS transient slew rate dVS/dt -120 – 120 V/ms 1) P_3.2.3 Supply voltage VCC transient slew rate dVCC/dt -120 – 120 V/ms 1) P_3.2.4 Junction temperature Tj -40 – 175 °C – P_3.2.6 Supply current total, normal operation IC,norm – – 35 mA PWM input @
1.8 MHz
P_3.2.9 Supply current total, no switching IC,ns – 200 – µA VS < 5.8 V; Vcc < 5.1 V; Tj < 85°C P_3.2.10 1) Not subject to production test, specified by design. Note: Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the electrical characteristics table. OPTIREG™ PMIC TLF11251EP Datasheet 9 Rev. 1.03 2022-11-25
3.3 Thermal resistance
Table 3 Thermal resistance 1) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Junction to case top, high side RthJCT(HS) 30.9 – 34.1 K/W – P_3.3.6 Junction to case top, low side RthJCT(LS) 39.5 – 43.7 K/W – P_3.3.7 Junction to case bottom, high side RthJCB(HS) 9.6 – 10.6 K/W – P_3.3.8 Junction to case bottom, low side RthJCB(LS) 13.4 – 14.8 K/W – P_3.3.9 Junction to ambient RthJA – 43.3 – K/W 2) P_3.3.10 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first inner copper layer. Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information visit www.jedec.org. OPTIREG™ PMIC TLF11251EP Datasheet 10 Rev. 1.03 2022-11-25
4 Block description and electrical characteristics
The device simplifies the interface of microcontroller control outputs to the half bridge.
4.1 Logical inputs
A single PWM input controls the state of the half bridge MOSFETs. The inverted logical scheme translates the PWM input state to the gate signal shifted to the output supply level, thus the device switches the high side MOSFET off during PWM logical on-state, and it switches them on during PWM logical off state. The built-in dead time control circuitry prevents a shoot-through condition over the MOSFET bridge and improves system efficiency while used in buck power conversion circuits. No external dead time adjustment is required. In addition to the PWM input, the LSCON input determines the low side MOSFET control scheme and allows for both synchronous as well as asynchronous operation in buck converter applications. Logical off state at the LSCON input switches off the low side MOSFET independently of the PWM input signal, so that the device only controls the high side MOSFET . A permanent logical on state at the LSCON input allows both high side and low side operation according to PWM input state with the internal dead time generation. If such operation is required, then the LSCON input can be pulled-up or connected directly to the VCC supply rail. The device interprets a toggling input signal at LSCON as a control request for synchronous low side and high side MOSFET switching. In this case the device generates dead time internally in accordance with the PWM input timing. Frequency detection at LSCON inputs detect toggling input signals within the acceptable range referred to as tdet. Table 4 Switching states LSCON PWM High side MOSFET Low side MOSFET On 1) On Off On On 2) Off On Off Off On Off Off Off Off On Off Toggling between on and off3) On Off On Off On Off Toggling between on and off stopped4) (< tfil) On Off On Off On Off Toggling between on and off stopped (> tfil); LSCON: on On Off On Toggling between on and off stopped (> tfil); LSCON: on Off On Off Toggling between on and off stopped (> tfil); LSCON: off On Off Off Toggling between on and off stopped (> tfil); LSCON: off Off On Off (table continues...) OPTIREG™ PMIC TLF11251EP Datasheet 11 Rev. 1.03 2022-11-25
Table 4 (continued) Switching states LSCON PWM High side MOSFET Low side MOSFET 1) On: "high" 2) Off: "low" 3) Toggling between on and off: The device detects switching on and off at a frequency corresponding to the detection range tdet at the LSCON input. 4) Toggling between on and off stopped: After the toggling between on and off, the device detects a permanent on or off state. The switching states in Table 4 are only valid for device input supplies within the operational range and if no protection feature is active. If the PWM pin is not connected, then the integrated weak pull-up ensures a defined level. If an AURIX™ TC3xx microcontroller controls the device, then place an additional pull-down resistor at the LSCON input to keep the low side MOSFET switched off during power-down, see Application information. OPTIREG™ PMIC TLF11251EP Datasheet 12 Rev. 1.03 2022-11-25
4.2 Control parameters
4.2.1 Functional description control parameters
The device provides a high frequency switching capability with a low propagation delay. The input stage and the drivers can react to fast changing PWM signals and provide a tres resolution to the on-time of the input signal with a pulse duration longer than tpulse. The "low" state pulse duration is limited to tpulse, min. The total propagation time tprop is the time from the "low" to "high" edge transition or from the "high" to "low" edge transition at the PWM input to the SW output level transitions to 10% or 90% of VS supply level accordingly. The internal dead time generation provides optimal efficiency during switching phases and performs the state change of the switching node SW within the specified propagation delay. The device is optimized for a switching frequency in a buck converter application from 0.3 MHz to 2 MHz. 0.1*Vs 0.9*Vs PWM Input Min accepted pulse: tpulse,min=65nsV IL V IH tpulse tpulse ± |t res | tprop,re tprop,fe PWM SW Vs DUT PGNDGND 15..25 Ohm 15..25 Ohm Test circuit SW output Figure 3 Control timing diagram OPTIREG™ PMIC TLF11251EP Datasheet 13 Rev. 1.03 2022-11-25
4.2.2 Electrical characteristics control parameters
Table 5 Electrical characteristics control parameters VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Propagation time, PWM falling edge tprop,fe – – 60 ns High side drain connected to resistive load; VCC > 3.0 V; VS > 4.5 V P_4.2.1 Propagation time, PWM rising edge tprop,re – – 60 ns Low side drain connected to resistive load; VCC > 3.0 V; VS > 4.5 V P_4.2.2 Minimum pulse width input tpulse, min Pulse resolution time tres – – 3 ns 1) P_4.2.4 Dead time "high" to "low" tdead,hl – 15 – ns 1) P_4.2.5 Dead time "low" to "high" tdead,lh – 18 – ns 1) P_4.2.6 LSCON frequency detector frequency range fdet,lscon 0.72 – – MHz – P_4.2.7 LSCON frequency detector filter time tfil,lscon 3 – – µs 1) P_4.2.8 Logic inputs Input voltage "high" VIH 0.67 × Vcc – – V CMOS function P_4.2.9 Input voltage "low" VIL – – 0.33 × Vcc V CMOS function P_4.2.10 Input voltage hysteresis VIHYS 0.05 – – V – P_4.2.11 Input capacitance CIN – 10 – pF 1) P_4.2.12 1) Not subject to production test, specified by design. OPTIREG™ PMIC TLF11251EP Datasheet 14 Rev. 1.03 2022-11-25
4.3 Output stage
4.3.1 Functional description output stage
The P-N-channel output half bridge of the device can operate at a switching frequency up to 2 MHz nominal range, providing very low power dissipation in synchronous buck converter topology. The P-channel MOSFET used as high side switch eliminates the need for a charge pump circuitry and improves the EMI performance. The output stage delivers a minimum output current of 2.5 A within the specified voltage and temperature range.
4.3.2 Electrical characteristics output stage
Table 6 Electrical characteristics output stage VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. On-state resistance high side RONHS – – 100 mΩ Tj ≤ 150°C; Id = -2 A; Vs = 5.8 V P_4.3.1 Id = -2 A; Vs = 5.8 V P_4.3.2 On-state resistance low side RONLS – – 105 mΩ Tj ≤ 150°C; Id = 2 A; Vs = 5.8 V P_4.3.3 Id = 2 A; Vs = 5.8 V P_4.3.4 Body diode forward voltage high side VDFHS – 0.67 0.95 V Ifw = 2 A P_4.3.5 Body diode forward voltage low side VDFLS – 0.72 0.91 V Ifw = 2 A P_4.3.6 1) Not subject to production test, specified by design. OPTIREG™ PMIC TLF11251EP Datasheet 15 Rev. 1.03 2022-11-25
4.3.3 Typical performance characteristics output stage
Maximum on-state resistance high side RONHS (PWM = "low") versus Tj = -40°C, 25°C, 150°C Maximum on-state resistance low side RONLS (PWM = "high") versus Tj = -40°C, 25°C, 150°C OPTIREG™ PMIC TLF11251EP Datasheet 16 Rev. 1.03 2022-11-25
4.4 Protection functions
The following integrated protection functions prevent the device and the output circuitry from destruction as well as from operation under unspecified conditions:
- High side and low side overcurrent detection and limitation
- Undervoltage shutdown
- Overtemperature protection The device reacts within the time specified for each protection feature. This is related to the state change of the half bridge MOSFETs independent from the PWM input signal. The device performs the input logic reset release at VS voltage exceeding the minimum functional limit of 3.5 V, where protection functions are also operational. For the VCC voltage below VCCUV, the output half bridge MOSFETs remain in the off-state and the output switch node SW is floating.
4.4.1 Undervoltage shutdown
4.4.1.1 Functional description undervoltage shutdown
The device monitors the input supply VCC for undervoltage conditions. If the output voltage drops below the Vccuv limit, then the device switches off the high side MOSFET and the low side MOSFET , so that the device is only operational within the specified supply limits. The voltage hysteresis circuitry Vccuvh protects from noise conditions.
4.4.1.2 Electrical characteristics undervoltage shutdown
Table 7 Electrical characteristics undervoltage shutdown VS = 3.5 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Undervoltage limit at VCC supply Undervoltage detector hysteresis Undervoltage detector reaction time Vuvr – – 3 µs 1) P_4.4.2.3 1) Not subject to production test, specified by design. OPTIREG™ PMIC TLF11251EP Datasheet 17 Rev. 1.03 2022-11-25
4.4.2 Overcurrent protection
4.4.2.1 Functional description overcurrent protection
The overcurrent protection works in a cycle-by-cycle limitation mode. If the sensed input drain current exceeds the peak current limit Ioc, lim during a switching cycle, then the device switches off the high side MOSFET and the switch node SW current decreases. If the overcurrent protection circuitry is active, then the device limits the PWM input duty cycle for each cycle. During startup or with VCC supply power cycle after the logic reset is released, the overcurrent protection remains inactive for the number of PWM pulses npwm,st to avoid accidental activation due to startup current overshoot. Figure 4 Overcurrent protection example OPTIREG™ PMIC TLF11251EP Datasheet 18 Rev. 1.03 2022-11-25
4.4.2.2 Electrical characteristics overcurrent protection
Table 8 Electrical characteristics overcurrent protection VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Startup protection inactive, number of PWM pulses npwm,st – – 5500 – VCC rising above VCC,min P_4.4.3.2 OPTIREG™ PMIC TLF11251EP Datasheet 19 Rev. 1.03 2022-11-25
4.4.3 Overtemperature protection
4.4.3.1 Functional description overtemperature protection
If an overtemperature condition TjOT occurs, then the integrated temperature sensor disables the device by switching off the high side and low side MOSFETs. Only if both the temperature decreases by the hysteresis temperature dTj and the temperature falls below TjSO, then the MOSFETs resume operation.
4.4.3.2 Electrical characteristics overtemperature protection
Table 9 Electrical characteristics overtemperature protection 1) VS = 3.5 V to 7 V; VCC = 2.35 V to 7 V; Tj = -40°C to 150°C; all voltages with respect to ground; positive current flowing into pin (unless otherwise specified). Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Overtemperature shutdown TjOT 175 – 200 °C – P_4.4.4.1 Switch-on temperature TjSO – – 165 °C – P_4.4.4.2 Overtemperature switch-on hysteresis 1) Not subject to production test, specified by design. OPTIREG™ PMIC TLF11251EP Datasheet 20 Rev. 1.03 2022-11-25
5 Application information
Note: The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
5.1 Application diagram
In the target application scenario the device is the counterpart for an AURIX™ TC3xx microcontroller for core voltage generation with the system power supply TLF35584. The device configuration allows connectivity with the half bridge control output of the microcontroller’s embedded voltage regulator core (EVRC) converter, which generates the core voltage Vdd. The device only supports power supply topologies that use different sources for the microcontroller supply domain Vext and the EVRC input VS, expecting different voltage levels. VS must exceed VCC during startup, in normal operation and during power-down. Figure 5 Application diagram Note: This figure is a simplified example of an application circuit. The function must be verified in the application. As soon as VS voltage reaches 3.5 V during power-up, the device releases the internal logic reset. During this phase the central function logic is operational. Only if VCC is within the specified range, then the device reacts to the input signals LSCON and PWM as specified. However, the operational VCC voltage minimum is specified at 2.35 V, which allows for early device readiness, even if the microcontroller is not yet operational. The VGATEP output of the microcontroller controls the PWM signal, while the VGATEN output is connected to LSCON. The microcontroller typically starts in an open loop mode, controlling only VGATEP and allowing for fast Vdd voltage ramp-up and startup. After ramp-up time, the EVRC starts to control the high side and low side MOSFETs of the half bridge. The LSCON input detects this phase with the frequency detector. If the microcontroller is switched into power-down mode and if the high side and low side control signals are off, OPTIREG™ PMIC TLF11251EP Datasheet 21 Rev. 1.03 2022-11-25
then the frequency detector recognizes it as a request to set the SW output floating. Therefore add a pull-down resistor for the LSCON signal in order to limit its possible variation during the power-down phase after the supply voltage reaches the hard reset limit of the microcontroller. Figure 6 Start-up and ramp-down example Table 10 shows the required nominal values of the discrete components for proper operation. Table 10 Nominal values of discrete components Component name Nominal value Acceptable variation Note CVS 10 µF ±30% Input capacitor CVDD 22 µF ±30% Output capacitor LVDD 3.3 µH ±30% (@ 1.8 MHz) Output inductor RLSCON 6.2 kΩ ±20% LSCON input pull-down OPTIREG™ PMIC TLF11251EP Datasheet 22 Rev. 1.03 2022-11-25
6 Package information
1) 1) Figure 7 PG-TSDSO-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a Green Product. Green Products are RoHS compliant (Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Information on alternative packages Please visit www.infineon.com/packages. OPTIREG™ PMIC TLF11251EP Datasheet 23 Rev. 1.03 2022-11-25
Revision history
1.03 2022-11-25 Editorial changes 1.02 2021-02-05 Editorial changes 1.01 2021-01-14 Editorial changes 1.0 2020-01-23 Datasheet created OPTIREG™ PMIC TLF11251EP Datasheet 24 Rev. 1.03 2022-11-25
All referenced product or service names and trademarks are the property of their respective owners. Edition 2022-11-25 Published by Infineon Technologies AG
81726 Munich, Germany
© 2022 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-Z8F57382527 Important notice The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.