TLE 232GP

TLE6232GP_09 INFINEON | Alldatasheet

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Technical content

V2.3 Page 2009-11-18 1 Smart Six Channel Low-Side Switch Features Product Summary

• Short Circuit Protection up to 24 V
• Over-temperature Protection
• Over-voltage Protection
• 16 bit Serial Data Input and Diagno s- tic Output (2 bit/ch. acc. SPI protocol)
• Direct Parallel Control of all six Chan- nels for PWM Applications
• General Fault Flag
• Low Quiescent Current
• Compatible with 3V Micro Controllers
• Electrostatic Discharge (ESD) Protection
• Parallel Inputs High or Low Active Programmable
• Green Product (RoHS compliant)
• AEC qualified Application
• µC Compatible Power Switch for 12 V and 24V Applications
• Switch for Automotive and Industrial System
• Solenoids, Relays and Resistive Loads
• Robotic Controls General description Six Channel Low -Side Switch in Smart Powe r Technology (SPT) with a Serial Peripheral Interface (SPI) and six open drain DMOS output stages. The TLE 6232 GP is protected by embedded prote c- tion functions and designed for automotive and industrial applications. The output stages are co n- trolled via a n SPI Interface. Additionally all six channels can be controlled direct in parallel for PWM applications. Therefore the TLE 6232 GP is particularly suitable for engine management and power- train systems. Block Diagram Supply voltage VS 4.5 – 5.5 V Drain source clamping voltage VDS(AZ)typ. 53 V On resistance RON1-4 0.25 Ω RON 5,6 0.45 Ω Output current (Channel 1-4) ID(NOM) 2 A (Channel 5,6) ID(NOM) 1 A PG-DSO 36 RESET FAULT CS Output Stage Output Control BufferSerial Interface SPI LOGIC SCLK SI 6 6 GND VS SO 1 6 IN1 OUT1 OUT6 PRG VBB VS as Ch. 1 GND Protection Functions as Ch. 1 as Ch. 1 as Ch. 1 IN6 as Ch. 1

V2.3 Page 2009-11-18 2 Detailed Block Diagram FAULTRESET Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 SCLK VS IN1 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 SPI Interface 16 bit Normal function SCB/Overload/OT Open load short to ground PRG VSGND Output Stage SI SO GND IN3 as Ch.1 IN4 as Ch.1 IN2 as Ch.1 IN5 as Ch.1 IN6 as Ch.1 Output Control Buffer CS

V2.3 Page 2009-11-18 3 Pin Description Pin Configuration (Top view) Pin Symbol Function

1 GND Ground

2 NC not connected

3 OUT5 Power Output Channel 5

4 NC not connected

5 OUT1 Power Output Channel 1

6 IN5 Input Channel 5

7 IN1 Input Channel 1

8 Vs Supply Voltage

9 RESET Reset

10 CS Slave Select

11 PRG Program (inputs high or low-active)

12 IN2 Input Channel 2

13 IN6 Input Channel 6

14 OUT2 Power Output Channel 2

15 NC not connected

16 OUT6 Power Output Channel 6

17 NC not connected

18 GND Ground

19 GND Ground

20 NC not connected

21 NC not connected

22 NC not connected

23 OUT3 Power Output Channel 3

24 NC not connected

25 IN3 Input Channel 3

26 FAULT General Fault Flag

27 SO Serial Data Output

28 SCLK Serial Clock

29 SI Serial Data Input

30 IN4 Input Channel 4

31 NC not connected

32 OUT4 Power Output Channel 4

33 NC not connected

34 NC not connected

35 NC not connected

36 GND Ground

Heat Slug internally connected to ground pins GND 1• 36 GND NC 2 35 NC OUT5 3 34 NC NC 4 33 NC OUT1 5 32 OUT4 IN5 6 31 NC IN1 7 30 IN4 VS 8 29 SI RESET 9 28 SCLK CS 10 27 SO PRG 11 26 FAULT IN2 12 25 IN3 IN6 13 24 NC OUT2 14 23 OUT3 NC 15 22 NC OUT6 16 21 NC NC 17 20 NC GND 18 19 GND Power SO 36

V2.3 Page 2009-11-18 4 Maximum Ratings for Tj = – 40°C to 150°C Parameter Symbol Values Unit Supply Voltage VS -0.3 ... +7 V Continuous Drain Source Voltage (OUT1...OUT8) VDS 45 V Input Voltage, All Inputs and Data Lines VIN - 0.3 ... + 7 V Operating Temperature Range Storage Temperature Range Tj Tstg - 40 ... + 150 - 55 ... + 150 Output Current per Channel (see el. characteristics) ID(lim) ID(lim) min A Single pulse inductive Energy (internal clamping) Tj=125°C, Ch1-4: 3A linear decreasing Ch5,6: 1,5A linear decreasing E mJ Output Current per Channel @ TA = 25°C (All 6 Channels ON; Mounted on PCB ) 1) ID 1-4 ID 5,6 1.1 0.55 A Power Dissipation (mounted on PCB) @ TA = 25°C Ptot 3.3 W Electrostatic Discharge Voltage (Human Body Model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 VESD 2000 V DIN Humidity Category, DIN 40 040 E IEC Climatic Category, DIN IEC 68-1 40/150/56 Thermal Resistance junction – case (die soldered on the frame) junction - ambient @ min. footprint junction - ambient @ 6 cm2 cooling area with heat pipes RthJC RthJA K/W 1) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to be calculated using RthJA according mounting conditions. PCB with heat pipes, backside 6 cm2 cooling area Minimum footprint

V2.3 Page 2009-11-18 5

Electrical Characteristics

Parameter and Conditions Symbol Values Unit VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) min typ max 1. Power Supply, Reset Supply Voltage2 VS 4.5 -- 5.5 V Supply Current IS -- -- 10 mA Supply Current in Standby Mode (RESET = L) IS(stdy) -- -- 10 µA Minimum Reset Duration tReset,min 1 -- -- µs 2. Power Outputs ON Resistance VS = 5 V; ID = 1 A TJ = 25°C Channel 1-4 TJ = 150°C RDS(ON) -- 0.25 0.28 0.5 Ω ON Resistance VS = 5 V; ID = 500 mA TJ = 25°C Channel 5,6 TJ = 150°C RDS(ON) -- 0.45 0.55 Ω Output Clamping Voltage Output OFF VDS(AZ) 45 53 60 V Current Limit Channel 1-4 Current Limit Channel 5,6 ID(lim) 1-4 ID(lim) 5,6 1.5 A Output Leakage Current VReset = L ID(lkg) -- -- 10 µA Turn-On Time Ch 1-4 ID = 2 A, resistive load Ch 5,6 ID = 1 A, resistive load tON -- 5 10 µs Turn-Off Time Ch 1-4 ID = 2 A, resistive load Ch 5,6 ID = 1 A, resistive load tOFF -- 5 10 µs Switch-On Slew Rate (resistive load) son 1 4 20 V/µs Switch-Off Slew Rate (resistive load) son 1 4 20 V/µs 3. Digital Inputs Input Low Voltage VINL - 0.3 -- 1.0 V Input High Voltage VINH 2.0 -- -- V Input Voltage Hysteresis VINHys 100 200 400 mV Input Pull Up Current (Reset) IIN(Res) 10 20 50 µA Input Pull Down Current (PRG) IIN(PRG) 10 20 50 µA Input Pull Up Current ( CS, SI, SCLK) IIN(SI,SCLK) 10 20 50 µA 4. Digital Outputs (SO, FAULT ) SO High State Output Voltage ISOH = -2 mA VSOH VS - 1 -- -- V SO Low State Output Voltage ISOL = 2 mA VSOL -- -- 0.4 V Output Tri-state Leakage Current CS = H, 0 ≤ VSO ≤ VS ISOlkg -10 0 10 µA FAULT Output Low Voltage IFAULT = 2 mA VFAULTL -- -- 0.4 V 2 For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched off. This under-voltage reset gets active at VS = 3V (typ. value) and is specified by design.

V2.3 Page 2009-11-18 6 Electrical Characteristics cont. Parameter and Conditions Symbol Values Unit VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H (unless otherwise specified) min typ max 5. Diagnostic Functions Open Load Detection Voltage VDS(OL) 0.52* Vs 0.6* Vs 0.68* Vs V Short to Ground Detection Voltage VDS(SHG) 0.32* Vs 0.4* Vs 0.48* Vs V Diagnostic Current (incl. Leakage) UOUTi,j = 14V UOUTi,j = 0V IOUTi,j -IOUTi,j 325 580 130 980 250 µA µA Current Limitation; Overload Threshold Current ID(lim) 1-4 ID(lim) 5,6 1.5 A A Over-temperature Shutdown Threshold Hysteresis Tth(sd) Thys 170 200 K Fault Delay Time td(fault) 60 120 240 µs 6. SPI-Timing Serial Clock Frequency (@ CSO ≤ 50pF) fSCK DC -- 5 MHz Serial Clock Period (1/fclk) tp(SCK) 200 -- -- ns Serial Clock High Time tSCKH 50 -- -- ns Serial Clock Low Time tSCKL 100 -- -- ns Enable Lead Time (falling edge of CS to rising edge of CLK) tlead 100 -- -- ns Enable Lag Time (falling edge of CLK to rising edge of CS) tlag 150 --- -- ns Data Setup Time (required time SI to falling of CLK) tSU 20 -- -- ns Data Hold Time (falling edge of CLK to SI) tH 20 -- -- ns Disable Time tDIS -- -- 100 ns Transfer Delay Time3 ( CS high time between two accesses) tdt 150 -- -- ns Data Valid Time4 CL = 50 pF CL = 100 pF CL = 150 pF tvalid -- 100 120 150 ns ns ns 3 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time t d(fault)max = 200µs. 4 This parameter will not be tested but specified by design

V2.3 Page 2009-11-18 7 Description of the Power Stages 4 low side power switches for nominal currents up to 3A (power stages OUT1 to OUT4). Co n- trol is possible by input pins or via SPI. For T J = 150°C the on-resistance of the power switches is below 500mΩ . 2 low side power switches for nominal currents up to 1.5A (power stages OUT5 and OUT6). Control is possible by input pins or via SPI. For T J = 150°C the on-resistance of the power switches is below 1Ω . In order to increase the switching current or to reduce the power dissipation parallel conne c- tion of power stages is possible. Each of the 6 output stages is equipped with its own zener clamp, which limits the output vol t- age to a maximum of 60V. The outputs are provided with a current limitation set t o a minimum of 1.5A resp. 3A. Each power stage is equipped with an own temperature sensor. Each output is protected by embedded protection functions 5) . In case of overload or short- circuit to UBatt the current is internally limited and the corresponding b it combination is set (early warning). If this operation leads to an over-temperature condition, a second protection level (about 170°C) will change the output into a low duty cycle PWM (selective thermal shut - down with restart) to prevent critical chip te mperatures. The following faults can be detected (individually for each output): - short to UBatt: (SCB/overload) can be detected when switches are On state - short to ground: (SCG) can be detected when switches are Off state - open load: (OL) can be detected when switches are Off state - over-temperature: (OT) will only be detected when switches are On state The fault conditions SCB, SCG and OL will not be stored until an integrated filtering time is expired (please note for PWM application ). If, at one output, several errors occur in a s e- quence, always the last detected error will be stored (with filtering time). All fault conditions are encoded in two bits per switch and are stored in the corresponding SPI registers. Additio - nally there are two central diagnostic bits: one especially for over-temperature (latched result of an OR-operation out of the 6 signals of the temperature sensor) and one for fault occu r- rence at any output. A fault that has been detected and stored in the fault registe r must not be replaced by o.k.-state (11) unless it is read out by the RD_DIAG command sent by the micro- controller or an internal or external reset has been applied. I.e. the fault register will be cleared only by the RD_DIAG command. PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 6 are high active PRG = Low (GND): Parallel inputs Channel 1 to 6 are low active. If the parallel input pins are not connected (independent of high or low activity) , channels 1 to 6 are switched OFF. PRG pin itself is internally pulled down when it is not connected. 5) The integrated protection functions prevent device destruction under fault conditions and may not be used in normal operation or permanently.

V2.3 Page 2009-11-18 8 The effect of the integrated under-voltage detection is similar to the effect of an external reset at pin Reset (except low current consumption): - locks all power switches regardless of their input signals - clears the fault registers - resets SPI control register Parallel Connection of Power Stages The power stages which are connected in parallel have to be switched on and off simultan e- ously. In case of overload the ground current and the power dissipation are increasing. The applic a- tion has to take into account that all maximum ratings are observed (e.g. operating temper a- ture TJ and total ground current IGND, see Maximal Ratings). The maximum current limitation value (or overload detectio n threshold) of the parallel co n- nected power stages is the summation of the corresponding maximum values of the power Max. Nominal Current Max. Clamping Energy On Resistance 2 power stages of the same type (see note 1) (Imax,OUTx+Imax,OUTy) x 0.9 0.8 x (Ex + Ey) yOUTxONxR ,,5.0 3 power stages of the same type (see note 1,2) (Imax,OUTx+Imax,OUTy+ Imax,OUTz) x 0.8 0.7 x (Ex + Ey + Ez) zyOUTxONxR ,,,34.0 2 power stages with the same clamping voltage, but different nominal current (see note 3) (Imax,OUTx+Imax,OUTy) x 0.8 Min (Eclpx , Eclpy) OUTyONOUTxON OUTyONOUTxON RR xRR Note 1: Power stages of the same type have the same nominal current Note 2: Only for 3A power stages Note 3: Parallel connection of power stage type 3A/53V with type 1.5A/53V SPI Interface The serial SPI interface makes possible communication between TLE6232 and the microco n- troller. TLE 6232 GP always works in slave mode whereas the microcontroller provides the master function. The maximum baud rate is 5MBaud. Applying a chip select signal at CS and setting bit 7 and bit 6 of the instruction byte to „1“ and „0“ TLE 6232 GP is selected by the SPI master. SI is the data input (Signal In), SO the data output (Signal Out). Via SCLK (Serial Clock Input) the SPI clock is given by the master.

V2.3 Page 2009-11-18 9 SPI Signal Description CS - Chip Select. The system microcontroller selects the TLE 6232 GP by means of the CS pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice versa. CS High to Low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - SO changes from high impedance state to logic high or low state corresponding to the SO bits CS Low to High transition: - transfer of SI bits from shift register into output buffers - reset of diagnosis register To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition of CS. When CS is in a logic high state, any sign als at the SCLK and SI pins are ignored and SO is forced into a high impedance state. SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE 6232 GP. The serial input (SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever chip select CS makes any tran sition. The number of clock pulses will be counted during a chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were counted during CS is active. SI - Serial Input. Serial data bits are shifted in at th is pin, the most significant bit first. SI info r- mation is read in on the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the output stages. The input data consists of two bytes - a "control b yte” followed by a "data byte". The control byte contains the information as to whether the data byte will be accepted or ignored (see d i- agnostics section). The data byte contains the input information for the six channels. A logic high level at this pin ( within the data byte) will switch on the power switch, provided that the corresponding parallel input is also switched on ( AND-operation for channel 1 to 6). SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most signific ant bit first. SO is in a high impedance state until the CS pin goes to a logic low state. New dia g- nostic data will appear at the SO pin following the rising edge of SCLK. RESET- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs OFF. An internal pull -up structure is provided on chip. In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing from1“ and „0“ the data output S O remains into tri-state.

V2.3 Page 2009-11-18 10 SPI Interface SPI Communication A SPI communication starts with a SPI instruction (SI control word) sent from the controller to TLE 6232 GP. Simultaneously the device sends the first SO byte back to the µC. During a writin g cycle the controller sends the data after the SPI instruction, beginning with the MSB. During a reading cycle, after having received the SPI instruction, TLE 6232 GP sends the corresponding data to the controller, also starting with the MSB. The SPI Interface consists of three register: - MUX_REG: 8-bit (1 byte) length for parallel operation mode (IN1 ... IN6 enabled or not) CS SCLK SPI Control: SO SCK SI CS Power Stages 1...6 State Machine Shift Register Power Stages 1...6 MUX_REGSCON_REG Clock Counter Control Bits Parity Generator Power Stages 1...6 DIA_REG

V2.3 Page 2009-11-18 11 - SCON_REG: 8-bit (1 byte) length for serial control of the outputs (serial data bits) - DIAG_REG: 16-bit (2 byte) length. Contains the diagnostic information (2 bits per cha n- nel), a common over-temperature bit and a common fault bit. Registers MUX_REG and SCON_REG are writeable as well as readable from the microco n- troller. The DIAG_REG can only be read from the µC. This leads to five different control bytes which are recognized by the IC. The following table shows the different modes. MSB LSB MSB LSB WR_SCON SI: SO: H L L H H L X X Z Z F OT DIA6 DIA5 D6 D5 D4 D3 D2 D1 X X DIA4 DIA3 DIA2 DIA1 Write to SCON Register. RD_SCON SI: SO: H L L H L H X X Z Z F OT DIA6 DIA5 X X X X X X X X SCON6 .. . SCON1 H H Read SCON Register WR_MUX SI: SO: H L H L H L X X Z Z F OT DIA6 DIA5 M6 M5 M4 M3 M2 M1 X X DIA4 DIA3 DIA2 DIA1 Write to MUX Register. RD_MUX SI: SO: H L H L L H X X Z Z F OT DIA6 DIA5 X X X X X X X X MUX6 . . MUX1 H H Read MUX Register RD_DIAG SI: SO H L L L L L X X Z Z F OT DIA6 DIA5 X X X X X X X X DIA4 DIA3 DIA2 DIA1 Read DIAG Register SI Control Byte SI Data Byte Note: ’X’ means ’don’t care’, because data will be ignored ’Dx’ represents the serial data bits, either being H (= OFF) or L (= ON) ’Mx’ enables parallel control of channel x H (=parallel) or L (=serial) ’Z’ means tri-state ’F’ is the common fault flag ’OT’ is the common over-temperature flag ’DIAx’ is the 2 bit diagnosis information per channel All other possible control bytes will lead to an ignorance of the data bits, but the full diagnosis information (like RD_DIAG command) is provided at the SO line. A reset of all fault registers (and OT bit) the will only be done if the RD_DIAG command was clocked in. Characteristics of the SPI Interface If the slave select signal at CS is High or bit 7 and bit 6 of the instruction byte differ from „1“ and „0“, the state machine is set on default condition, i.e. the state machine expects an i n- struction. If the 5V-reset (RESET) is active, the SPI output SO is switched into tri-state. In order to increase the possible number of SPI participants on one and the same CS signal, bits 7 and 6 of the instruction byte are fixed as shown above. While receiving the first two bits of the instruction byte the data output SO has to be in tri-state. After having received the first two bits TLE6232 has to decide if it is addressed (bit 7 = high, bit 6 = low). In this case the remaining 6 bits of the instruction byte and the data byte are accepted and th e diagnostic feedback respectively the data byte content (MUX, SCON) is sent to the microcontroller. Oth- erwise instruction and data bits are rejected and SO remains in tri-state.

V2.3 Page 2009-11-18 12 On a reading access the bit pattern of the data byte at the SPI input SI will be ignored. The first SO byte sent out simultaneously by the TLE 6232 GP always contains the common fault bit, the over-temperature bit and the diagnostic information of channels 6 and 5 (2 bits each). Depending on the SI control byte, the second SO byte contains the requested information. - Read back of SCON_REG (SCON bits 6 to 1 and two high bits) - Read back of MUX_REG (MUX information for channel 6 to 1 and two high bits) - Diagnostic information of channel 4 to 1 (2 bits per channel) On a writing access always the full diagnostic information of the 6 channels (2 bit per channel) and the over-temperature and common fault bit is performed. Invalid instruction/access: An instruction is invalid, if the following condition is fulfilled: - an unused instruction code is detected (see tables with SPI instructions). If an invalid instruction is detected, a writing access on a register of TLE6232 GP is not allow - wed. In addition an access is invalid if the number of SPI clock pulses counted during active CS differs from exactly 16 clock pulses (falling edges are counted). - On a writing access the received data is only taken over into the internal registers and - the fault register is only cleared by the RD_DIAG command, if exactly 16 SPI clock pulses were counted while CS active. Writing access / 8 bit + 8 bit resp. SPI Instruction SS SI SO MSB Data/8 Bit SS DIA4 DIA3 DIA2 DIA1 MSB MSB ZZ F OT DIA6 DIA5 1 0 --- --- SPI Instruction SI SO MSB XXXX XXXX MSB MSB ZZ OT DIA6 DIA5F 1 0 --- --- Reading access / 8 bit + 8 bit Data/8 Bit

V2.3 Page 2009-11-18 13 Serial/Parallel Control of the Power Stages 1...6 (SPI-Instructions: WR_MUX, RD_MUX, WR_SCON, RD_SCON) The following table shows the truth table for the control of the power stages 1...6. The register MUX_REG prescribes parallel or serial control of the power stages. The register SCON_REG prescribes the state of the power stage in case of serial control. RST PRG INx MUXx SCONx Output OUTx of Power Stage x, x = 1..6

0 X X X X OUTx off

1 X X 0 0 Serial Control: OUTx on

1 X X 0 1 Serial Control: OUTx off

1 0 0 1 X Parallel Control: OUTx on 1 0 1 1 X Parallel Control: OUTx off 1 1 0 1 X Parallel Control: OUTx off 1 1 1 1 X Parallel Control: OUTx on Note: Serial Data bits are low active. Parallel Inputs are high or low active depending on the PRG pin. Description of the SPI Registers Register: MUX_REG 7 6 5 4 3 2 1 0 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 1 1 State of Reset: FFH Access by Controller: Read/Write Bit Name Description

7 MUX6 Serial or parallel control of power stage 6

6 MUX5 Serial or parallel control of power stage 5

5 MUX4 Serial or parallel control of power stage 4

4 MUX3 Serial or parallel control of power stage 3

3 MUX2 Serial or parallel control of power stage 2

2 MUX1 Serial or parallel control of power stage 1

1-0 No function: HIGH on reading Register: SCON_REG 7 6 5 4 3 2 1 0 SCON6 SCON5 SCON4 SCON3 SCON2 SCON1 1 1 State of Reset: FFH Access by Controller: Read/Write Bit Name Description

7 SCON6 State of serial control of power stage 6

6 SCON5 State of serial control of power stage 5

5 SCON4 State of serial control of power stage 4

4 SCON3 State of serial control of power stage 3

3 SCON2 State of serial control of power stage 2

2 SCON1 State of serial control of power stage 1

1-0 No function: HIGH on reading Diagnostics/Encoding of Failures

V2.3 Page 2009-11-18 14 Description of the SPI Registers (SPI Instructions: RD_DIAG) Register: DIAG_REG1 7 6 5 4 3 2 1 0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 State of Reset: FFH Access by Controller: Read only Bit Name Description 7-6 DIA4 Diagnostic Bits of power stage 4 5-4 DIA3 Diagnostic Bits of power stage 3 3-2 DIA2 Diagnostic Bits of power stage 2 1-0 DIA1 Diagnostic Bits of power stage 1 Note: This byte is always clocked out (second SO-byte), except the SI control words says: RD_SCON or RD_MUX. But: The content of the fault register will only be deleted i f the control command ’RD_DIAG’ was clocked in and 16 clock pulses were counted. Register: DIA_REG2 7 6 5 4 3 2 1 0 Z Z F OT ST11 ST10 ST9 ST8 State of Reset: FFH Access by Controller: Read only Bit Name Description 7-6 Z Bit 7 and 6 are always tri-state

5 F Common error flag

4 OT Common over-temperature flag

3-2 DIA6 Diagnostic Bits of power stage 6 1-0 DIA5 Diagnostic Bits of power stage 5 Encoding of the Diagnostic (Status) Bits of the Power Stages ST(2*x-1) ST(2*x-2) State of power stage x x = 1..6 1 1 Power stage o.k. 1 0 Overload, short circuit to battery (SCB) or over-temperature (OT) 0 1 Open load (OL) 0 0 Short circuit to ground (SCG) Note: DIA_REG2 is always clocked out as first byte F, OT Bit = 1: No Fault F, OT Bit = 0: Fault, Over-temperature The over-temperature bit is the latched result of an OR -operation out of the 6 signals of the temperature sensor) The general fault bit shows the fault occurrence at any of the outputs. Reset of the Diagnostic Information The diagnostic information will only be reset after the RD_DIAG command on the rising edge of slave select or a reset signal is applied (RESET = low).

V2.3 Page 2009-11-18 16 Figure 5: Power Outputs Timing is valid for resistive load with parallel and serial control. Rising edge of chip select initiates the switching Application Circuits t t tON tOFF 80% VDS VIN 20% OUT1 OUT2 OUT6 TLE 6232 GP SI SO CLK CS VS VS = 5V RESET GND VBB CLK MTSR MRST P xy µC e.g. C167 IN1 IN6 PRG FAULT 10kC

V2.3 Page 2009-11-18 17 Parallel SPI Configuration Engine Management Application TLE 6232 GP in combination with TLE 6240 GP (16-fold switch) for relays and general pu r- pose loads and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system. From 26 channels in sum 18 can be controlled direct in parallel for PWM applications. SI CLK SO SI CLK SO CS CS MTSR MRST CLK P x.y P x.1-6 P x.y P x.1-4 µC C167

4 PWM

6 PWM

8 PWM

16-foldP x.y P x.1-8

V2.3 Page 2009-11-18 18 Package and Ordering Code (All dimensions in mm) PG-DSO 36 TLE 6232 GP Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be co m- pliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb -free soldering according to IPC/JEDEC J-STD-020).

V2.3 Page 2009-11-18 19

Revision History

V2.2 -> V2.3

18.11.2009 Package changed to PG-DSO-36

V2.1 -> V2.2 Ordering Code / Q-Nr. removed V2.0 -> V2.1

05.04.2007 Layout Changes, correct green package name implemented P -DSO-

36-12 à PG-DSO-36-26 V1.2 -> V2.0

05.03.2007 Changes to Green Product Version:

• AEC, RoHS Logo and Feature List content added - Package Name P-DSO -> PG-DSO - Change History added - Disclaimer re-newed V1.2 08.10.2003 Initial Version of “grey” product

V2.3 Page 2009-11-18 20 Edition 2007-04-17 Published by Infineon Technologies AG

81726 Munich, Germany

© 11/19/09 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteris- tics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabili- ties of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest In- fineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other per- sons may be endangered.