TLD5S10AH TSC | Alldatasheet

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Technical content

H TLD5S43A H Tai wan Semiconductor Version: B 180 00W, 1 V V Surface Mount Transient Voltage Suppressor

FEATURES

T J =175 capability suitable for high reliability and automotive requirement Moisture sensitivity level: level 1, per J STD 020 Compliant to RoHS directive 2011/65/EU and in accordance to WEEE 2002/96/EC Halogen free according to IEC 61249 Meets ISO7637 and ISO16750 surge specification s (varied by test condition s

APPLICATIONS

Surge Protection. Automotive Load Dump Surge Protection. MECHANICAL DATA Case: DO 218AB Molding compound meets UL 94V 0 flammability rating Terminal: Matte tin plated leads, solderable per J STD 002 Meet JESD 201 class whisker test Polarity: Uni directional Weight: .677 g (approximately) KEY PARAMETERS P ARAMETER VALUE UNIT V WM V V BR 52.8 V P PPM 10x1,000 μ s 3600 W P PPM 10x10,000 μ s 2800 W T J MAX 175 Package DO 218AB DO 218AB ABSOLUTE M AXIMUM RATINGS T A unless otherwise noted P ARAMETER S YMBOL VALUE UNIT Non repetitive peak impulse power dissipation with μ s waveform P PPM 3600 W Non repetitive peak impulse power dissipation with μ s waveform (1) P PPM 2800 W Steady state power dissipation (2) P D W Forward Voltage at I F 100 A (3) V F MAX V Peak forward surge current, 8.3 ms single half sine wave I F SM 500 A Junction temperature T J 55 to +175 Storage temperature T STG 55 to +175 Notes N on repetitive c urrent p ulse p er Fig. Units mounted on PCB ( mm x mm Cu pad test board Pulse test with PW=0.3 ms

H TLD5S43A H Tai wan Semiconductor Version: B 180 THERMAL PERFORMANCE P ARAMETER S YMBOL TYP. UNIT Junction to case thermal resistance per diode R Ө J C Junction to lead thermal resistance per diode R Ө J L 10.0 Junction to ambient thermal resistance per diode R Ө J A Thermal Performance Note: Units mounted on PCB ( mm x mm Cu pad test board) ELECTRICAL SPECIFICATIONS T A unless otherwise noted Part number Marking code Breakdown voltage V BR at I T (V) (Note 1) Test current I T (mA) Working stand off voltage V WM (V) Maximum blocking leakage current I R at V WM µ (Note 1) Maximum peak impulse current I PP M (A) tp =10/1000 μ s Maximum clamping voltage V C at I PP M (V) Min. Max. TLD S10A H TLD S10A 11.1 12.3 5.0 10.0 212 17.0 TLD A H TLD A 12.2 13.5 5.0 11.0 198 18.2 TLD A H TLD A 13.3 14.7 5.0 12.0 181 19.9 TLD A H TLD A 14.4 15.9 5.0 13.0 167 21.5 TLD A H TLD A 15.6 17.2 5.0 14.0 155 23.2 TLD A H TLD A 16.7 18.5 5.0 15.0 148 24.4 TLD A H TLD A 17.8 19.7 5.0 16.0 138 26.0 TLD A H TLD A 18.9 20.9 5.0 17.0 130 27.6 TLD A H TLD A 20.0 22.1 5.0 18.0 123 29.2 TLD S H TLD S 22.2 24.5 5.0 20.0 111 32.4 TLD S A H TLD S A 24.4 26.9 5.0 22.0 101 35.5 TLD S A H TLD S A 26.7 29.5 5.0 24.0 38.9 TLD S A H TLD S A 28.9 31.9 5.0 26.0 42.1 TLD S A H TLD S A 31.1 34.4 5.0 28.0 45.4 TLD S A H TLD S A 33.3 36.8 5.0 30.0 48.4 TLD S A H TLD S A 36.7 40.6 5.0 33.0 53.3 TLD S A H TLD S A 40.0 44.2 5.0 36.0 58.1 TLD S A H TLD S A 44.4 49.1 5.0 40.0 64.5 TLD S A H TLD S A 47.8 52.8 5.0 43.0 69.4 Note: Pulse test with PW= ms

ORDERING INFORMATION

(Note PACKAGE PACKING TLD5SxxAH MA G DO 218AB 750 / 13 Plastic reel Note: x " defines voltage from V ( TLD5S10AH) to 43 V ( TLD5S43 AH)

H TLD5S43A H Tai wan Semiconductor Version: B 180 CHARACTERISTICS CURVES A = 25°C unless otherwise noted) Fig.1 Power Derating Curve Fig.2 Load Dump Power Characteristics (10ms Exponential Waveform Fig.3 Clamping Power Pulse Waveform Fig. Reverse Power Capability Fig. Typical Transient Thermal Impedance Fig. Typical Junction Capacitance 100 125 150 175 Heat sink 16mm x 16mm Cu pad test board 500 1000 1500 2000 2500 3000 3500 100 125 150 175 100 150 INPUT PEAK PULSE CURRENT (%) t TIME (ms) t d Peak value I PPM t r =10μs Half value I PPM Pulse width (t d ) is defined as the point where the peak current decays to 50% of I PPM 1000 10000 100 0.01 0.1 100 0.01 0.1 100 R θ JC R θ JA 100 1000 10000 100000 Measured at Zero Bias Measured at Stand Off Voltage V WM f = 1MHz V sig = 50mV P P LOAD DUMP POWER (W) R EVERSE S URGE P OWER (W) P ULSE W IDTH (ms) POWER DISSIPATION (W CASE TEMPERATURE (°C) CASE TEMPERATURE (°C) PULSE DURATION (s) T RANSIENT THERMAL IMPEDANCE (°C/W) JUNCTION CAPACITANCE pF STAND OFF VOLTAGE, V WM (V)

H TLD5S43A H Tai wan Semiconductor Version: B 180 PACKAGE OUTLINE DIMENSIONS DO 218AB SUGGESTED PAD LAYOUT MARKING DIAGRAM P/N Marking Code YW W = Date Code F = Factory Code

H TLD5S43A H Tai wan Semiconductor Version: B 180 Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, cop yright, or other intellectual property right. The products shown herein are not designed for use in medical, life saving, or life sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and a gree to fully indemnify TSC for any damages resulting from such improper use or sale.