TLD2326EL

TLD2326EL_15 INFINEON | Alldatasheet

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Technical content

Rev. 1.1, 2015-03-24 TLD2326EL

3 Channel High Side Current Source

Infineon ® LITIX TM Basic

Data Sheet 2 Rev. 1.1, 2015-03-24 TLD2326EL

TLD2326EL PG-SSOP14 TLD2326EL Data Sheet 3 Rev. 1.1, 2015-03-24

Features

• 3 Channel device with integrated output stages (current sources), optimized to drive LEDs
• Output current up to 120mA per channel
• Low current consumption in sleep mode
• PWM-operation supported via VS- and EN-pin
• Output current adjustable via external low power resistor and possibility to connect PTC resistor for LED protection during over temperature conditions
• Dynamic overhead control
• Reverse polarity protection
• Overload protection
• Undervoltage detection
• Open load and short circuit to GND diagnosis
• Wide temperature range: -40 °C < T j < 150 °C
• PG-SSOP14 package with exposed heatslug
• Green Product (RoHS compliant)
• AEC Qualified

Description

TM Basic TLD2326EL is a three channel high side driver IC with integrated output stages. It is designed to control LEDs with a current up to 120 mA. In typical au tomotive applications the device is capable to drive i.e. 3 red LEDs per chain (total 9 LEDs) with a current up to 60mA, which is limited by thermal cooling aspects. The output current is controlled practically independent of load and supply voltage changes. Table 1 Product Summary Operating voltage VS(nom) 5.5 V… 40 V Maximum voltage VS(max) VOUTx(max) 40 V Nominal output (load) current IOUTx(nom) 60 mA when using a supply voltage range of 8V - 18V (e.g. Automotive car battery). Currents up to IOUT(max) possible in applications with low thermal resistance RthJA Maximum output (load) current IOUTx(max) 120 mA; depending on thermal resistance RthJA

Data Sheet 4 Rev. 1.1, 2015-03-24 TLD2326EL Overview Protective functions - ESD protection - Under voltage lock out - Over Load protection - Over Temperature protection - Reverse Polarity protection Diagnostic functions - OL detection - SC to Vs (indicated by OL diagnosis) - SC to GND detection

Applications

Designed for exterior LED lighting applications such as tail/brake light, turn indicator, position light, side marker,... The device is also well suited for inte rior LED lighting applications such as ambient lighting (e .g. RGB), interior illumination and dash board lighting. Output current accuracy at RSETx = 12 kΩ kLT 750 ± 7% Current consumption in sleep mode IS(sleep,typ) 0.1 µA Table 1 Product Summary

Data Sheet 5 Rev. 1.1, 2015-03-24

2 Block Diagram

Figure 1 Basic Block Diagram Output control OUT2 Internal supply Thermal protection Current adjust TLD2326EL GND EN VS IN_SET2 DC/DC control FB OUT3 OUT1 IN_SET1 IN_SET3

Data Sheet 6 Rev. 1.1, 2015-03-24 TLD2326EL Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration TLD2326EL EP NC FB OUT3 OUT2EN OUT1NC VS VS IN_SET3 IN_SET2 IN_SET1 8N C GND

Data Sheet 7 Rev. 1.1, 2015-03-24

3.2 Pin Definitions and Functions

1, 2 VS – Supply Voltage; battery supply, connect a decoupling capacitor (100 nF - 1 µF) to GND 3E NI Enable pin 4N C – Pin not connected

5 IN_SET3 I/O Input / SET pin 3; Connect a low power resistor to adjust the output current

6 IN_SET2 I/O Input / SET pin 2; Connect a low power resistor to adjust the output current

7 IN_SET1 I/O Input / SET pin 1; Connect a low power resistor to adjust the output current

8N C – Pin not connected 9G N D – 1) Ground 1) Connect all GND-pins together.

10 FB O Feedback Output

11 OUT1 O Output 1

12 OUT2 O Output 2

13 OUT3 O Output 3

14 NC – Pin not connected

GND – 1) Exposed Pad; connect to GND in application

Data Sheet 8 Rev. 1.1, 2015-03-24 TLD2326EL General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) 1) Not subject to production test, specified by design Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. Voltages

4.1.1 Supply voltage

VS -16 40 V –

4.1.2 Input voltage EN VEN -16 40 V –

4.1.3 Input voltage EN related to VS VEN(VS) VS - 40 VS + 16 V –

4.1.4 Input voltage EN related to VOUTx

-16 40 V –

4.1.5 Output voltage VOUTx -1 40 V –

4.1.6 Power stage voltage

VPS = VS - VOUTx VPS -16 40 V – 4.1.7 IN_SETx voltage VIN_SETx -0.3 6 V – 4.1.8 Feedback voltage VFB -0.3 40 V – Currents

4.1.9 IN_SETx current IIN_SETx –

mA – Diagnosis output 4.1.10 Feedback current IFB –0 . 5 m A –

4.1.11 Output current IOUTx –1 3 0 m A –

4.1.12 Junction temperature Tj -40 150 °C–

4.1.13 Storage temperature Tstg -55 150 °C–

4.1.14 ESD resistivity to GND VESD -2 2 kV Human Body

Model (100 pF via 1.5 kΩ)2) 2) ESD susceptibility, Human Body Model “HB M” according to ANSI/ESDA/JEDEC JS-001-2011

4.1.15 ESD resistivity all pins to GND VESD -500 500 V CDM 3)

3) ESD susceptibility, Charged Device Model “CDM” according to JESD22-C101E

4.1.16 ESD resistivity corner pins to GND VESD -750 750 V CDM 3)

General Product Characteristics Data Sheet 9 Rev. 1.1, 2015-03-24

4.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal Resistance

Pos. Parameter Symbol Limit Values Unit Conditions Min. Max.

4.2.17 Supply voltage range for

VS(nom) 5.5 40 V –

4.2.18 Power on reset threshold VS(POR) –5V VEN = VS

RSETx =1 2k Ω IOUTx =8 0 %IOUTx(nom) VOUTx =2 . 5V

4.2.19 Junction temperature Tj -40 150 °C–

Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

4.3.1 Junction to Case RthJC –81 0 K / W 1) 2)

1) Not subject to production test, specifi ed by design. Based on simulation results. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed Pad are fixed to ambient temperature). Ta = 85°C, Total power dissipation 1.5 W.

4.3.2 Junction to Ambient 1s0p board RthJA1

K/W 1) 3) Ta =8 5° C Ta = 135 °C 3) The RthJA values are according to Jedec JESD51-3 at natural convection on 1s0p FR4 board. The product (chip + package) distributed statically and homogenously over all power stages.

4.3.3 Junction to Ambient 2s2p board RthJA2

K/W 1) 4) Ta =8 5° C Ta = 135 °C 4) The RthJA values are according to Jedec JESD51-5,-7 at natural convection on 2s2p FR4 board. The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (outside 2 x 70 µm Cu, inner 2 x 35µm Cu). Where applicable, a thermal via array under the exposed pad contacted the first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all power stages.

Data Sheet 10 Rev. 1.1, 2015-03-24 TLD2326EL EN Pin 5E N P i n The EN pin is a dual function pin: Figure 3 Block Diagram EN pin Note: The current consumption at the EN-pin IEN needs to be added to the total device current consumption. The total current consumption is the sum of the currents at the VS-pin IS and the EN-pin IEN.

5.1 EN Function

If the voltage at the pin EN is below a threshold of VEN(off) the LITIXTM Basic IC will enter Sleep mode. In this state all internal functions are switched off, the current consumption is reduced to IS(sleep). A voltage above VEN(on) at this pin enables the device after the Power on reset time tPOR. Figure 4 Power on reset VEN EN Output Control Internal Supply VEN t t 80 % tPORIOUT 100 % t VS

Data Sheet 11 Rev. 1.1, 2015-03-24

5.2 Internal Supply Pin

The EN pin can be used to supply the internal logic. There are two typical application conditions, where this feature can be used: 1) In “DC/DC control Buck” configurations, where the voltage Vs can be below 5.5V. 2) In configurations, where a PWM signal is applied at the Vbatt pin of a light module. The buffer capacitor CBUF is used to supply the LITIX TM Basic IC during Vbatt low ( Vs low) periods. This feature can be used to minimize the to be considered. The capacitor can be calculated using the following formula: (1) See also a typical application drawing in Chapter 10. Figure 5 External circuit when applying a fast PWM signal on VBATT CBUF tLOW max() IEN LS() VS VD1– VSP O R()– RSET CBUF VBATT GND Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1 LITIXTM Basic

Data Sheet 12 Rev. 1.1, 2015-03-24 TLD2326EL EN Pin Figure 6 Typical waveforms when applying a fast PWM signal on VBATT The parameter tON(VS) is defined at Pos. 9.2.11. The parameter tOFF(VS) depends on the load and supply voltage VBATT characteristics.

5.3 EN Unused

In case of an unused EN pin, there are two different ways to connect it:

5.3.1 EN - Pull Up to VS

The EN pin can be connected with a pull up resistor (e.g. 10 k Ω) to Vs potential. In this configuration the LITIXTM Basic IC is always enabled.

5.3.2 EN - Direct Connection to VS

The EN pin can be connected directly to the VS pin (I C always enabled). This configuration has the advantage (compared to the configuration described in Chapter 5.3.1) that no additional external component is required. VBATT t t 20 % 80 % tON(VS)IOUT 100 % VEN t Switch off behavior depends on VBATT and load characteristics

Data Sheet 13 Rev. 1.1, 2015-03-24

5.4 Electrical Characteristics Internal Supply / EN Pin

Electrical Characteristics Internal Supply / EN pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSETx =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

5.4.1 Current consumption,

IS(sleep) –0 . 12µ A 1) VEN = 0.5 V Tj < 85 °C VS = 18 V VOUTx = 3.6 V

5.4.2 Current consumption,

IS(on) 1.7 1.0 1.75 mA 2) IIN_SET = 0µ A Tj < 105 °C VS = 18 V VOUTx = 3.6V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin

5.4.3 Current consumption,

IN_SETx IS(dis,IN_SET) 1.65 0.9 1.7 mA 2) VS = 18 V Tj < 105 °C VIN_SETx = 5 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin

5.4.4 Current consumption,

active mode in single fault detection condition IS(fault) 6.0 4.9 5.9 mA 2) VS = 18 V Tj < 105 °C RSET1 = 12 kΩ RSET2,3 = unconnected VOUTx = 18 V or 0 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin

5.4.5 Current consumption,

active mode in double fault detection condition and one output disabled via IN_SETx IS(dfault) 9.0 8.4 9.0 mA 2) VS = 18 V Tj < 105 °C RSET1,2 = 12 kΩ RSET3 = unconnected VOUTx = 18 V or 0 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin 5.4.6 Power-on reset delay time 3) tPOR –– 2 5 µ s 1) VS = VEN =0 → 13.5 V VOUTx(nom) = 3.6 ± 0.3V IOUTx = 80% IOUTx(nom)

Data Sheet 14 Rev. 1.1, 2015-03-24 TLD2326EL EN Pin

5.4.7 Required supply voltage for

VS(on) –– 4V VEN = 5.5 V VOUTx = 3 V IOUTx =5 0 % IOUTx(nom)

5.4.8 Required supply voltage for

VS(CC) –– 5 . 2 V VEN = 5.5 V VOUTx = 3.6 V IOUTx ≥ 90% IOUTx(nom) 5.4.9 EN turn on threshold VEN(on) –– 2 . 5 V – 5.4.10 EN turn off threshold VEN(off) 0.8 – – V –

5.4.11 EN input current during low

IEN(LS) –– 2 . 4 m A 1) VS = 4.5 V Tj < 105 °C VEN = 5.5 V

5.4.12 EN high input current IEN(H)

0.1 0.1 2.05 0.45 mA Tj < 105 °C VS = 13.5 V, VEN = 5.5 V VS = 18 V, VEN = 5.5 V VS = VEN = 18 V 1) VS = 18 V, REN = 10 kΩ between VS and EN-pin 1) Not subject to production test, specified by design 2) The total device current consumption is the sum of the currents IS and IEN(H), please refer to Pos. 5.4.12 3) See also Figure 4 Electrical Characteristics Internal Supply / EN pin (cont’d) Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSETx =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

Data Sheet 15 Rev. 1.1, 2015-03-24 6F B P i n The following block diagram shows the feedback pin functionality. Figure 7 Block Diagram FB pin

6.1 DC/DC Control

With the FB pin the LITIXTM Basic IC realizes the dynamic overhead control. The IC provides a voltage feedback to an external DC/DC converter. Using the circuit shown in Figure 17 it is possible to adjust the DC/DC output voltage in a way that the voltage drop over the output st ages of the LITIX TM Basic IC is minimized - dynamic overhead control. This leads to a significant reduction of the overall driver’s power dissipation and an increased system efficiency. Figure 17 gives an application example, how different light functions can be controlled using a µC, if an open load diagnosis per LED chain is required. Note: For correct output current control and dynamic overhead control the parameters as specified in Pos. 6.2.1 the FB regulation voltage VFB(nom). The resistor RFB(PD) can be dimensioned by applying equations Equation (2) and Equation (3). The following parameters are required:

• VOUT represents the maximum LED loads forward voltage, i.e. number of LEDs multiplied with the maximum LED forward voltage. Temperature drifts of the LED’s forward voltage needs to be considered!
• VBO represents the DC/DC output voltage, which is predefined by the feedback resistors (Figure 17: RFB1, RFB2, RFB3). Please refer to the according DC/DC device data sheet for the dimensioning of those resistors.
• nlen represents the numbers of LITIXTM Basics using the longest LED-chains (e.g. if there are 3 devices connected to one DC/DC converter and two devices using LED chains with 7 LEDs and one device is used with LED chain lengths of 6 LEDs the according nlen =2 . )
• β represents the DC gain of the external bipolar transistor, which is connected to the DC/DC’s feedback pin. (2) (3) FB OUT1 OUT2 OUT3 Output voltage feedback IFB(SOC) RFB PD min,() min VOUT 0.5 V– 41 0 5– A⋅ nlen VBO VOUT–1 . 1 V– nlen RFB PD max,() VOUT 1.1 V– VBO VOUT– RFB1 β 1+

Data Sheet 16 Rev. 1.1, 2015-03-24 TLD2326EL FB Pin

6.2 Electrical Characteristics FB Pin

Electrical Characteristics FB pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

6.2.1 FB regulation voltage VFB(nom) (VOUT -

1)*0.9 VOUT -1 – V IFB(SOC) = 25 µA

6.2.2 FB operating voltage at

VPS(FB) = VS - VOUTx VPS(FB) –– 1 0 V 1) 1) Not subject to production test, specified by design

IN_SETx Pin Data Sheet 17 Rev. 1.1, 2015-03-24

7 IN_SETx Pin

The IN_SET pin is a multiple function pin for output current definition, input and diagnostics: Figure 8 Block Diagram IN_SET pin

7.1 Output Current Ad justment via RSET

The output current of each channel can be adjusted independently. The current adjustment can be done by placing a low power resistor (RSET) at the IN_SETx pin to ground. The dimensioning of the resistor can be done using the formula below: (4) defined by the resistor itself and the reference voltage VIN_SET(ref), which is applied to the IN_SET during supplied device.

7.2 Smart Input Pin

The IN_SETx pin can be connected via RSET to the open-drain output of a µC or to an external NMOS transistor as described in Figure 9. This signal can be used to turn off t he output stages of the IC. A minimum IN_SET current of IIN_SET(act) is required to turn on the output stages. This feature is implemented to prevent glimming of LEDs caused by leakage currents on the IN_SET pin, see Figure 11 for details. In addition, the IN_SET pin offers the diagnostic feedback information. In case of a fault event the IN_SET voltage is increased to VIN_SET(OL/SC) Note: If one output has a present fault (open load or short circuit) and one or both of the other channels are dimmed via PWM at the IN_SET-pins a short spike to VIN_SET(OL/SC) is possible. Please refer to Chapter 8.3. IIN_SET VIN_SET(OL/SC) IN_SET GND VIN_SET Logic RSET k IOUT

Data Sheet 20 Rev. 1.1, 2015-03-24 TLD2326EL Load Diagnosis

8 Load Diagnosis

8.1 Open Load

An open load diagnosis feature is integrated in the TLD23 26EL driver IC. If there is an open load on one of the outputs, the respective output is turned off. The potential on the IN_SET pin rises up to VIN_SET(OL/SC). This high voltage can be used as input signal for an µC as shown in Figure 9. The open load status is not latched, as soon as the open load condition is no longer present, the output stage will be turned on again. An open load condition is detected, if the voltage drop over the output stage VPS is below the threshold according Pos. 8.4.6 and a filter time of tOL is passed. Figure 13 IN_SET behavior during open load condition

8.2 Short Circuit to GND detection

The TLD2326EL has an integrated SC to GND detection. If th e output stage is turned on and the voltage at the output falls below VOUT(SC) the potential on the IN_SET pin is increased up to VIN_SET(OL/SC) after tSC. This condition is not latched. For detecting a normal condition after a short circuit detection an output current according to IOUT(SC) is driven by the channel. t VS –V PS( OL) tOL VOUT t VF VIN_SET (r e f ) VIN _SET (OL/SC) VS VIN_SET open load occurs open load disappears tIN_SET (reset)

Data Sheet 21 Rev. 1.1, 2015-03-24 Figure 14 IN_SET behavior during short circuit to GND condition with ST connected to GND and VDEN > VDEN(act)

8.3 Double Fault Conditions

The TLD2326EL allows the diagnosis of each channel separately. The diagnosis filter times tOL and tSC (Pos. 8.4.5 and Pos. 8.4.8) are valid only for the channel, which diagnoses fi rst the fault condition. For the other channel or channels with a subsequential fault the di agnosis is reported immediately without the diagnosis filter time, if the filter time tOL has been elapsed for the channel with the first faul t. During activation via IN_SET of a non-faulty output, where one channel has already a fault detected, a short spike to VIN_SET(OL/SC) could occur on the channel, which should be activated. Therefore, in general a diagnosis should be done earliest after the diagnosis filter times tOL and tSC to avoid any incorrect diagnosis readout. In the scenario mentioned above the turn on time tON(IN_SET) could be extended. The following figure shows the example behavior, if OUT1 has a fault and OUT2 is operated in PWM-mode. OUT3 is disabled. t VOUT (SC) tSC VOUT VIN_SET t VF VIN _ SET( r ef ) VIN _SET (OL/SC) tIN_SET( reset) short circuit occurs short circuit disappears

Data Sheet 22 Rev. 1.1, 2015-03-24 TLD2326EL Load Diagnosis Figure 15 Example single channel faul t on OUT1 and PWM-operation on OUT2 t VS –V PS( OL) tOL VOUT1 t VF VIN _ SET (r ef ) VIN _ SET( OL/SC) VS VIN_SET 1 open load occurs t VOUT2 t VF VIN _ SET (r ef ) VIN _ SET( OL/SC) VIN_SET2 VOUT ( SC) turn on command IIN_SET1 t IIN_SET2 t VIN_SET( OL/SC) / RSET1 VIN_SET( r e f )/ RSET1 VIN _SET (OL/SC) / RSET 2 VIN _SET (r e f )/ RSET 2

Data Sheet 23 Rev. 1.1, 2015-03-24

8.4 Electrical Characteristics IN _SET Pin and Load Diagnosis

Electrical Characteristics IN_SET pin and Load Diagnosis Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSETx = 12 kΩ, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

8.4.1 IN_SET reference

VIN_SET(ref) 1.19 1.23 1.27 V 1) VOUTx =3 . 6V Tj = 25...115 °C 1) Not subject to production test, specified by design

8.4.2 IN_SET open load/short

VIN_SET(OL/SC) 4– 5 . 5 V 1) VS > 8 V Tj = 25...150 °C VS = VOUTx (OL) or VOUTx = 0 V (SC)

8.4.3 IN_SET open load/short

VIN_SET(OL/SC) 3.2 – 5.5 V 1) VS = 5.5 V Tj = 25...150 °C VS = VOUTx (OL) or VOUTx = 0 V (SC)

8.4.4 IN_SET open load/short

IIN_SET(OL/SC) 0.5 – 2.5 mA 1) VS > 8 V Tj = 25...150 °C VIN_SET = 4 V VS = VOUTx (OL) or VOUTx = 0 V (SC)

8.4.5 OL detection filter time tOL 10 22 35 µs 1) VS >8V

8.4.6 OL detection voltage

VPS(OL) = VS - VOUTx VPS(OL) 0.2 – 0.4 V VS >8V

8.4.7 Short circuit to GND

VOUT(SC) 0.8 – 1.4 V VS >8V

8.4.8 SC detection filter time tSC 10 22 35 µs 1) VS > 8 V

8.4.9 IN_SET diagnosis reset

tIN_SET(reset) –5 2 0 µ s 1) VS > 8 V 8.4.10 SC detection current IOUT(SC) 0.1 2 4.75 mA VS > 8 V VOUTx = 0 V

8.4.11 IN_SET activation

current without turn on of output stages IIN_SET(act) 2 – 15 µA See Figure 11

Data Sheet 24 Rev. 1.1, 2015-03-24 TLD2326EL Power Stage

9 Power Stage

The output stages are realized as high side current sources with a current of 120 mA. During off state the leakage current at the output stage is minimized in order to prevent a slightly glowing LED. To increase the overall output current for high brightness LED applications it is possible to connect two or all three output stages in parallel. The maximum current of each channe l is limited by the power dissipation and used PCB cooling areas (which results in the applications RthJA). For an operating current control loop the supply and output voltages according to the following parameters have to be considered:

• Required supply voltage for current control VS(CC), Pos. 5.4.8
• Voltage drop over output stage during current control VPS(CC), Pos. 9.2.6
• Required output voltage for current control VOUTx(CC), Pos. 9.2.7

9.1 Protection

The device provides embedded protective functions, wh ich are designed to prevent IC destruction under fault conditions described in this data sheet. Fault condit ions are considered as “out side” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.

9.1.1 Over Load Behavior

An over load detection circuit is integrated in the LITIXTM Basic IC. It is realized by a temperature monitoring of the output stages (OUTx). As soon as the junction temperature exceeds the current reduction temperature threshold Tj(CRT) the output current will be reduced by the device by re ducing the IN_SET reference voltage VIN_SET(ref). This feature avoids LED’s flickering during static output overload conditions. Furthermore, it protects LEDs against over temperature, which are mounted thermally close to the de vice. If the device temper ature still increases, th e three output currents decrease close to 0 A. As soon as the device cools down the output currents rise again. Figure 16 Output current reduction at high temperature Note: This high temperature output current reduction is realized by reducing the IN_SET reference voltage voltage (Pos. 8.4.1). In case of very high power loss applied to the device and very high junction temperature the output current may drop down to IOUTx = 0 mA, after a slight cooling down the current increases again.

9.1.2 Reverse Battery Protection

The TLD2326EL has an integrated reverse battery protection feature. This feature protects the driver IC itself, but also connected LEDs. The output reverse current is limited to IOUTx(rev) by the reverse battery protection. Tj IOUT Tj(CRT ) VIN_SET

Data Sheet 25 Rev. 1.1, 2015-03-24 Note: Due to the reverse battery protection a reverse protection diode for the light module may be obsolete. In case of high ISO-pulse requirements and only minor protecting components like capacitors a reverse protection diode may be reasonable. The external protection circuit needs to be verified in the application.

9.2 Electrical Charact eristics Power Stage

Electrical Characteristics Power Stage Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

9.2.1 Output leakage current IOUTx(leak)

µA VEN = 5.5 V IIN_SET = 0µ A VOUTx =2 . 5V Tj = 150 °C 1) Tj = 85 °C

9.2.2 Output leakage current in

IOUTx(leak,B2B) ––5 0 µ A 1) VEN = 5.5 V IIN_SET =0µ A VOUTx = VS = 40 V

9.2.3 Reverse output current -IOUTx(rev) ––1µ A 1) VS = -16 V

Output load: LED with break down voltage <-0 . 6V

9.2.4 Output current accuracy

1)Tj = 25...115 °C VS = 8...18 V VPS = 2 V RSETx = 6...12 kΩ RSETx = 30 kΩ

9.2.5 Output current accuracy

VS = 8...18 V VPS = 2 V RSETx = 6...12 kΩ RSETx = 30 kΩ

9.2.6 Voltage drop over power

stage during current control VPS(CC) = VS - VOUTx VPS(CC) 0.75 – – V 1) VS = 13.5 V RSETx = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSETx)

9.2.7 Required out put voltage for

VOUTx(CC) 2.3 – – V 1) VS = 13.5 V RSETx = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSETx) 9.2.8 Maximum output current IOUT(max) 120 – – mA RSETx = 4.7 kΩ The maximum output current is limited by the thermal conditions. Please refer to

Data Sheet 26 Rev. 1.1, 2015-03-24 TLD2326EL Power Stage 9.2.9 IN_SET turn on time tON(IN_SET) ––1 5 µ s VS = 13.5 V IIN_SET = 0 → 100 µA IOUTx = 80% of (kLT(typ)/RSETx) No OL or SC at other channels 9.2.10 IN_SET turn off time tOFF(IN_SET) ––1 0 µ s VS = 13.5 V IIN_SET =1 0 0→ 0µ A IOUTx = 20% of (kLT(typ)/RSETx) 9.2.11 VS turn on time tON(VS) ––2 0 µ s 1) 2) VEN =5 . 5V RSETx = 12 kΩ VS = 0 → 13.5 V IOUTx = 80% of (kLT(typ)/RSETx)

9.2.12 Current reduction

Tj(CRT) –1 4 0 –° C 1)IOUTx = 95% of (kLT(typ)/RSETx)

9.2.13 Output current during

IOUT(CRT) 85% of kLT(typ)/ RSETx) ––A 1) RSETx =1 2k Ω Tj = 150 °C 1) Not subject to production test, specified by design 2) see also Figure 6 Electrical Characteristics Power Stage (cont’d) Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

Application Information

Data Sheet 27 Rev. 1.1, 2015-03-24 Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 17 System diagram DC/DC cont rol Boost using 3 IN_SET pins Note: This is a very simplified example of an application circuit. The function must be verified in the real application.

10.1 Further Application Information

• For further information you may contact http://www.infineon.com/ Microcontroller (e.g. XC866) FBH FBL OVFB SWO SWCS GND SGND TLD5095 EN / PWMI COMP ST IVCC RFREQ RCOMP CCOMP CIVCC IN VBATT VIN FREQ / SYNC CIN DRV LBO DBO TSW RCS ROVH ROVL CBO RFB1 RFB2 RFB3PWMO VBO RSET2RSET3 RSET1 RSET2RSET3 EN DIAG function A OUT function A DIAG function B OUT function B RFB(PD) 1nF Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET2 DC/DC control FB OUT3 OUT1 IN_SET1 IN_SET3 VIN RSET1 Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET2 DC/DC control FB OUT3 OUT1 IN_SET1 IN_SET3 VIN VBO ** For EMI improvement , if required . CVS =4.7nF CVS =4.7nF LITIXTM Basic LITIXTM Basic

Data Sheet 28 Rev. 1.1, 2015-03-24 TLD2326EL Package Outlines Figure 18 PG-SSOP14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad Dimensions in mm For further information on alternative packages, please visit our website: http://www.infineon.com/packages.

Revision History

Data Sheet 29 Rev. 1.1, 2015-03-24 Revision Date Changes 1.0 2013-08-08 Inital revision of data sheet 1.1 2015-03-19 Updated parameters K LT and KALL in the chapter Power Stage.

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