TLD2131-3EP

TLD2131-3EP INFINEON | Alldatasheet

Document overview

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Technical content

Features

• Triple channel device with integr ated and protected output stages (current sources), optimized to drive LEDs as additional low cost current source
• High output current (up to 80 mA) per channel
• Very low current consumption in sleep mode
• Very low output leakage when channel is “off”
• Low current consumption during fault
• Additional output current demand supported by LI TIX™ Companion direct drive without additional components
• Very high precision di gital dimming supported
• Intelligent fault management: up to 16 and more devi ces can share a common error network with only one external resistor
• Reverse polarity protection allows reduction of ex ternal components and improves system performance at low battery/input voltages
• Overload protection
• Wide temperature range: -40°C < T J < 150°C
• Output current control via external low power resistor
• Green product (RoHS compliant) Potential applications
• Cost effective “stop”/ “tail” function implementa tion with shared and separated LEDs per function
• Turn indicators
• Position, fog, rear li ghts and side markers
• Animated light functions like wiping indicators and “welcome/goodbye” functions
• Day Running Light
• Interior lighting functions like ambient lighting (inc luding RGB color control), illumination and dash board lighting
• LED indicators for industrial applications and instrumentation Product validation Qualified for Automotive Applications. Product Validation according to AEC-Q100/101.

Datasheet 2 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+

Description

The LITIX™ Basic+ TLD2131-3EP is a tr iple channel high-side driver IC wi th integrated output stages. It is designed to control LEDs with a current up to 80 mA. In typical automotive applications the device is capable of driving 3 red LEDs per chain (total 9 LEDs) with a curr ent up to 60 mA and even ab ove, if not limited by the overall system thermal properties. Prac tically, the output current is cont rolled by an external resistor or reference source, independently from load and supply voltage changes. Table 1 Product summary Parameter Symbol Values Operating voltage VS(nom) 5.5 V … 40 V Maximum voltage VS(max) VOUTx(max) 40 V Nominal output (load) current IOUTx(nom) 60 mA (nominal) when using the automotive supply voltage range 8 V - 18 V. Currents up to IOUTx(max) are possible with low thermal resistance RthJA Maximum output (load) current IOUTx(max) 80 mA depending on RthJA Current accuracy at RSET = 10 kΩ KLTx 300 ±5% Current consumption in sleep mode IS(sleep, typ) 0.1 µA Maximum current consumption during fault IS(fault, ERRN) 850 µA or less when fault is detected from another device (disabled via ERRN) Type Package Marking TLD2131-3EP PG-TSDSO-14 TLD2131

Datasheet 3 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+

6.3.4 SLS fault management : D and DS pins open or connected with capacitors to GND (low power

consumption mode with retry strategy) 33 Table of Contents

Datasheet 4 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Block diagram

1 Block diagram

D Current reference VS ERRN OUT2 OUT1 OUT3DS IN_SET SLS_REF 2OUT_SET

Datasheet 5 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Pin configuration

2 Pin configuration

2.1 Pin assignment

Figure 2 Pin configuration

2.2 Pin definitions and functions

10 VS Supply voltage; Connected to battery or supply control switch, with EMC

8G N D Ground; Signal ground 4I N _ S E T Control input for OUT channels; Connect to a low power resistor to adjust OUT output currents. Alternatively, a different current reference (i.e. the OUT_SET of another LITIX™ Basic+ LED Driver) may be connected 2O U T _ S E T Control output for additional current source; If an additional channel or output current with same input control is needed, connect this pin to the IN_SET pin of the additional LED driver. If not used, leave the pin open 6P W M I PWM input; Connect to an external PWM controller. If not used, connect to GND 1S L S _ R E F Single LED short reference input; Connect to a low power resistor or a voltage reference to adjust Internal SLS threshold. If not used, connect to GND 5D S Single LED short delay/restart input; Connect to a capacitor, leave open or connect to GND, depending on the required diagnosis management for single LED short detection (see Chapter 6 for further details) 7D Disable/delay error input; Connect to a capacitor, leave open or connect to GND, depending on the required diagnosis management (see Chapter 6 for further details) 14 ERRN ERROR flag I/O; Open drain, active low. Connect to a pull-up resistor EN/DEN VS D PWMI n.c. OUT3 OUT2 ERRNSLS_REF GND OUT1 EP exposed pad (bottom) TLD2131-3EP OUT_SET DS IN_SET

Datasheet 6 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Pin configuration 9E N / D E N Outputs enable and diagnosis control input; Connect to a control input (i.e. to VS via a resistor divider or a Zener diode) to enable OUTx control and diagnosis capability

13 OUT1 Channel 1 output pin; Connect to the target load

12 OUT2 Channel 2 output pin; Connect to the target load

11 OUT3 Channel 3 output pin; Connect to the target load

3n . c . Not connected; Leave these pins open Exposed Pad EP Exposed Pad; Connected to GND-pin in application Pin Symbol Function

Datasheet 7 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ General product characteristics

3 General product characteristics

3.1 Absolute maximum ratings

Table 2 Absolute maximum ratings 1) TJ = -40°C to +150°C; RIN_SET = 10 kΩ; all voltages with respect to GND, po sitive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltage Supply voltage VS -18 – 40 V – P_4.1.1 EN/DEN voltage VEN/DEN -18 – 40 V – P_4.1.3 EN/DEN voltage related to VS: VEN/DEN - VS VEN/DEN(VS EN/DEN voltage related to VOUTx: VEN/DEN - VOUTx VEN/DEN(V OUTx) Output voltages VOUTx -1 – 40 V – P_4.1.10 Output voltages related to VS: VS - VOUTx VOUTx(VS) -18 – 40 V – P_4.1.11 IN_SET voltages VIN_SET -0.3 – 6 V – P_4.1.12 OUT_SET voltage VOUT_SET -0.3 – 6 V – P_4.1.13 PWMI voltage VPWMI -0.3 – 6 V – P_4.1.14 ERRN voltage VERRN -0.3 – 40 V – P_4.1.18 D Voltage VD -0.3 – 6 V – P_4.1.19 DS voltage VDS -0.3 – 6 V – P_4.1.42 SLS_REF voltage VSLS_REF -0.3 – 6 V – P_4.1.43 Current Output currents (On each output channel OUTn) I OUTx 0–9 5 m A – P_4.1.21 PWMI current IPWMI -0.5 – 0.5 mA – P_4.1.26 IN_SET current IIN_SET 0 – 300 µA – P_4.1.30 D current ID -0.5 – 0.5 mA – P_4.1.31 DS current IDS -0.5 – 0.5 mA – P_4.1.44 SLS_REF current ISLS_REF -0.5 – 0 mA – P_4.1.45 OUT_SET current IOUT_SET 0–0 . 5 m A – P_4.1.32 Temperature Junction temperature T Storage temperature Tstg -55 – 150 °C – P_4.1.34

Datasheet 8 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ General product characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

3.2 Functional range

Note: Within the Normal Operation range, the IC operates as described in the circuit description. Within the Extended Operation range, parameters deviations are possible. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. ESD susceptibility ESD susceptibility all pins to GND VESD -2 – 2 kV HBM 2) P_4.1.36 ESD susceptibility all pins to GND VESD -500 – 500 V CDM 3) P_4.1.37 ESD susceptibility Pin 1, 7, 8, 14 (corner pins) to GND VESD1,7,8,1 -750 – 750 V CDM 3) P_4.1.38 1) Not subject to production test, specified by design 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 Table 3 Functional range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltage range for normal operation VS(nom) 5.5 – 18 V – P_4.2.1 Extended supply voltage for functional range VS(ext) VSUV(ON) –4 0 V – P_4.2.2 Junction temperature TJ -40 – 150 °C – P_4.2.4 Table 2 Absolute maximum ratings 1) (cont’d) TJ = -40°C to +150°C; RIN_SET = 10 kΩ; all voltages with respect to GND, po sitive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 9 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ General product characteristics

3.3 Thermal resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 4 Thermal resistance 1) 1) Not subject to production test, specified by design Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to Case RthJC ––1 0 K / W 1)2) 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and exposed pad are fixed to ambient temperature). TA = 85°C. Total power dissipation = 1.5 W P_4.3.1 Junction to Ambient 1s0p board RthJA1 K/W 1)3) TA = 85°C TA = 135°C 3) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board. The product (chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 70 µm Cu, 300 mm2 cooling area. Total power dissipation 1.5 W distributed statically and homogenously over all power stages P_4.3.3 Junction to Ambient 2s2p board RthJA2 K/W 1)4) TA = 85°C TA = 135°C 4) Specified RthJA value is according to Jedec JESD51-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all power stages P_4.3.4

Datasheet 10 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Internal supply

4 Internal supply

This chapter describes the internal supply in its main parameters and functionality.

4.1 Description

The internal supply principle is highlighted in the concept diagram of Figure 3. If the voltage applied at the EN/DEN pin is below VEN(th) the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to IS(sleep) . As soon as the voltage applied at the supply pin VS is above VSUV(ON) and the voltage applied at the EN/DEN pin is above VEN(th), after the power-on reset time tPOR, the device is ready to deliver output current from the output stages. The power on reset time tPOR has to be taken into account also in relevant application conditions, i. e. with PWM control from VS or EN/DEN lines. Figure 3 Internal supply Furthermore, as soon as the vo ltage applied at the supply pin VS is above VSUV(ON) and the voltage applied to the EN/DEN pin VEN is above VDEN(th), the device is ready to detect and re port fault conditions via ERRN (error network pin) as described in Chapter 6. To program outputs enable and diagnosis enable via EN/DEN pin there are several possibilities, like a resistor divider from VS to GND, a Zener diode from EN/DEN to VS and also a logic control pin (e.g. from a microcontroller output). OUTx Diagnosis Control EN/DEN VDE N(th) VEN(th) OUTx Control VS Internal Supply VSUV

Datasheet 11 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Internal supply Figure 4 Power on reset timing diagram t t 80% tPO R 100% t VEN IOUT VS VEN (th) VSU V(th)

Datasheet 12 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Internal supply

4.2 Electrical characteristics internal supply and EN pin

Table 5 Electrical characteristics: Internal supply and EN pin TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption, sleep mode IS(sleep) –0 . 1 2µ A 1)VEN = 0 V TJ < 85°C VS = 18 V VOUTx = 3.6 V P_5.2.1 Current consumption, active mode (no fault) IS(active) –1 . 5 3m A VEN = 5.5 V IIN_SETx = 0 µA TJ < 105°C VS = 18 V VOUTx = 3.6 V P_5.2.3 Current consumption during fault condition triggered from another device sharing ERRN bus (all channels deactivated) I S(fault, ERRN) – – 850 µA VEN = 5.5 V TJ < 105°C VS = 18 V VERRN = 0 V VOUTx = 3.6 V D open P_5.2.4 Current consumption during fault condition (all channels deactivated) IS(fault, OUT) ––1 . 2 5 m A VEN = 5.5 V TJ < 105°C VS = 18 V VOUT1 = 0 V VOUT2 = VOUT3= 3.6 V D open P_5.2.16 Supply thresholds Required supply voltage for output activation VSUV(ON) ––5 . 5 V VEN = VS VOUTx = 3 V RIN_SET = 6.8 kΩ IOUTx > 50% IOUTx(nom) P_5.2.5 Required supply voltage for output deactivation VSUV(OFF) 4.5 – – V VEN = VS VOUTx = 3 V RIN_SET = 6.8 kΩ IOUTx < 50% IOUTx(nom) P_5.2.6 Supply voltage activation hysteresis: VSUV(ON) - VSUV(OFF) VSUV(hys) – 200 – mV 1)VEN > VEN(th) P_5.2.8

Datasheet 13 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Internal supply EN pin EN outputs enable threshold VEN(th) 1.4 1.65 1.8 V VS = 5.5 V VPS = 2 V RIN_SET = 6.8 kΩ IOUTx = 50% IOUTx(nom) P_5.2.9 DEN diagnosis enable threshold DEN diagnosis enable hysteresis VDEN(hys) – 120 – mV 1)RIN_SET = 6.8 kΩ P_5.2.12 EN/DEN pull-down current IEN/DEN(PD) ––6 0 µ A 1)VS > 8 V VEN/DEN = 2.8 V P_5.2.17 EN/DEN pull-down current IEN/DEN(PD) – – 110 µA 1)VS > 8 V VEN/DEN = 5.5 V P_5.2.14 EN/DEN pull-down current IEN/DEN(PD) – – 350 µA 1)VS > 8 V VEN/DEN = VS P_5.2.15 Timing Power on reset delay time tPOR ––2 5 µ s 1)VS rising from 0 V to 13.5 V VOUTx = 3.6 V RIN_SET = 6.8 kΩ IOUTx = 80% IOUTx(nom) P_5.2.13 1) Not subjected to production test: specified by design Table 5 Electrical characteristics: Internal supply and EN pin (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 14 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages

5 Power stages

The three output stages are realized as high-side curren t sources with an output current up to 80mA. During off state the leakage current at the output stages is minimized in order to prevent a slightly glowing LED. The maximum output current is limited by the power dissipation and used PCB cooling areas. For an operating output current control loop, the supply and output voltages have to be considered according to the following parameters:

• Required supply voltage for current control VS(CC)
• Voltage drop over through the output stage during current control VPSx(CC)
• Required output voltage for current control VOUTx(CC)

5.1 Protection

The device provides embedded protec tive functions, which are designed to prevent IC damage under fault conditions described in this datasheet. Fault conditions are considered as “outside” normal operating range. Protective functions are not designed for continuous nor for repetitive operations.

5.1.1 Thermal protection

A thermal protection circuitry is inte grated in the device. It is realized by a temperature monitoring of the output stages. As soon as the junction temperature exceed s the current reduction temperature threshold TJ(CRT) the output current can be reduced by the device by reducing the IN_SETx reference voltage VIN_SETx(ref). This feature greatly helps to avoid LEDs flickeri ng during static output overload conditions. Furthermore, it helps to protect the LEDs, which are mounted thermally close to the device, agai nst overtemperature. If the device temperature still increases, the three output currents decrease close to 0 A. As soon as the device cools down the output currents rise again. Figure 5 Output current reduction at high temperature (qualitative diagram) Note: It is assumed that a configuration resistor RSET is applied from IN_SET to GND, and not a current source, to make the protection effective. Tj IOUT Tj(CRT ) VIN _SE T

Datasheet 15 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages

5.1.2 Reverse battery protection

The device has an integrated reverse battery protection feature. This feature protects the driver IC itself and, potentially, also connected LEDs. The ou tput reverse current is limited to IOUTx(REV) by the reverse battery protection.

5.2 Output configuration via IN_SET, OUT_SET and PWMI pins

Outputs current can be defined via IN_SET and OUT_SET (to drive additional devices without further external components) pins.

5.2.1 IN_SET pin

The IN_SET pin is a multiple function pin for the output current definition and input control. Output currents definition and analog dimming control can be done defining accordingly the IN_SET current. Figure 6 IN_SET pin block diagram

5.2.2 Output current adjustment via RSET

The output current for the channels can be defined connecting a low power resistor (RSET) between the IN_SET pin and GND. The dimensioning of the resistor can be done using the formula: (5.1) The gain factor kx (defined as the ratio IOUTx/IIN_SET) is graphically described in Figure 7. The current through the RSETx is defined by the resistor it self and the reference voltage VIN_SET(ref), which is applied to the IN_SET pin when the device is supplied and the channel enabled. ref/fault selection logic IN_SET IIN_SET GND IIN_SET(fault)VIN_SET(ref) SETrefSETINxSETINxOUTx RVkIkI /)(__ ⋅=⋅=

Datasheet 16 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages

5.2.3 Output control via IN_SET

The IN_SET pin can be connected via RSET to the open-drain output of a microcontroller or to an external NMOS transistor as described in Figure 9. This signal can be used to turn off the relative output stages of the IC. A minimum IN_SET current of IIN_SET(ACT) is required to turn on the output stages. This feature is implemented to prevent glowing of LEDs caused by leakage currents on the IN_SET pin, see again Figure 7 for details. Figure 7 IOUT vs IIN_SET Figure 8 Typical output current accuracy IOUT / IIN_SET at TJ = 25°C IIN_SET(ACT) IIN_SET [µA] IOUT [mA] k = IOUT / IIN_SET IOUT IIN_SET k/k(typ) 33 66 100 200 100% 105% 95% 267150 IIN_SET [µA]

Datasheet 17 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages Figure 9 Output control via IN_SET pin and op en-drain microcontroller out (simplified diagram)

5.2.4 IN_SET pin behavior during device fault management

If a fault condition arises on the ch annel controlled by the IN_SET pin, on ce the D-pin reaches the high level threshold VD(th), the current of the IN_S ET pin is reduced to IIN_SET(fault), in order to minimise the current consumption of the whole device under fault condition (detailed description is in the load diagnosis section, Chapter 6).

5.2.5 OUT_SET pin

The OUT_SET pin, mirroring the IN_SET current defined by the external resistor RSET, can be used to define the IN_SET current of an additional companion device. If minimum IN_SET activation current IIN_SET(act) is not reached or if the D-pin reaches the high level threshold VD(th) the OUT_SET current is reduced to IOUT_SET(OFF). This allows to drive other devices via OUT_SET, even when digital dimming is required, without external components (see application drawing example in Chapter 7). Supply Protection VS (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections for microcontroller IN_SET control are shown) RSET LITIX™ Basic+ (*) VS EN PWMI OUT GND IN_SET Microcontroller OUT

Datasheet 18 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages Figure 10 OUT_SET pin block diagram Figure 11 IN_SET to OUT_SE T serial connection example

5.2.6 Direct control of PWMI

PWMI input can be controlled by the PWMO output of another device of LITIX™ Basic+ family or, alternatively, a push-pull output stage of a microcontroller: the host device decides the digital dimming characteristics by applying the proper control cycle in order to set the “on”/“off” timing, according to the chosen dimming function.

5.2.7 Timing diagrams

In the following diagrams (Figure 12, Figure 13, Figure 14) the influences of different driving inputs on output activation delays are shown. LOGIC OUT_SET IOUT_SET GND IOUT_SET(OF F) IOUT_SET(ON) Supply Protection VS (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections are shown) LITIX™ Basic+ (*) VS EN PWMI OUT_SET GND IN_SET OUT RSET LITIX™ Basic+ (*) VS EN PWMI OUT_SET GND IN_SET OUT LITIX™ Basic+ (*) VS EN PWMI OUT_SET GND IN_SET OUT

Datasheet 20 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages

5.3 Electrical characteristics power stage

Table 6 Electrical char acteristics: Power stage TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output leakage currents IOUTx(leak) ––3µ A 1)VENx = 5.5 V IIN_SETx = 0 µA VOUTx = 2.5 V TJ = 85°C P_6.5.1 Output leakage currents IOUTx(leak) ––7µ A 1)VENx = 5.5 V IIN_SETx = 0 µA VOUTx = 2.5 V TJ = 150°C P_6.5.59 Reverse output currents IOUTx(rev) ––3µ A 1)VEN = V s VSx = -18 V Output load: LED with break down voltage < - 0.6 V P_6.5.2 Output current accuracy Output current accuracy KLTx 279 300 321 – 1)TJ = 25... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 33 µA P_6.5.30 Output current accuracy KALLx 267 300 333 – 1)TJ = -40... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 33 µA P_6.5.31 Output current accuracy KLTx 285 300 315 – 1)TJ = 25... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 66 µA P_6.5.32 Output current accuracy KALLx 279 300 321 – 1)TJ = -40... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 66 µA P_6.5.33 Output current accuracy KLTx 288 300 312 – 1)TJ = 25... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 200 µA P_6.5.34 Output current accuracy KALLx 285 300 315 – 1)TJ = -40... 115°C VS = 8... 18 V VPSx = 2 V IIN_SETx = 200 µA P_6.5.35

Datasheet 21 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages Required voltage drop during current control V PS(CC) = VS - VOUTx VPSx(CC) 1.0 – – V 2)VS = 8... 18 V IOUTx > 90% of Kx(typ)*IIN_SET P_6.5.36 Required voltage drop during current control VPSx(CC) = VS - VOUTx VPSx(CC) 0.65 – – V 2)VS = 8... 18 V IIN_SET = 133 µA IOUTx > 90% of Kx(typ)*IIN_SET TJ = -40°C P_6.5.37 Required voltage drop during current control VPSx(CC) = VS - VOUTx VPSx(CC) 0.75 – – V 2)VS = 8... 18 V IIN_SET = 133 µA IOUTx > 90% of Kx(typ)*IIN_SET TJ = 25°C P_6.5.38 Required voltage drop during current control VPSx(CC) = VS - VOUTx VPSx(CC) 0.85 – – V 2)VS = 8... 18V IIN_SET = 133 µA IOUTx > 90% of Kx(typ)*IIN_SET TJ = 150°C P_6.5.39 Required supply voltage for current control VS(CC) 5.5 – – V VEN = 5.5 V VOUT = 3 V RIN_SET = 6.8 kΩ IOUT > 90% of Kx*IIN_SET P_6.5.40 Required output voltage for current control VOUT(CC) 1.4 – – V VS = 8... 18 V IOUT > 90% of Kx*IIN_SET P_6.5.41 Current reduction temperature threshold Output current during current reduction at high temperature I OUT(CRT) 85% of IOUT(typ) 1) Not subjected to production test: specified by design 2) In these test conditions, the parameter K(typ) represents the typical value of output current accuracy. Table 6 Electrical char acteristics: Power stage (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 22 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages

5.4 Electrical characteristics IN_SET, OUT_ SET and PWMI pins for output settings

Table 7 Electrical characterist ics: IN_SET, OUT_SET and PWMI pins TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. IN_SET reference voltage VIN_SET(ref) 1.195 1.22 1.245 V 1)VEN = 5.5 V TJ = 25°C P_6.6.1 IN_SET reference voltage VIN_SET(ref) 1.184 1.22 1.256 V 1)VEN = 5.5 V TJ = -40... 115°C P_6.6.17 IN_SET output activation current IIN_SET(ACT) ––1 5 µ A VEN = 5.5 V VPSx = 3 V IOUTx > 50% of Kx(typ)*IIN_SET P_6.6.2 OUT_SET output current matching ∆IOUT_SET(ON)/II N_SET -4 – 4 % VS = 8 V to 18 V VOUT_SET = 1.2V IIN_SET = 267 µA P_6.6.3 PWMI low threshold VPWMI(L) 1.5 1.7 2 V VS = 8 V to 18 V VEN = 5.5 V P_6.6.6 PWMI high threshold VPWMI(H) 2.5 2.7 3 V VS = 8 V to 18 V VEN = 5.5 V P_6.6.7 Timing IN_SET turn on time tON(IN_SET) ––2 0 µ s 1)2)VS = 13.5 V VPSx = 4 V IIN_SET rising from 0 to 180 µA I OUTx = 90% of Kx*IIN_SET P_6.6.8 IN_SET turn off time tOFF(IN_SET) ––1 0 µ s 1)2)VS = 13.5 V VPSx = 4 V IIN_SET falling from 180 to 0 µA IOUTx = 10% of Kx*IIN_SET P_6.6.9 OUT_SET activation time tdel(OUT_SET,H) ––5µ s 1)3)VS = 13.5 V IIN_SET rising from 0 to 180 µA IOUT_SET = 90% of IIN_SET P_6.6.10 OUT_SET deactivation time tdel(OUT_SET,L) ––5µ s 1)3)VS = 13.5 V IIN_SET falling from 180 to 0 µA IOUT_SET = 10% of IIN_SET P_6.6.11

Datasheet 23 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Power stages PWMI turn on time tON(PWMI) ––1 5 µ s 1)4)VS = 8 V to 18 V VEN = 5.5 V VPWMI falling from 5V t o 0 V IOUTx = 90% of Kx*IIN_SET TJ = -40... 115°C P_6.6.12 PWMI turn off time tOFF(PWMI) ––1 0 µ s 1)4)VS = 8 V to 18 V VEN = 5.5 V VPWMI = 0 rising from 0 V to 5 V IOUTx = 10% of Kx*IIN_SET TJ = -40... 115°C P_6.6.13 1) Not subjected to production test: specified by design 2) Refer to Figure 12 3) Refer to Figure 13 4) Refer to Figure 14 Table 7 Electrical characterist ics: IN_SET, OUT_SET and PWMI pins (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 24 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis

6 Load diagnosis

6.1 Error management via ERRN and D-pins

Several diagnosis features are integrated in the TLD2131-3EP:

• Open load detection (OL) for an y of the output channels OUTx.
• Short circuit OUTx-GND (SC) for any of the output channels OUTx.
• Single LED Short detection (SLS).

6.1.1 ERRN pin

Figure 15 ERRN pin (block diagram) The device is able to report a detected failure in one of its driven loads and react to a fault detected by another LED driver in the system if a shared error network is implemented (i. e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open drain diagnosis output pin ER RN. All devices sharing the common error network are capable to detect the fault from any of the channels driv en by the LITIX™ Basic+ LED drivers and, if desired, to switch multiple loads off. ERRN VERRN(th) IERRN(fault) no faultfault Ou tp ut control

Datasheet 25 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Figure 16 Shared error network principl e between LITIX™ Basic+ family devices When one of the channels is detected to be unde r fault conditions (for, at least, a filter time tfault), the open- drain ERRN pin sinks a pull-down current IERRN(fault) toward GND. Therefore an active low state can be detected at ERRN pin when VERRN < VERRN(fault) and if this condition is reached, provided the proper setup of the delay pin D , a l l t h e c h a n n e l s a r e s w i t c h e d o f f . S i m i l a r l y , w h e n t h e f a u l t i s r e m o v e d , E R R N p i n i s p u t b a c k i n h i g h impedance state, and the channels reactivation procedure can be completed once D-pin voltage is below the value V D(th), as illustrated in the timing diagrams in this chapter. OUT LITIX™ Basic+ (*) PWMI IN_SET GND Supply Protection VS VS EN ERRN LITIX™ Basic+ (*) VS EN RERRN ERRN Connection to further devices (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections are shown)RSET OUT PWMI IN_SET GND RSET

Datasheet 26 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis

6.1.2 D-pin

Figure 17 D-pin (block diagram). The D-pin is designed for 2 main purposes:

• To react to error conditions in LED arrays according to the implemented fault management policy, in systems where multiple LED chains are used for a given light function.
• To extend the channels deactiva tion delay time of a value tD, adding a small signal capacitor from the D- pin to GND. In this way, an unstable or noisy fault condition may be prevented from switching off all the channels of a given light function (i.e. driven by several driver ICs sharing the same error network). The functionality of the D-pin is shown in the Figure 17 simplified block diagram: If one LED within one chain fails in open load condition or one of the de vice outputs are shorted to GND, the respective LED chain is off. Differ ent automotive applicatio ns require a complete deactivation of a light function, if the desired brightness of the function (LED array) can not be achieved due to an internal error condition. In normal operative status (no fault) a pull-down current ID(PD) is sunk from the D-pin to GND. If there is a fault condition (for, at least, a filter time tfault) in one of the LED channels driven by the IC or in any of the devices sharing the same ERRN error ne twork line, a pull-up current ID(fault) is instead sourced from the D-pin. As a consequence, if a capacitive or open load is applied at this pin, its voltage starts rising. When VD(th) is reached at D-pin, all the channels driven by the device are switched off and if other devices share the same ERRN and D-pins nodes, all the devices turn their outputs off. Alternatively, if the D-pin is tied to GND, only the channel that has b een detected with a fault is safely deactivated. D ID(PD) CD ID(fault) ERRN = H VD(th) Ou tp ut control ERRN = L ERRN = H ERRN = L

Datasheet 27 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis The capacitor value used at the D-pin, CD, sets the delay times tD(set/reset) according to the following equations: (6.1) (6.2) Note: If the device detects a Single LED Short failure, the D-pin behavior and the overall fault management is slightly different (allows periodical retries with load reactivation, according to DS pin settings too), as described in Chapter 6.3.

6.2 Open Load (OL) and short OUTx to GND (SC)

The behavior of the device during ov erload conditions that lead to an excess of internal heating up to overtemperature condition, is already described in Chapter 5. Open load (OL) and OUTx shorted to GND (SC) diagnosis features are also integrated in the TLD2131-3EP. An open load condition is detected if the voltage drop over one of the output stages VPSx is below the threshold VPSx(OL) at least for a filter time tfault. A short to GND condition is detected if the voltage of one output stages VOUTx is below the threshold VOUTx(SC) at least for a filter time tfault.

6.2.1 Fault management (D-pin open or connected with a capacitor to GND)

With D-pin open or connected with a capacitor to GND configuration, it is possible to switch off all the channels which share a common error network, without the need of an auxiliary microcontroller. For more details refer also to the timing diagram of Figure 18, Figure 19. If there is an OL or SC condition on one of the outputs, a pull-up current IOUT(fault) then flows out from the affected channel, replacing the configured output curr ent (but limited by the ac tual load impedance, e.g. reduced to zero with an ideal open load). Under these conditions, the ERRN pin starts sinking a current IERRN(fault) toward GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). After tD(set), the voltage VD(th) is reached at D-pin, the IN_SET goes in a weak pull-down state with a current consumption IIN_SET(fault) after an additional latency time t IN_SET(del). The ERRN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy. The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (at least for a filter time tfault) ERRN goes back to high impeda nce. When its voltage is above VERRN(fault), the D-pin voltage starts decreasing and after t D(reset) goes below (VD(th) - VD(th,hys)). Then the IN_SET voltage goes up to VIN_SET(ref), again after a time t IN_SET(del): at this point, the output stages are ac tivated again. The to tal time between the fault removal and the IN_SET reactivation tERR(reset) is extended by an additional latency which depends on the external ERRN pin pull-up and filter circuitry. ݐܦ(ݐ݁ݏ)= ܥܦ∙ܸ)ℎݐ(ܦ ܫܦ(ݐ݈ݑ݂ܽ) ݐܦ(ݐ݁ݏ݁ݎ)= ܥܦ∙൫ܸ)ܮܥ(ܦ−ܸ)ℎݐ(ܦ൯ ܫ)ܦܲ(ܦ

Datasheet 28 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Figure 18 Open load condition timing diagram ex ample (D-pin unconnected or connected to external capacitor to GND, VF represents the typical forward voltage of the output load) t tfault VOUT t VF VD( th ) VS VD t VER R N (fault) VE RRN open load occurs open load disappears VS –V PS (O L ) t VIN _SET (ref) VIN _SET tfault tD(reset) tER R (r es et) tD(set ) tIN _SET (del) tIN _SET (del) VD(t h, hys )

Datasheet 29 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Figure 19 Short circuit to GND condition timing diagram example (D-pin not connected or connected to external capacitor to GND, VFxyz represents the forward voltage of the output loads)

6.2.2 Fault management (D-pin connected to GND)

With D-pin connected to GND configuration, it is po ssible to deactivate only the channel under fault conditions, still sharing ERRN pin in a common error network with other devices of LITIX™ Basic+ family. If there is fault condition on one of the outputs, a pull-up current IOUT(fault) flows out from the affected channel, replacing the configured output current (but limited by the actual lo ad impedance, e.g. reduced to zero with an ideal open load). Under fault conditio ns the ERRN pin starts sinking a current IERRN(fault) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy. t VOUT VF VS short circuit occurs short circuit disappears VOUT (SC ) tfault tfault tD (reset ) tER R (res et) t VD( t h ) VD t VE RRN ( f a u l t ) VER R N t VIN _ SET (ref) tD(set) tIN_SET (del ) tIN_SET (del ) VIN _SET VD(t h, hys )

Datasheet 30 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis The fault status is not latched: as soon as the fault condition is no longer present (at least for a filter time tfault), ERRN goes back to high impedanc e and, once its voltage is above VERRN(fault), finally the output stages are activated again. Examples of open load or short to GND diagnosis with D-pin open or connected to GND are shown in the timing diagrams of Figure 20 and Figure 21. Figure 20 Open load condition timing diagram example (D-pin connected to GND, VF represents the forward voltage of the output load) t tfault VOUT VF VS VER RN (fault) VER R N open load occurs open load disappears VS – VPS (O L) t VIN_SE T(ref) VIN _SE T t tfault

Datasheet 31 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Figure 21 Short circuit condition timing diagram example (D-pin connected to GND, VF represents the forward voltage of the output load)

6.3 Single LED Short detect ion, SLS_REF and DS pins

An output single LED short circuit (SLS) detection diagnosis feature is available. This allows an easy detection of loss of luminous flux in the light function due to this failure mode, which does not necessarily result in a condition similar or equivalent to an open load or short to GND condition. To make the SLS error management compliant with the majority of system requirements, the TLD2131-3EP allows the possibility to manage a low current consumption mode with a lo ad reactivation and re try strategy (via D and DS pins connected to external capacitors), or with error detection via ERRN pin monitoring (with D-pin shorted to GND). VOUT VS VF short circuit occurs short circuit disappears VOUT (SC ) t tfault VER R N( fault) VER R N t VIN_SET (ref) t tfault VIN _SET

Datasheet 32 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis

6.3.1 SLS_REF pin

Figure 22 SLS_REF pin (block di agram) with resistor termination The SLS_REF pin is designed to generate an accurate and tunable reference voltage to allow reliable detection of SLS failure. This reference can be programmed to adapt the SLS detection to the load related variables (as number of LED in series, load currents, LED forward voltages fluctuation and mismatches, etc.). The pin provides an accurate reference current ISLS_REF (a replica of IIN_SET) which can be used to generate the desired reference voltage with an external low cost precision resistor. The voltage VSLS_REF is then internally compared with a fraction of the OU T voltage: if the OUT voltage is be low the minimum expected value, then the SLS error management starts (see Chapter 6.3.3 for more detailed description and reference formulas). Figure 22 shows the basic block diagram of SLS_REF pin. ISLS_REF -SLS_REF RSLS_REF VSLS_REF(CL) Output control SLS error management state Machine OUT2 OUT1 OUT3 min (VOU Tx ( ON )) 1/B

Datasheet 33 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis

6.3.2 DS pin

Figure 23 DS pin (block diagram) The DS pin is used to implement a timer function which allows load reactivation retries during SLS failure. By default, when no SLS fault is detected, a pull-down current IDS(PD) is sunk from the DS pin to GND. If a SLS fault condition is verified, a capacitor on DS pin allows fault management with minimal current consumption of the device for a time which depends on the capacitive load applied, according to the detailed description of Chapter 6.3.4.

6.3.3 SLS fault detection

A single LED anode-cathode short circuit condition is detected if the lowest voltage between OUT1, OUT2 and OUT3 is below a fixed multiple BSLS of the voltage at SLS_REF pin, according to Equation (6.3).The voltage VSLS_REF can be adjusted applying a resistor from SLS_REF to GND, according to Equation (6.4) and the parameter KSLS_REF (P_7.5.13). (6.3) (6.4)

6.3.4 SLS fault management: D and DS pins open or connected with capacitors to

GND (low power consumption mode with retry strategy) Under this pin configuration, as described in the title of this chapter, if there is an SLS condition the outputs are turned off when the voltage level VD(th) is reached at D-pin. Under fault condition the ERRN pin starts sinking a current IERRN(fault) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. After tD(set), the voltage VD(th) is reached at D-pin and the IN_SET pins goes into a weak pull-down state with a current consumption IIN_SET(fault), after an additional latency time tIN_SET(del). SLS error management state machine DS IDS(PD) VDS(L) CDS VDS(H) VDS(CL) IDS(PU) () REFSLSSLSOUTOUTOUT VBVVV _321 ,,min ⋅≤ REFSLSREFSLSREFSLS RIV ___ ⋅=

Datasheet 34 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Then (differently from the management of OL and SC detection) the voltage at DS pin also starts rising with a pull-up current IDS(PU), until it reaches the threshold VDS(H), when it starts discharging with the current IDS(PD). Now the DS voltage can cross the lower voltage threshold VDS(L): at this time a full wait time cycle tSL_WAIT is completed and the device performs a load reactivation re try, turning the output curr ents back on. If the SLS fault condition persists, a new tSL_WAIT cycle is started. If at the end of one wait cycle the fa ult is not detected anymore, the device goes ba ck to normal operation. Th e dimensioning of typical tSL_WAIT is ruled by the following equations. (6.5) (6.6) (6.7) A graphical description is shown in the timing diagram example of Figure 24. With this error management algorithm, it is possi ble to detect the SLS fault monitoring the device consumption from the VS line, which remains as low as IS(fault) during the whole wait cycle. Figure 24 Single LED short condition timing diag ram example (D pin not connected or connected to external capacitor to GND)

6.3.5 SLS fault management: D-pin shorted to GND

Under D-pin shorted to GND configuratio n, the output affected by a single LED short fault is not turned off, different from an open load or shor t circuit to GND fault condition. Th e potential on the IN_SET pin remains PUDS HDSDS riseDS I VCt ⋅= ( ) )()( PDDS HDSDS PDDS LDSHDSDS fallDS I VC I VVCt ⋅≈−⋅= )()(_)()()( riseDSdelSETINfallDSriseDSwaitSL ttttt ≈++= VOUT t VERRN VERRN(fault) t tfault tD(set) tD(reset) VD VD(th) VDS VIN_SET t tIN_SET(del) VIN_SET(ref) tfault VDS (H) VDS (L) t tSL(wait) t SLS fault appears SLS fault disappears Retry + Restart B*VSLS_REF VOUT(typ) VOUT(SLS) Active Retry tfault tIN_SET(del)

Datasheet 35 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis VIN_SET(ref), the ERRN pin starts sinking a current IERRN(fault) toward GND. Again, the resulting ERRN low voltage can be used as input signal for a microcontroller to perform the desired diagnosis policy. Also the SLS status is not latched: as soon as the fault condition is no longer present (at least for a filter time tfault) ERRN goes back to high impedance. An examples of this SLS diagnosis condition is shown in the timing diagrams of Figure 25. Figure 25 Single LED short condition timi ng diagram example (D pin shorted to GND)

6.4 Electrical characteristics: Load diagnosis and Overload management

Table 8 Electrical Characteristics: Fault management TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. IN_SET fault current IIN_SET(fault) ––1 0 µ A 1)VS > 8 V VOUT = 3.6 V VERRN = 0 V VIN_SET = 1 V D open VEN > VDEN(th,max) P_7.5.1 ERRN fault current IERRN(fault) 2––m A 1)VS > 8 V VERRN = 0.8 V Fault condition V EN > VDEN(th,max) P_7.5.2 ERRN input threshold V ERRN(th) 0.8 – 2.0 V 1)VS > 8 V P_7.5.3 OL detection threshold VPS(OL) 0.2 – 0.4 V VS > 8 V VEN > VDEN(th, max) P_7.5.5 SC detection threshold VOUT(SC) 0.8 – 1.35 V VS > 8 V VEN > VDEN(th, max) P_7.5.6 VOUT t VERRN VERRN(fault) t tfault VIN_SET t VIN_SET(ref) SLS fault appears SLS fault disappears B*VSLS_REF VOUT(typ) VOUT(SLS) tfault

Datasheet 36 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis Fault detection current IOUT(fault) 50 – 180 µA VS > 8 V VOUT = 0 V VEN > VDEN(th, max) P_7.5.7 D-pin Threshold voltage for function de-activation VD(th) 1.4 1.7 2 V VS > 8 V VEN= 5.5 V P_7.5.8 Threshold hysteresis VD(hys) – 100 – mV 1)VS > 8 V VEN = 5.5 V VOUT = VOUT(OL) P_7.5.9 Fault pull-up current ID(fault) 20 35 50 µA VS > 8 V VOUT = VOUT(OL) VD = 2 V P_7.5.10 Pull-down current ID(PD) 40 60 95 µA VS > 8 V VEN = 5.5 V VD = 1.4 V VERRN = 2 V VPS = 3 V No fault conditions P_7.5.11 Internal clamp voltage VD(CL) 4–6V VS > 8 V VOUT = VOUT(OL) D-pin open P_7.5.12 SLS_REF pin Relative pull-up current, related to IN_SET I SLS_REF / IINSET KSLS_REF 0.972 1 1.028 – VS > 8 V VSLS_REF = 0.75... 3.25 V IIN_SET = 50... 270 µA P_7.5.13 Output attenuation factor for internal reference comparison BSLS 3.77 3.93 4.09 – VS > 14.65 V min(VOUT) = 13 V P_7.5.21 Output attenuation factor for internal reference comparison BSLS 3.76 3.93 4.10 – VS > 8 V min(VOUT) = 7 V P_7.5.22 Output attenuation factor for internal reference comparison BSLS 3.75 3.93 4.11 – VS > 8 V min(VOUT) = 5 V P_7.5.23 Output attenuation factor for internal reference comparison B SLS 3.73 3.93 4.13 – VS > 8 V min(VOUT) = 3 V P_7.5.24 Table 8 Electrical Characteristics: Fault management (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 37 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Load diagnosis SLS saturation voltage threshold VSLS_REF(CL) 3.5 – 6 V VS > 8 V VEN = 5.5 V VPWMI = 0 V SLS_REF open P_7.5.14 DS pin High threshold voltage (to trigger from pull up to pull- down current) VDS(H) 2.3 2.5 2.7 V VS > 8 V VSLS_REF = 1.5 V VOUT = VOUT = 7 V VOUT = 5 V P_7.5.15 Low threshold voltage for retry activation VDS(L) 0.2 0.3 0.4 V VS > 8 V VSLS_REF = 1.5 V VOUT = VOUT = 7 V VOUT = 5 V P_7.5.16 Pull-up current IDS(PU) 25 35 50 µA VS > 8 V VSLS_REF = 1.5 V VOUT = VOUT = 7 V VOUT = 5 V P_7.5.17 Pull-down current IDS(PD) 300 500 750 µA VS > 8 V VEN = 5.5 V VDS = 0.4 V VERRN = 2 V VPS = 3 V No fault conditions P_7.5.18 Timing Fault to ERRN activation delay tfault 40 – 150 µs 1)VS > 8 V VOUT rising from 5 V to VS VEN > VDEN(th, max) P_7.5.19 Fault appearance/removal to IN_SET deactivation/activation delay tIN_SET(del) ––1 0 µ s 1)VS > 8 V OUT open D rising from 0 V to V EN > VDEN(th, max) P_7.5.20 1) Not subjected to production test: specified by design. Table 8 Electrical Characteristics: Fault management (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 38 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+

Application information

7 Application information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 26 Application diagram example Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application. OUT1 OUT2 OUT3 TLD2131-3EPVS D EN/DEN COUT* Supply Pr otection ERRN DS IN_SET PWMI SLS_REF GND CVS* CD CDS RSET RSLS_RE F REN/DE N2 VS OUT1 OUT2 OUT3 VS D EN/DEN ERRN DS CVS REN/DEN1 RERRN * For EMI improvement, if required (e.g. 4,7 or 10nF) OUT_SET IN_SET PWMI SLS_REF GND RSLS_RE F OUT_SET TLD2131-3EP COUT* COUT* COUT* COUT* COUT*

Datasheet 39 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+ Package outline

8 Package outline

Green product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages ,1'(; 0$; 67$1'2)) & [ 0$5.,1* 6($7,1* 3/$1( &23/$1$5,7< s s s rr s $% & s %27720 9,(: s s [ [ s *$8*( 3/$1(

Datasheet 40 Rev. 1.10 2019-09-26 TLD2131-3EP LITIX™ Basic+

Revision History

9 Revision History

1.10 2019-09-26 Updated P_4.1.21 1.10 2019-09-26 Corrected copper dimensions in footnote 4) in Table 4 1.10 2019-09-26 Updated Equation (6.1) and Equation (6.2) 1.10 2019-09-26 Specified typical value for VD(th) . See P_7.5.8 1.00 2018-10-09 Initial datasheet created

All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-09-26 Published by Infineon Technologies AG

81726 Munich, Germany

© 2019 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference LITIX™ Basic+ TLD2131-3EP IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.