TLD1326EL_15 INFINEON | Alldatasheet
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Technical content
Rev. 1.1, 2015-03-24 TLD1326EL
3 Channel High Side Current Source
Infineon ® LITIX TM Basic
Data Sheet 2 Rev. 1.1, 2015-03-24 TLD1326EL
TLD1326EL PG-SSOP14 TLD1326EL Data Sheet 3 Rev. 1.1, 2015-03-24
Features
- 3 Channel device with integrated output stages (current sources), optimized to drive LEDs
- Output current up to 120mA per channel
- Low current consumption in sleep mode
- PWM-operation supported via VS- and EN-pin
- Integrated PWM dimming engine to provide two LED brightness levels without external logic (e.g. µC)
- Output current adjustable via external low power resistor and possibility to connect PTC resistor for LED protection during over temperature conditions
- Dynamic overhead control
- Reverse polarity protection
- Overload protection
- Undervoltage detection
- Infineon® N-1 detection functionality
- Wide temperature range: -40 °C < T j < 150 °C
- PG-SSOP14 package with exposed heatslug
- Green Product (RoHS compliant)
- AEC Qualified
Description
The LITIXTM Basic TLD1326EL is a three channel high side driver IC with integrated output stages. It is designed to control LEDs with a current up to 120 mA. In typical au tomotive applications the device is capable to drive i.e. 3 red LEDs per chain (total 9 LEDs) with a current up to 60mA, which is limited by thermal cooling aspects. The output current is controlled practically independent of load and supply voltage changes. Table 1 Product Summary Operating voltage VS(nom) 5.5 V… 40 V Maximum voltage VS(max) VOUTx(max) 40 V Nominal output (load) current IOUTx(nom) 60 mA when using a supply voltage range of 8V - 18V (e.g. Automotive car battery). Currents up to IOUT(max) possible in applications with low thermal resistance RthJA
Data Sheet 4 Rev. 1.1, 2015-03-24 TLD1326EL Overview Protective functions - ESD protection - Under voltage lock out - Over Load protection - Over Temperature protection - Reverse Polarity protection Diagnostic functions - N-1 detection, latched function - SC to Vs (indicated by N-1 diagnosis)
Applications
Designed for exterior LED lighting applications such as tail/brake light, turn indicator, position light, side marker,... The device is also well suited for in terior LED lighting applications such as ambient lighting, interior illumination and dash board lighting. Maximum output (load) current IOUTx(max) 120 mA; depending on thermal resistance RthJA Output current accuracy at RSET = 12 kΩ kLT 750 ± 7% Current consumption in sleep mode IS(sleep,typ) 0.1 µA Table 1 Product Summary
Data Sheet 5 Rev. 1.1, 2015-03-24
2 Block Diagram
Figure 1 Basic Block Diagram Output control OUT2 Internal supply Thermal protection Current adjust TLD1326EL GND EN VS IN_SET N-1 PWMI DC/DC control FB OUT3 OUT1
Data Sheet 6 Rev. 1.1, 2015-03-24 TLD1326EL Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration TLD1326EL EP NC FB OUT3 OUT2EN OUT1NC VS VS PWMI IN_SET N-1 8N C GND
Data Sheet 7 Rev. 1.1, 2015-03-24
3.2 Pin Definitions and Functions
1, 2 VS – Supply Voltage; battery supply, connect a decoupling capacitor (100 nF - 1 µF) to GND 3E NI Enable pin 4N C – Pin not connected 5P W M I I / O PWM Input
6 IN_SET I/O Input / SET pin; Connect a low power resistor to adjust the output current
8N C – Pin not connected 9G N D – 1) Ground 1) Connect all GND-pins together.
10 FB O Feedback Output
11 OUT1 O Output 1
12 OUT2 O Output 2
13 OUT3 O Output 3
14 NC – Pin not connected
GND – 1) Exposed Pad; connect to GND in application
Data Sheet 8 Rev. 1.1, 2015-03-24 TLD1326EL General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) 1) Not subject to production test, specified by design Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. Voltages
4.1.1 Supply voltage
VS -16 40 V –
4.1.2 Input voltage EN VEN -16 40 V –
4.1.3 Input voltage EN related to VS VEN(VS) VS - 40 VS + 16 V –
4.1.4 Input voltage EN related to VOUTx
-16 40 V –
4.1.5 Output voltage VOUTx -1 40 V –
4.1.6 Power stage voltage
VPS = VS - VOUTx VPS -16 40 V – 4.1.7 Input voltage PWMI VPWMI -0.3 6 V – 4.1.8 IN_SET voltage VIN_SET -0.3 6 V – 4.1.9 N-1 voltage VN-1 -0.3 6 V – 4.1.10 Feedback voltage VFB -0.3 40 V – Currents
4.1.11 IN_SET current IIN_SET –
mA – Diagnosis output 4.1.12 N-1 current IN-1 -0.5 0.5 mA – 4.1.13 Feedback current IFB –0 . 5 m A –
4.1.14 Output current IOUTx –1 3 0 m A –
4.1.15 Junction temperature Tj -40 150 °C–
4.1.16 Storage temperature Tstg -55 150 °C–
4.1.17 ESD resistivity to GND VESD -2 2 kV Human Body
Model (100 pF via 1.5 kΩ)2) 2) ESD susceptibility, Human Body Model “HB M” according to ANSI/ESDA/JEDEC JS-001-2011
4.1.18 ESD resistivity all pins to GND VESD -500 500 V CDM 3)
3) ESD susceptibility, Charged Device Model “CDM” according to JESD22-C101E
4.1.19 ESD resistivity corner pins to GND VESD -750 750 V CDM 3)
General Product Characteristics Data Sheet 9 Rev. 1.1, 2015-03-24 Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions Min. Max.
4.2.20 Supply voltage range for
VS(nom) 5.5 40 V –
4.2.21 Power on reset threshold VS(POR) –5V VEN = VS
RSET =1 2k Ω IOUTx =8 0 %IOUTx(nom) VOUTx =2 . 5V
4.2.22 Junction temperature Tj -40 150 °C–
Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
4.3.1 Junction to Case RthJC –81 0 K / W 1) 2)
1) Not subject to production test, specifi ed by design. Based on simulation results. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed Pad are fixed to ambient temperature). Ta = 85°C, Total power dissipation 1.5 W.
4.3.2 Junction to Ambient 1s0p board RthJA1
K/W 1) 3) Ta =8 5° C Ta = 135 °C 3) The RthJA values are according to Jedec JESD51-3 at natural convection on 1s0p FR4 board. The product (chip + package) distributed statically and homogenously over all power stages.
4.3.3 Junction to Ambient 2s2p board RthJA2
K/W 1) 4) Ta =8 5° C Ta = 135 °C 4) The RthJA values are according to Jedec JESD51-5,-7 at natural convection on 2s2p FR4 board. The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (outside 2 x 70 µm Cu, inner 2 x 35µm Cu). Where applicable, a thermal via array under the exposed pad contacted the first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all power stages.
Data Sheet 10 Rev. 1.1, 2015-03-24 TLD1326EL EN Pin 5E N P i n The EN pin is a dual function pin: Figure 3 Block Diagram EN pin Note: The current consumption at the EN-pin IEN needs to be added to the total device current consumption. The total current consumption is the sum of the currents at the VS-pin IS and the EN-pin IEN.
5.1 EN Function
If the voltage at the pin EN is below a threshold of VEN(off) the LITIXTM Basic IC will enter Sleep mode. In this state all internal functions are switched off, the current consumption is reduced to IS(sleep). A voltage above VEN(on) at this pin enables the device after the Power on reset time tPOR. Figure 4 Power on reset VEN EN Output Control Internal Supply VEN t t 80 % tPORIOUT 100 % t VS
Data Sheet 11 Rev. 1.1, 2015-03-24
5.2 Internal Supply Pin
The EN pin can be used to supply the internal logic. There are two typical application conditions, where this feature can be used: 1) In “DC/DC control Buck” configurations, where the voltage Vs can be below 5.5V (see Figure 20 for details). 2) In configurations, where a PWM signal is applied at the Vbatt pin of a light module. The buffer capacitor CBUF is used to supply the LITIX TM Basic IC during Vbatt low ( Vs low) periods. This feature can be used to minimize the has to be considered. The capacitor can be calculated using the following formula: (1) See also a typical application drawing in Chapter 11. Figure 5 External circuit when applying a fast PWM signal on VBATT CBUF tLOW max() IEN LS() VS VD1– VSP O R()– RSET CBUF VBATT GND Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1 LITIXTM Basic
Data Sheet 12 Rev. 1.1, 2015-03-24 TLD1326EL EN Pin Figure 6 Typical waveforms when applying a fast PWM signal on VBATT The parameter tON(VS) is defined at Pos. 10.2.13. The parameter tOFF(VS) depends on the load and supply voltage VBATT characteristics.
5.3 EN Unused
In case of an unused EN pin, there are two different ways to connect it:
5.3.1 EN - Pull Up to VS
The EN pin can be connected with a pull up resistor (e.g. 10 k Ω) to Vs potential. In this configuration the LITIXTM Basic IC is always enabled.
5.3.2 EN - Direct Connection to VS
The EN pin can be connected directly to the VS pin (I C always enabled). This configuration has the advantage (compared to the configuration described in Chapter 5.3.1) that no additional external component is required. VBATT t t 20 % 80 % tON(VS)IOUT 100 % VEN t Switch off behavior depends on VBATT and load characteristics
Data Sheet 13 Rev. 1.1, 2015-03-24 6P W M I P i n The PWMI pin is designed as a dual function pin. Figure 7 Block Diagram PWMI pin The pin can be used for PWM-dimming via a push-pull stage of a micro controller, which is connecting the PWMI- pin to a low or high potential. Note: The micro controller’s push-pull stage has to able to sink currents according to Pos. 6.3.16 to activate the device. Furthermore, the device offers also an internal PWM unit by connecting an external-RC network according to Figure 10.
6.1 PWM Dimming
A PWM signal can be applied at the PWMI pin for LED brightness regulation. The dimming frequency can be adjusted in a very wide range (e.g. 400 Hz). The PWMI pin is low active. Turn on/off thresholds VPWMI(L) and Figure 8 Turn on and Turn off time for PWMI pin usage IPWMI(L) VPWMI PWMI Output Control VPWMI t t 20% 80% tON(PWMI ) IOUT 100% tOFF(PWMI )
Data Sheet 14 Rev. 1.1, 2015-03-24 TLD1326EL PWMI Pin
6.2 Internal PWM Unit
Connecting a resistor and a capacitor in parallel on the PWMI pin enables the internal pulse width modulation unit. The following figure shows the charging and discharging defined by the RC-network according to and the internal PWM unit. Figure 9 PWMI operating voltages The PWM Duty cycle (DC) and the PWM frequency can be adjusted using the formulas below. Please use only typical values of VPWMI(L), VPWMI(H) and IPWMI(on) for the calculation of tPWMI(on) and tPWMI(off) (as described in (2) (3) (4) (5) Out of this equations the required CPWMI and RPWMI can be calculated: (6) (7) Outputs ON VPWMI Outputs OFF t OUT- ON OUT - OFF VPWMI(H) VPWMI(L) Internal PWM OUT- ON OUT - OFF OUT- ON OUT - OFF OUT- ON OUT - OFF tPWMI on() R– PWMI CPWMI LN VPWMI H() IPWMI on() RPWMI⋅– VPWMI L() IPWMI on() RPWMI⋅– ⎛⎞⋅⋅= tPWMI off() RPWMI C⋅ PWMI LN VPWMI H() VPWMI L() ⎛⎞⋅= fPWMI tPWMI on() tPWMI off()+ DC t PWMI on() fPWMI⋅= CPWMI I– PWMI on() tPWMI off() VPWMI L() VPWMI H() tPWMI on() tPWMI off() 1–⋅⋅ LN VPWMI L() VPWMI H() ⎛⎞ VPWMI L() VPWMI L() VPWMI H() tPWMI on() tPWMI off() VPWMI H()–⋅⋅ RPWMI tPWMI off() CPWMI LN VPWMI H() VPWMI L() ⎛⎞⋅
Data Sheet 15 Rev. 1.1, 2015-03-24 See Figure 10 for a typical external circuitry. Note: In case of junction temperatures above Tj(CRT) (Pos. 10.2.14) the device provides a temperature dependent current reduction feature as descirbed in Chapter 10.1.1. In case of output current reduction IIN_SET is reduced as well, which leads to increased turn on-times tPWMI(on), because the CPWMI is charged slower. The turn off-time tPWMI(off) remains the same. Figure 10 Typical circuit using internal PWM unit
6.3 Electrical Characteristics Inte rnal Supply / EN / PWMI Pin
Electrical Characteristics Internal Supply / EN / PWMI pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
6.3.1 Current consumption,
IS(sleep) –0 . 12µ A 1) VEN = 0.5 V Tj < 85 °C VS = 18 V VOUTx = 3.6 V
6.3.2 Current consumption,
IS(on) 1.7 1.0 1.75 mA 2) VPWMI= 0.5 V IIN_SET = 0µ A Tj < 105 °C VS = 18 V VOUTx = 3.6V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin RSET VBATT GND Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1 10kΩ N-1 PWMI CN- 1 RPWMI CPWMI DC/DC control FB
Data Sheet 16 Rev. 1.1, 2015-03-24 TLD1326EL PWMI Pin
6.3.3 Current consumption,
device disabled via IN_SET IS(dis,IN_SET) 1.65 0.9 1.7 mA 2) VS = 18 V Tj < 105 °C VIN_SET = 5 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin
6.3.4 Current consumption,
IS(dis,PWMI) 1.9 1.0 2.0 mA 2) VS = 18 V Tj < 105 °C VPWMI= 3.4 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin
6.3.5 Current consumption,
active mode in single fault detection condition IS(fault) 6.0 4.9 5.9 mA 2) VS = 18 V Tj < 105 °C RSET = 12 kΩ VPWMI= 0.5 V VOUTx = 18 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin 6.3.6 Power-on reset delay time 3) tPOR –– 2 5 µ s 1) VS = VEN =0 → 13.5 V VOUTx(nom) = 3.6 ± 0.3V IOUTx = 80% IOUTx(nom)
6.3.7 Required supply voltage for
VS(on) –– 4V VEN = 5.5 V VOUTx = 3 V IOUTx =5 0 % IOUTx(nom)
6.3.8 Required supply voltage for
VS(CC) –– 5 . 2 V VEN = 5.5 V VOUTx = 3.6 V IOUTx ≥ 90% IOUTx(nom) 6.3.9 EN turn on threshold VEN(on) –– 2 . 5 V – 6.3.10 EN turn off threshold VEN(off) 0.8 – – V –
6.3.11 EN input current during low
IEN(LS) –– 1 . 8 m A 1) VS = 4.5 V Tj < 105 °C VEN = 5.5 V Electrical Characteristics Internal Supply / EN / PWMI pin (cont’d) Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Data Sheet 17 Rev. 1.1, 2015-03-24
6.3.12 EN high input current IEN(H)
0.1 0.1 1.65 0.45 mA Tj < 105 °C VS = 13.5 V, VEN = 5.5 V VS = 18 V, VEN = 5.5 V VS = VEN = 18 V 1) VS = 18 V, REN = 10 kΩ between VS and EN-pin
6.3.13 PWMI (active low)
(outputs on)
6.3.14 PWMI(active low)
(outputs off)
6.3.15 PWMI
VPWMI(H) - VPWMI(L)
6.3.16 PWMI (active low)
active channels (voltage <VPWMI(L)) IPWMI(on) IIN_SET *3.1 IIN_SET *4 IIN_SET *4.9 IIN_SET = 100 µA VPWMI= 1.7 V VEN = 5.5 V VS = 8...18 V
6.3.17 PWMI(active low)
IPWMI(off) -5 – 5 µA VPWMI= 5 V VEN = 5.5 V VS = 8...18 V 1) Not subject to production test, specified by design 2) The total device current consumption is the sum of the currents IS and IEN(H), please refer to Pos. 6.3.12 3) See also Figure 4 4) Parameter valid if an external PWM signal is applied 5) If TTL level compatibility is required, use µC open drain output with pull up resistor Electrical Characteristics Internal Supply / EN / PWMI pin (cont’d) Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Data Sheet 18 Rev. 1.1, 2015-03-24 TLD1326EL FB Pin 7F B P i n The following block diagram shows the feedback pin functionality. Figure 11 Block Diagram FB pin
7.1 DC/DC Control
With the FB pin the LITIXTM Basic IC realizes the dynamic overhead control. The IC provides a voltage feedback to an external DC/DC converter. Using the circuit shown in Figure 20 it is possible to adjust the DC/DC output voltage in a way that the voltage drop over the output st ages of the LITIX TM Basic IC is minimized - dynamic overhead control. This leads to a significant reduction of the overall driver’s power dissipation and an increased system efficiency. Figure 21 shows the same concept but, using a higher number of LEDs per LED chain (please note that the cathode of the LED chain is connected to VIN). Note: For correct output current control and dynamic overhead control the parameters as specified in Pos. 7.2.1 the FB regulation voltage VFB(nom). The resistor RFB(PD) can be dimensioned by applying equations Equation (8) and Equation (9). The following parameters are required:
- VOUT represents the maximum LED loads forward voltage, i.e. number of LEDs multiplied with the maximum LED forward voltage. Temperature drifts of the LED’s forward voltage needs to be considered!
- VBO represents the DC/DC output voltage, which is predefined by the feedback resistors (Figure 20: RFB1, RFB2, Figure 21: RFB1, RFB2, RFB3). Please refer to the according DC/DC device data sheet for the dimensioning of those resistors.
- nlen represents the numbers of LITIXTM Basics using the longest LED-chains (e.g. if there are 3 devices connected to one DC/DC converter and two devices using LED chains with 7 LEDs and one device is used with LED chain lengths of 6 LEDs the according nlen =2 . )
- β represents the DC gain of the external bipolar transistor, which is connected to the DC/DC’s feedback pin. (8) (9) FB OUT1 OUT2 OUT3 Output voltage feedback IFB(SOC) RFB PD min,() min VOUT 0.5 V– 41 0 5– A⋅ nlen VBO VOUT–1 . 1 V– nlen RFB PD max,() VOUT 1.1 V– VBO VOUT– RFB1 β 1+
Data Sheet 19 Rev. 1.1, 2015-03-24
7.2 Electrical Characteristics FB Pin
Electrical Characteristics FB pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
7.2.1 FB regulation voltage VFB(nom) (VOUT -
1)*0.9 VOUT -1 – V IFB(SOC) = 25 µA
7.2.2 FB operating voltage at
VPS(FB) = VS - VOUTx VPS(FB) –– 1 0 V 1) 1) Not subject to production test, specified by design
Data Sheet 20 Rev. 1.1, 2015-03-24 TLD1326EL IN_SET Pin
8 IN_SET Pin
The IN_SET pin is a multiple function pin for output current definition, input and diagnostics: Figure 12 Block Diagram IN_SET pin
8.1 Output Current Ad justment via RSET
The output current for all three channels can only be adjusted simultaneously. The current adjustment can be done by placing a low power resistor (RSET) at the IN_SET pin to ground. The dimensioning of the resistor can be done using the formula below: (10) is defined by the resistor itself and the reference voltage VIN_SET(ref), which is applied to the IN_SET during supplied device.
8.2 Smart Input Pin
The IN_SET pin can be connected via RSET to the open-drain output of a µC or to an external NMOS transistor as described in Figure 13. This signal can be used to turn off the output stages of the IC. A minimum IN_SET current of IIN_SET(act) is required to turn on the output stages. This feature is implemented to prevent glimming of LEDs caused by leakage currents on the IN_SET pin, see Figure 15 for details. In addition, the IN_SET pin offers the Therefore, the device has two voltage domains at the IN_SET-pin, which is shown in Figure 16. Figure 13 Schematics IN_SET interface to µC IIN_SET VIN_SET(N-1) IN_SET GND VIN_SET Logic RSET k IOUT RSET/2 Microcontroller (e.g. XC866) OUT VDDP = 5 V Current adjustIN_SET GNDBasic LED Driver RSET/2 IN
Data Sheet 22 Rev. 1.1, 2015-03-24 TLD1326EL IN_SET Pin Figure 16 Voltage domains for IN_SET pin, if ST pin is connected to GND VIN _ SET( r ef )ma x VIN_ S E T(N -1) m in VIN_SET VI N_ SET (N -1 ) ma x Normal operation and high temperature current reduction range Diagnostic voltage range
Data Sheet 23 Rev. 1.1, 2015-03-24
9 Load Diagnosis
9.1 N-1 Detection
The N-1 diagnosis is specially designed to detect error conditions in LED arrays with multiple LED chains used for one light function. If one LED within one chain fails in open condition the respective LED chain is off. Different automotive applications require a complete deactivation of a light function, if the desired brightness of the function (LED array) can not be achieved due to an internal error condition. Such a deactivation feature is integrated in the LITIXTM Basic IC. The functionality of the N-1 pin is shown in the following block diagram: Figure 17 Block Diagram N-1 pin In applications, where more than one LITIXTM Basic IC is used, the IN_SET pins can be connected via the PWMI pins as shown in Figure 20 and Figure 21. This circuit can be used to dis able all output stages (of all LITIX TM Basic ICs) during an open load event on one channel. The outputs are deactivated after a N-1 filter time tN-1, which is defined by the charging current IN-1 (Pos. 9.3.6). The time is adjustable with a capacitor connected to the N-1 pin according the following equation: (11) IN-1 VN-1 N-1 Output Control ttyp CN1– VN1 t h()–⋅ IN1–
Data Sheet 24 Rev. 1.1, 2015-03-24 TLD1326EL Load Diagnosis Figure 18 IN_SET behavior during open load condition The N-1 status is latched. The output stages can be re-enabled by a Low to High transition at the EN pin or by a Power on reset. To provide a Limp Home functionality (l ower number of LEDs instead of complete deactivation) in the case of a partially damaged LED array, the N-1 filter time tN-1 can be used. If a PWM signal with an ON-time of less than tN-1 is applied to the VS and EN pins, the N-1 detection feature will not be activated. If there is more than one device used for N-1 detection the maximum number of devices, which can be connected as shown in Figure 20 and Figure 21, is limited to nN-1. The maximum number of devices in N-1 configuration is t tN-1 VOUT t VF VN- 1(th ) VS VN-1 t VIN_SET( r e f ) VIN _ SET( N-1) VIN_SET open load occurs open load disappears VS –V PS(N- 1) t VEN( o ff ) VEN( on) VEN tON(EN) Slope depends on R SET
Data Sheet 25 Rev. 1.1, 2015-03-24 calculated according to Equation (12), and the precondition of Equation (13) has to be fulfilled. The pull-down resistor RPWMI is calculated according to Equation (14) and Equation (15). (12) (13) (14) (15) VF represents the voltage drop across the diode between the IN_SET- and the PWMI-pin. Note: If one channel of the device should not be used, the according output needs to be connected to GND, which leads to a disabling of this output. Note: In case of a double fault, where the loads of two channels are faulty at the same time, the device operates as in normal operation. This feature is implemented to avoid any unwanted switch off during significant supply voltage drops. Please refer to Chapter 9.2.
9.2 Double Fault Conditions
The TLD1326EL has an integrated double fault detection feature. This feature is implemented to detect significant supply voltage drops. During such supply voltage drops close to the forward voltage of the LEDs the drivers outputs remain active. In case of load faults on two or more outputs within the time period tN-1 the device disables the diagnosis to avoid any uncorrect open load diagnosis during low supply voltages close to the forward voltages of the connected LED chains. If the faults between tw o or three channels happen with a delay of longer than tOL the double fault detection feature is not active, i.e. the device is not turned on.
9.3 Electrical Characteristics IN _SET Pin and Load Diagnosis
Electrical Characteristics IN_SET pin and Load Diagnosis Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET = 12 kΩ, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
9.3.1 IN_SET reference
VIN_SET(ref) 1.19 1.23 1.27 V 1) VOUTx =3 . 6V Tj = 25...115 °C 9.3.2 IN_SET N_1 voltage VIN_SET(N-1) 4– 5 . 5 V 1) VS > 8 V Tj = 25...150 °C VS = VOUTx (OL) x nN1– IIN_SET(OL,min) VPWMI H max,() VF+ RSET(min) ⎛⎞ VPWMI H min,() RSET(min)⋅⋅ VPWMI H max,() 4 VIN_SET(max)⋅⋅ VPWMI H min,() VIN_SET(min) R⋅ SET(min)⋅ VIN_SET(max)() RSET(max)⋅ RPWMI(min) VPWMI H max,() IIN_SET(OL,min) VPWMI H max,() VF+ RSET(max) RPWMI(max) VPWMI H min,() nN1– 4 VIN_SET(max) RSET(min)
Data Sheet 26 Rev. 1.1, 2015-03-24 TLD1326EL Load Diagnosis Tj = 25...150 °C VS = VOUTx (OL) x 9.3.4 IN_SET N_1 current IIN_SET(N-1) 1.5 – 7.4 mA 1) VS > 8 V Tj = 25...150 °C VIN_SET = 4 V VS = VOUTx (OL)
9.3.6 N-1 output current IN-1 12 20 28 µA VS > 8 V
VN-1 = 2 V
9.3.7 N-1 detection voltage
VPS(N-1) = VS - VOUTx VPS(N-1) 0.2 – 0.4 V VS >8V
9.3.8 IN_SET activation
current without turn on of output stages IIN_SET(act) 2 – 15 µA See Figure 15 1) Not subject to production test, specified by design Electrical Characteristics IN_SET pin and Load Diagnosis (cont’d) Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET = 12 kΩ, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Data Sheet 27 Rev. 1.1, 2015-03-24
10 Power Stage
The output stages are realized as high side current sources with a current of 120 mA. During off state the leakage current at the output stage is minimized in order to prevent a slightly glowing LED. The maximum current of each channe l is limited by the power dissipation and used PCB cooling areas (which results in the applications RthJA). For an operating current control loop the supply and output voltages according to the following parameters have to be considered:
- Required supply voltage for current control VS(CC), Pos. 6.3.8
- Voltage drop over output stage during current control VPS(CC), Pos. 10.2.6
- Required output voltage for current control VOUTx(CC), Pos. 10.2.7
10.1 Protection
The device provides embedded protective functions, wh ich are designed to prevent IC destruction under fault conditions described in this data sheet. Fault condit ions are considered as “out side” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.
10.1.1 Over Load Behavior
An over load detection circuit is integrated in the LITIXTM Basic IC. It is realized by a temperature monitoring of the output stages (OUTx). As soon as the junction temperature exceeds the current reduction temperature threshold Tj(CRT) the output current will be reduced by the device by re ducing the IN_SET reference voltage VIN_SET(ref). This feature avoids LED’s flickering during static output overload conditions. Furthermore, it protects LEDs against over temperature, which are mounted thermally close to the de vice. If the device temper ature still increases, th e three output currents decrease close to 0 A. As soon as the device cools down the output currents rise again. Figure 19 Output current reduction at high temperature Note: This high temperature output current reduction is realized by reducing the IN_SET reference voltage voltage (Pos. 9.3.1). In case of very high power loss applied to the device and very high junction temperature the output current may drop down to IOUTx = 0 mA, after a slight cooling down the current increases again.
10.1.2 Reverse Battery Protection
The TLD1326EL has an integrated reverse battery protection feature. This feature protects the driver IC itself, but also connected LEDs. The output reverse current is limited to IOUTx(rev) by the reverse battery protection. Tj IOUT Tj(CRT ) VIN_SET
Data Sheet 28 Rev. 1.1, 2015-03-24 TLD1326EL Power Stage Note: Due to the reverse battery protection a reverse protection diode for the light module may be obsolete. In case of high ISO-pulse requirements and only minor protecting components like capacitors a reverse protection diode may be reasonable. The external protection circuit needs to be verified in the application.
10.2 Electrical Charact eristics Power Stage
Electrical Characteristics Power Stage Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
10.2.1 Output leakage current IOUTx(leak)
µA VEN = 5.5 V IIN_SET = 0µ A VOUTx =2 . 5V Tj = 150 °C 1) Tj = 85 °C
10.2.2 Output leakage current in
IOUTx(leak,B2B) ––5 0 µ A 1) VEN = 5.5 V IIN_SET =0µ A VOUTx = VS = 40 V
10.2.3 Reverse output current -IOUTx(rev) ––1µ A 1) VS = -16 V
Output load: LED with break down voltage <-0 . 6V
10.2.4 Output current accuracy
1)Tj = 25...115 °C VS = 8...18 V VPS = 2 V RSET = 6...12 kΩ RSET = 30 kΩ
10.2.5 Output current accuracy
VS = 8...18 V VPS = 2 V RSET = 6...12 kΩ RSET = 30 kΩ
10.2.6 Voltage drop over power
stage during current control VPS(CC) = VS - VOUTx VPS(CC) 0.75 – – V 1) VS = 13.5 V RSET = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSET)
10.2.7 Required output voltage for
VOUTx(CC) 2.3 – – V 1) VS = 13.5 V RSET = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSET) 10.2.8 Maximum output current IOUT(max) 120 – – mA RSET = 4.7 kΩ The maximum output current is limited by the thermal conditions. Please refer to
Data Sheet 29 Rev. 1.1, 2015-03-24 10.2.9 PWMI turn on time tON(PWMI) ––1 5 µ s 2) VS = 13.5 V RSET = 12 kΩ PWMI → L IOUTx = 80% of (kLT(typ)/RSET) 10.2.10 PWMI turn off time tOFF(PWMI) ––1 0 µ s 2) VS = 13.5 V RSET = 12 kΩ PWMI → H IOUTx = 20% of (kLT(typ)/RSET) 10.2.11 IN_SET turn on time tON(IN_SET) ––1 5 µ s VS = 13.5 V IIN_SET = 0 → 100 µA IOUTx = 80% of (kLT(typ)/RSET) 10.2.12 IN_SET turn off time tOFF(IN_SET) ––1 0 µ s VS = 13.5 V IIN_SET =1 0 0→ 0µ A IOUTx = 20% of (kLT(typ)/RSET) 10.2.13 VS turn on time tON(VS) ––2 0 µ s 1) 3) VEN =5 . 5V RSET = 12 kΩ VS = 0 → 13.5 V IOUTx = 80% of (kLT(typ)/RSET)
10.2.14 Current reduction
Tj(CRT) –1 4 0 –° C 1)IOUTx = 95% of (kLT(typ)/RSET)
10.2.15 Output current during
IOUT(CRT) 85% of (kLT(typ)/ RSET) ––A 1) RSET =1 2k Ω Tj = 150 °C 1) Not subject to production test, specified by design 2) see also Figure 8 3) see also Figure 6 Electrical Characteristics Power Stage (cont’d) Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Data Sheet 30 Rev. 1.1, 2015-03-24 TLD1326EL
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 20 System diagram DC/DC control Buck + N-1 detection BDS BUO FB GND COMP PWMI EN VS Cbootstrap DBU LBU CBU1 CCOMP RCOMP TLD5085 VBatt CS DRV RFB1 RFB2 VS VBO VBO 1nF RSET Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1N-1 PWMI CN-1 DC/DC control FB RSET Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1N-1 PWMI CN-1 DC/DC control FB RFB(PD) CVS =4 .7n F ** For EMI improvement , if required . CVS =4.7nF LITIXTM Basic LITIXTM Basic
Data Sheet 31 Rev. 1.1, 2015-03-24 Figure 21 System diagram DC/DC control Boost + N-1 detection Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
11.1 Further Application Information
- For further information you may contact http://www.infineon.com/ FBH FBL OVFB SWO SWCS GND SGND TLD5095 EN / PWMI COMP ST IVCC RFREQ RCOMP CCOMP CIVCC IN VBATT VIN FREQ / SYNC CIN DRV LBO DBO TSW RCS ROVH ROVL CBO RFB1 RFB2 RFB3PWMO VBO VBO RPWMI 1nF VIN RSET Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1N-1 PWMI CN-1 DC/DC control FB VIN RSET Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1N-1 PWMI CN-1 DC/DC control FB RFB(PD) * For EMI improvement , if required , ≈10nF 10kΩ CVS=4.7nF 10kΩ CVS=4.7nF LITIXTM Basic LITIXTM Basic
Data Sheet 32 Rev. 1.1, 2015-03-24 TLD1326EL Package Outlines Figure 22 PG-SSOP14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad Dimensions in mm For further information on alternative packages, please visit our website: http://www.infineon.com/packages.
Revision History
Data Sheet 33 Rev. 1.1, 2015-03-24 Revision Date Changes 1.0 2013-08-08 Inital revision of data sheet 1.1 2015-03-19 Updated parameters K LT and KALL in the chapter Power Stage.
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