TLD1310EL_15 INFINEON | Alldatasheet
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Rev. 1.1, 2015-03-19 TLD1310EL
3 Channel High Side Current Source
Infineon ® LITIX TM Basic
Data Sheet 2 Rev. 1.1, 2015-03-19 TLD1310EL
TLD1310EL PG-SSOP14 TLD1310EL Data Sheet 3 Rev. 1.1, 2015-03-19
Features
- 3 Channel device with integrated output stages (current sources), optimized to drive LEDs
- Output current up to 120mA per channel
- Low current consumption in sleep mode
- PWM-operation supported via VS- and EN-pin
- Output current adjustable via external low power resistor and possibility to connect PTC resistor for LED protection during over temperature conditions
- Reverse polarity protection
- Overload protection
- Undervoltage detection
- Wide temperature range: -40 °C < T j < 150 °C
- PG-SSOP14 package with exposed heatslug
- Green Product (RoHS compliant)
- AEC Qualified
Description
TM Basic TLD1310EL is a three channel high side driver IC with integrated output stages. It is designed to control LEDs with a current up to 120 mA. In typical au tomotive applications the device is capable to drive i.e. 3 red LEDs per chain (total 9 LEDs) with a current up to 60mA, which is limited by thermal cooling aspects. The output current is controlled practically independent of load and supply voltage changes. Table 1 Product Summary Operating voltage VS(nom) 5.5 V… 40 V Maximum voltage VS(max) VOUTx(max) 40 V Nominal output (load) current IOUTx(nom) 60 mA when using a supply voltage range of 8V - 18V (e.g. Automotive car battery). Currents up to IOUT(max) possible in applications with low thermal resistance RthJA Maximum output (load) current IOUTx(max) 120 mA; depending on thermal resistance RthJA Output current accuracy at RSET = 12 kΩ kLT 750 ± 7% Current consumption in sleep mode IS(sleep,typ) 0.1 µA
Data Sheet 4 Rev. 1.1, 2015-03-19 TLD1310EL Overview Protective functions - ESD protection - Under voltage lock out - Over Load protection - Over Temperature protection - Reverse Polarity protection
Applications
Designed for exterior LED lighting applications such as tail/brake light, turn indicator, position light, side marker,... The device is also well suited for in terior LED lighting applications such as ambient lighting, interior illumination and dash board lighting.
Data Sheet 5 Rev. 1.1, 2015-03-19
2 Block Diagram
Figure 1 Basic Block Diagram Output control OUT2 Internal supply Thermal protection Current adjust TLD1310EL GND EN VS IN_SET OUT3 OUT1 GNDS
Data Sheet 6 Rev. 1.1, 2015-03-19 TLD1310EL Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration TLD1310EL EP NC NC OUT3 OUT2EN OUT1NC VS VS GNDS IN_SET NC 8N C GND
Data Sheet 7 Rev. 1.1, 2015-03-19
3.2 Pin Definitions and Functions
1, 2 VS – Supply Voltage; battery supply, connect a decoupling capacitor (100 nF - 1 µF) to GND 3E NI Enable pin 4N C – Pin not connected 5G N D S – 1) GNDS; Signal GND, connect to GND 1) Connect all GND-pins together.
6 IN_SET I/O Input / SET pin; Connect a low power resistor to adjust the output current
7N C – Pin not connected 8N C – Pin not connected 9G N D – 1) Ground
10 NC – Pin not connected
11 OUT1 O Output 1
12 OUT2 O Output 2
13 OUT3 O Output 3
14 NC – Pin not connected
GND – 1) Exposed Pad; connect to GND in application
Data Sheet 8 Rev. 1.1, 2015-03-19 TLD1310EL General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin for input pins (I), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) 1) Not subject to production test, specified by design Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. Voltages
4.1.1 Supply voltage
VS -16 40 V –
4.1.2 Input voltage EN VEN -16 40 V –
4.1.3 Input voltage EN related to VS VEN(VS) VS - 40 VS + 16 V –
4.1.4 Input voltage EN related to VOUTx
-16 40 V –
4.1.5 Output voltage VOUTx -1 40 V –
4.1.6 Power stage voltage
VPS = VS - VOUTx VPS -16 40 V – 4.1.7 IN_SET voltage VIN_SET -0.3 6 V – Currents
4.1.8 IN_SET current IIN_SET –2m A –
4.1.9 Output current IOUTx –1 3 0 m A –
4.1.10 Junction temperature Tj -40 150 °C–
4.1.11 Storage temperature Tstg -55 150 °C–
4.1.12 ESD resistivity to GND VESD -2 2 kV Human Body
Model (100 pF via 1.5 kΩ)2) 2) ESD susceptibility, Human Body Model “HB M” according to ANSI/ESDA/JEDEC JS-001-2011
4.1.13 ESD resistivity all pins to GND VESD -500 500 V CDM 3)
3) ESD susceptibility, Charged Device Model “CDM” according to JESD22-C101E
4.1.14 ESD resistivity corner pins to GND VESD -750 750 V CDM 3)
General Product Characteristics Data Sheet 9 Rev. 1.1, 2015-03-19
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions Min. Max.
4.2.15 Supply voltage range for
VS(nom) 5.5 40 V –
4.2.16 Power on reset threshold VS(POR) –5V VEN = VS
RSET =1 2k Ω IOUTx =8 0 %IOUTx(nom) VOUTx =2 . 5V
4.2.17 Junction temperature Tj -40 150 °C–
Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
4.3.1 Junction to Case RthJC –81 0 K / W 1) 2)
1) Not subject to production test, specifi ed by design. Based on simulation results. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed Pad are fixed to ambient temperature). Ta = 85°C, Total power dissipation 1.5 W.
4.3.2 Junction to Ambient 1s0p board RthJA1
K/W 1) 3) Ta =8 5° C Ta = 135 °C 3) The RthJA values are according to Jedec JESD51-3 at natural convection on 1s0p FR4 board. The product (chip + package) distributed statically and homogenously over all power stages.
4.3.3 Junction to Ambient 2s2p board RthJA2
K/W 1) 4) Ta =8 5° C Ta = 135 °C 4) The RthJA values are according to Jedec JESD51-5,-7 at natural convection on 2s2p FR4 board. The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (outside 2 x 70 µm Cu, inner 2 x 35µm Cu). Where applicable, a thermal via array under the exposed pad contacted the first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all power stages.
Data Sheet 10 Rev. 1.1, 2015-03-19 TLD1310EL EN Pin 5E N P i n The EN pin is a dual function pin: Figure 3 Block Diagram EN pin Note: The current consumption at the EN-pin IEN needs to be added to the total device current consumption. The total current consumption is the sum of the currents at the VS-pin IS and the EN-pin IEN.
5.1 EN Function
If the voltage at the pin EN is below a threshold of VEN(off) the LITIXTM Basic IC will enter Sleep mode. In this state all internal functions are switched off, the current consumption is reduced to IS(sleep). A voltage above VEN(on) at this pin enables the device after the Power on reset time tPOR. Figure 4 Power on reset VEN EN Output Control Internal Supply VEN t t 80 % tPORIOUT 100 % t VS
Data Sheet 11 Rev. 1.1, 2015-03-19
5.2 Internal Supply Pin
The EN pin can be used to supply the internal logic. There are two typical application conditions, where this feature can be used: 1) In “DC/DC control Buck” configurations, where the voltage Vs can be below 5.5V. 2) In configurations, where a PWM signal is applied at the Vbatt pin of a light module. The buffer capacitor CBUF is used to supply the LITIX TM Basic IC during Vbatt low ( Vs low) periods. This feature can be used to minimize the to be considered. The capacitor can be calculated using the following formula: (1) See also a typical application drawing in Chapter 8. Figure 5 External circuit when applying a fast PWM signal on VBATT CBUF tLOW max() IEN LS() VS VD1– VSP O R()– RSET CBUF VBATT GND Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver GND EN VS IN_SET OUT3 OUT1 LITIXTM Basic
Data Sheet 12 Rev. 1.1, 2015-03-19 TLD1310EL EN Pin Figure 6 Typical waveforms when applying a fast PWM signal on VBATT The parameter tON(VS) is defined at Pos. 7.2.11. The parameter tOFF(VS) depends on the load and supply voltage VBATT characteristics.
5.3 EN Unused
In case of an unused EN pin, there are two different ways to connect it:
5.3.1 EN - Pull Up to VS
The EN pin can be connected with a pull up resistor (e.g. 10 k Ω) to Vs potential. In this configuration the LITIXTM Basic IC is always enabled.
5.3.2 EN - Direct Connection to VS
The EN pin can be connected directly to the VS pin (I C always enabled). This configuration has the advantage (compared to the configuration described in Chapter 5.3.1) that no additional external component is required. VBATT t t 20 % 80 % tON(VS)IOUT 100 % VEN t Switch off behavior depends on VBATT and load characteristics
Data Sheet 13 Rev. 1.1, 2015-03-19
5.4 Electrical Characteristics Internal Supply / EN Pin
Electrical Characteristics Internal Supply / EN pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET =1 2k Ω all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
5.4.1 Current consumption,
IS(sleep) –0 . 12µ A 1) VEN = 0.5 V Tj < 85 °C VS = 18 V VOUTx = 3.6 V 1) Not subject to production test, specified by design
5.4.2 Current consumption,
IS(on) 1.4 0.75 1.5 mA 2) IIN_SET = 0µ A Tj < 105 °C VS = 18 V VOUTx = 3.6V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin
5.4.3 Current consumption,
device disabled via IN_SET IS(dis,IN_SET) 1.4 0.7 1.4 mA 2) VS = 18 V Tj < 105 °C VIN_SET = 5 V VEN =5 . 5V VEN =1 8V 1) REN = 10 kΩ between VS and EN-pin 5.4.4 Power-on reset delay time 3) tPOR –– 2 5 µ s 1) VS = VEN =0 → 13.5 V VOUTx(nom) = 3.6 ± 0.3V IOUTx = 80% IOUTx(nom)
5.4.5 Required supply voltage for
VS(on) –– 4V VEN = 5.5 V VOUTx = 3 V IOUTx =5 0 % IOUTx(nom)
5.4.6 Required supply voltage for
VS(CC) –– 5 . 2 V VEN = 5.5 V VOUTx = 3.6 V IOUTx ≥ 90% IOUTx(nom) 5.4.7 EN turn on threshold VEN(on) –– 2 . 5 V – 5.4.8 EN turn off threshold VEN(off) 0.8 – – V –
5.4.9 EN input current during low
IEN(LS) –– 1 . 8 m A 1) VS = 4.5 V Tj < 105 °C VEN = 5.5 V
5.4.10 EN high input current IEN(H)
0.1 0.1 1.65 0.45 mA Tj < 105 °C VS = 13.5 V, VEN = 5.5 V VS = 18 V, VEN = 5.5 V VS = VEN = 18 V 1) VS = 18 V, REN = 10 kΩ between VS and EN-pin
Data Sheet 14 Rev. 1.1, 2015-03-19 TLD1310EL EN Pin 2) The total device current consumption is the sum of the currents IS and IEN(H), please refer to Pos. 5.4.10 3) See also Figure 4
IN_SET Pin Data Sheet 15 Rev. 1.1, 2015-03-19
6 IN_SET Pin
The IN_SET pin is a multiple function pin for output current definition and input: Figure 7 Block Diagram IN_SET pin
6.1 Output Current Ad justment via RSET
The output current for all three channels can only be adjusted simultaneously. The current adjustment can be done by placing a low power resistor (RSET) at the IN_SET pin to ground. The dimensioning of the resistor can be done using the formula below: (2) defined by the resistor itself and the reference voltage VIN_SET(ref), which is applied to the IN_SET during supplied device.
6.2 Input Pin
The IN_SET pin can be connected via RSET to the open-drain output of a µC or to an external NMOS transistor as described in Figure 8. This signal can be used to turn off the output stages of the IC. A minimum IN_SET current of IIN_SET(act) is required to turn on the output stages. This feature is implemented to prevent glimming of LEDs caused by leakage currents on the IN_SET pin, see Figure 10 for details. Figure 8 Schematics IN_SET interface to µC The resulting switching times are shown in Figure 9: IIN_SET IN_SET GND VIN_SET RSET k IOUT RSET Microcontroller (e.g. XC866) OUT VDDP = 5 V Current adjustIN_SET GNDBasic LED DriverLITIXTM Basic
IN_SET Pin Data Sheet 17 Rev. 1.1, 2015-03-19
6.3 Electrical Charact eristics IN_SET Pin
Electrical Characteristics IN_SET pin Unless otherwise specified: VS = 5.5 V to 40 V, Tj = -40 °C to +150 °C, RSET = 12 kΩ, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
6.3.1 IN_SET reference
VIN_SET(ref) 1.19 1.23 1.27 V 1) VOUTx =3 . 6V Tj = 25...115 °C 1) Not subject to production test, specified by design
6.3.2 IN_SET activation
current without turn on of output stages IIN_SET(act) 2 – 15 µA See Figure 10
Data Sheet 18 Rev. 1.1, 2015-03-19 TLD1310EL Power Stage
7 Power Stage
The output stages are realized as high side current sources with a current of 120 mA. During off state the leakage current at the output stage is minimized in order to prevent a slightly glowing LED. The maximum current of each channe l is limited by the power dissipation and used PCB cooling areas (which results in the applications RthJA). For an operating current control loop the supply and output voltages according to the following parameters have to be considered:
- Required supply voltage for current control VS(CC), Pos. 5.4.6
- Voltage drop over output stage during current control VPS(CC), Pos. 7.2.6
- Required output voltage for current control VOUTx(CC), Pos. 7.2.7
7.1 Protection
The device provides embedded protective functions, wh ich are designed to prevent IC destruction under fault conditions described in this data sheet. Fault condit ions are considered as “out side” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.
7.1.1 Over Load Behavior
An over load detection circuit is integrated in the LITIXTM Basic IC. It is realized by a temperature monitoring of the output stages (OUTx). As soon as the junction temperature exceeds the current reduction temperature threshold Tj(CRT) the output current will be reduced by the device by re ducing the IN_SET reference voltage VIN_SET(ref). This feature avoids LED’s flickering during static output overload conditions. Furthermore, it protects LEDs against over temperature, which are mounted thermally close to the de vice. If the device temper ature still increases, th e three output currents decrease close to 0 A. As soon as the device cools down the output currents rise again. Figure 11 Output current reduction at high temperature Note: This high temperature output current reduction is realized by reducing the IN_SET reference voltage voltage (Pos. 6.3.1). In case of very high power loss applied to the device and very high junction temperature the output current may drop down to IOUTx = 0 mA, after a slight cooling down the current increases again.
7.1.2 Reverse Battery Protection
The TLD1310EL has an integrated reverse battery protection feature. This feature protects the driver IC itself, but also connected LEDs. The output reverse current is limited to IOUTx(rev) by the reverse battery protection. Tj IOUT Tj(CRT ) VIN_SET
Data Sheet 19 Rev. 1.1, 2015-03-19 Note: Due to the reverse battery protection a reverse protection diode for the light module may be obsolete. In case of high ISO-pulse requirements and only minor protecting components like capacitors a reverse protection diode may be reasonable. The external protection circuit needs to be verified in the application.
7.2 Electrical Charact eristics Power Stage
Electrical Characteristics Power Stage Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
7.2.1 Output leakage current IOUTx(leak)
µA VEN = 5.5 V IIN_SET = 0µ A VOUTx =2 . 5V Tj = 150 °C 1) Tj = 85 °C
7.2.2 Output leakage current in
IOUTx(leak,B2B) ––5 0 µ A 1) VEN = 5.5 V IIN_SET =0µ A VOUTx = VS = 40 V
7.2.3 Reverse output current -IOUTx(rev) ––1µ A 1) VS = -16 V
Output load: LED with break down voltage <-0 . 6V
7.2.4 Output current accuracy
1)Tj = 25...115 °C VS = 8...18 V VPS = 2 V RSET = 6...12 kΩ RSET = 30 kΩ
7.2.5 Output current accuracy
VS = 8...18 V VPS = 2 V RSET = 6...12 kΩ RSET = 30 kΩ
7.2.6 Voltage drop over power
stage during current control VPS(CC) = VS - VOUTx VPS(CC) 0.75 – – V 1) VS = 13.5 V RSET = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSET)
7.2.7 Required out put voltage for
VOUTx(CC) 2.3 – – V 1) VS = 13.5 V RSET = 12 kΩ IOUTx ≥ 90% of (kLT(typ)/RSET) 7.2.8 Maximum output current IOUT(max) 120 – – mA RSET = 4.7 kΩ The maximum output current is limited by the thermal conditions. Please refer to
Data Sheet 20 Rev. 1.1, 2015-03-19 TLD1310EL Power Stage 7.2.9 IN_SET turn on time tON(IN_SET) ––1 5 µ s VS = 13.5 V IIN_SET = 0 → 100 µA IOUTx = 80% of (kLT(typ)/RSET) 7.2.10 IN_SET turn off time tOFF(IN_SET) ––1 0 µ s VS = 13.5 V IIN_SET =1 0 0→ 0µ A IOUTx = 20% of (kLT(typ)/RSET) 7.2.11 VS turn on time tON(VS) ––2 0 µ s 1) 2) VEN =5 . 5V RSET = 12 kΩ VS = 0 → 13.5 V IOUTx = 80% of (kLT(typ)/RSET)
7.2.12 Current reduction
Tj(CRT) –1 4 0 –° C 1)IOUTx = 95% of (kLT(typ)/RSET)
7.2.13 Output current during
IOUT(CRT) 85% of (kLT(typ)/ RSET) ––A 1) RSET =1 2k Ω Tj = 150 °C 1) Not subject to production test, specified by design 2) see also Figure 6 Electrical Characteristics Power Stage (cont’d) Unless otherwise specified: VS = 5.5 V to 18 V, Tj = -40 °C to +150 °C, VOUTx = 3.6 V, all voltages with respect to ground, positive current flowing into pin for input pins (I ), positive currents flowing out of the I/O and output pins (O) (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Application Information
Data Sheet 21 Rev. 1.1, 2015-03-19
8 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 12 Application Diagram Note: This is a very simplified example of an application circuit. In case of high ISO-pulse requirements a reverse protection diode may be used for LED protection. The function must be verified in the real application.
8.1 Further Application Information
- For further information you may contact http://www.infineon.com/ RSET VBATT GND Output control OUT2 Internal supply Thermal protection Current adjust Basic LED Driver EN VS IN_SET OUT3 OUT1 GNDGNDS ** For EMI improvement , if required . Cmo d=2.2µF ISO-Pulse protection circuit depending on requirements 10kΩ CVS =4 .7nF LITIXTM Basic
Data Sheet 22 Rev. 1.1, 2015-03-19 TLD1310EL Package Outlines
9 Package Outlines
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad Dimensions in mm For further information on alternative packages, please visit our website: http://www.infineon.com/packages.
Revision History
Data Sheet 23 Rev. 1.1, 2015-03-19 Revision Date Changes 1.0 2013-08-08 Inital revision of data sheet 1.1 2015-03-19 Updated parameters K LT and KALL in the chapter Power Stage.
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© 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.