TLD1173-1ET

TLD1173-1ET INFINEON | Alldatasheet

Document overview

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Technical content

Features

• Single channel device with integrated and protected output stage (current sink), optimized to drive LEDs
• High output current up to 400 mA
• Possibility to offload power consumption via low cost external resistor to allow maximum current driving capability (Power Shift)
• Fault management supports both 1-fail-all-OFF and 1-fail-all-ON
• Analog output current control input to adjust the output current
• Open load (OL), short to battery (SC) and thermal shutdown protections
• Intelligent fault management: up to 10 devices can share a common error network with only one external resistor
• Thermal derating function via external NTC resistor Potential applications
• Cost effective "stop"/"tail" function with shared and separated LEDs per function
• Automotive light functions like turn indicators, position, fog, stop/tail, DRL and side markers
• Animated light functions like sequential indicator and "welcome/goodbye" functions
• Interior lighting functions like ambient lighting, illumination and dash board lighting
• LED indicators for industrial applications and instrumentation Product validation Product validation according to AEC-Q100, Grade 1. Qualified for automotive applications.

Description

The TLD1173-1ET is a single channel low-side driver IC with integrated and protected output stage. It is designed to control LEDs with a current up to 400 mA as linear current sink (LCS). The power shift feature allows the device to reach maximum current driving capability by offloading power consumption to an external low cost resistor. Along with its integrated diagnostic features, it offers a simple and reliable solution compared to discrete solutions. The diagnostic features and thermal derating via external NTC resistor provide a reliable solution for high current applications. The configurable fault management allows up to 10 and more devices to share the same error network and to be combined in applications with other LITIX™ LED drivers, such other LITIX™ Basic+ products and LITIX™ TLD7002-16ES. TLD1173-1ET VS EN/DEN ACC/PWMI OUT SENSE GND R1R2 CVS VS RERRN ERRN/DEN RSENSE RNTC IREF RIREF D PS RPS DRP ERRN Product type Package Marking TLD1173-1ET TFDSO-16 117 TLD1173-1ET Datasheet Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document Rev.1.00 www.infineon.com 2024-10-14

Datasheet 2 Rev.1.00 2024-10-14

Datasheet 3 Rev.1.00 2024-10-14

1 Product description

Operating voltage VS(func) 5.5 V - 18 V Extended operating voltage VS(ext) 4.5 V - 36 V Maximum load current ISENSE(max) 400 mA Output current accuracy VSENSE(reg) ±4% with VSENSE = 400 mV Current consumption in sleep mode IVS(sleep, max) 3 μA Maximum current consumption during fault IVS(fault, ERRN) 850 μA Maximum dropout voltage VDR,CS(max) 0.6 V TLD1173-1ET Datasheet Datasheet 4 Rev.1.00 2024-10-14

2 Block diagram

D PS Power stage Power shift Current reference generation Analog output current control Internal supply Load diagnostic PWM control Figure 1 TLD1173-1ET Block diagram TLD1173-1ET Datasheet Datasheet 5 Rev.1.00 2024-10-14

3 Pin configuration

3.1 Pin assignment

3 IREF

4 GND

5 ACC/PWMI

6 SENSE

8 EN/DEN 9 ERRN/DEN

14 OUT

(top view) Figure 2 PG-TFDSO-16

3.2 Pin definitions and functions

Table 2 Pin definitions and functions Pin Symbol Function

16 VS Power supply voltage

4 GND Ground

Ground potential. Connect externally close to the chip

8 EN/DEN Output enable and diagnosis control input

Connect to VS via a resistor divider to enable OUT control and diagnosis capability

9 ERRN/DEN ERROR flag I/O and diagnosis control input

Open drain, active low. Connect to VS via pull-up resistor for ERROR flag capability only otherwise connect to VS via a resistor divider to enable diagnosis capability

6 SENSE Sense input

Connect to low ohmic accurate sense resistor

14 OUT Channel output pin

Open drain linear current sink. Connect to the target load

15 PS Power shift

Connect to external power resistor (table continues...) TLD1173-1ET Datasheet Datasheet 6 Rev.1.00 2024-10-14

Table 2 (continued) Pin definitions and functions Pin Symbol Function

2 D Disable/delay error input

Connect to a capacitor, leave open or connect to GND depending on the required diagnostic management

5 ACC/PWMI Analog current control and PWMI input pin

Connect to external low power resistor or apply a desired reference voltage to adjust the output current. Connect to external NTC to apply thermal derating. It is possible also to connect to an external open drain PWM controller

3 IREF Current reference generation

Connect to an external accurate low power resistor to generate a current reference 1,7,10, 11,12,13 NC Not connected Leave these pins open Exposed pad EP Exposed pad Used only for thermal dissipation purpose. Connect externally to GND close to the chip TLD1173-1ET Datasheet Datasheet 7 Rev.1.00 2024-10-14

4 General product characteristics

4.1 Absolute maximum ratings

Table 3 Absolute maximum ratings 1) TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Voltages Supply voltage VS -0.3 – 40 V – PRQ-32 EN/DEN voltage VEN/DEN -0.3 – 40 V – PRQ-55 Output voltage VOUT -0.3 – 40 V – PRQ-56 Power shift voltage VPS -0.3 – 40 V – PRQ-59 Sense voltage VSENSE -0.3 – 0.9 V – PRQ-63 ERRN/DEN voltage VERRN/DEN -0.3 – 40 V – PRQ-61 D voltage VD -0.3 – 5.5 V – PRQ-175 ACC/PWMI voltage VACC/PWMI -0.3 – 5.5 V – PRQ-64 IREF voltage VIREF -0.3 – 5.5 V – PRQ-176 Temperatures Junction temperature TJ_ABS -40 – 150 °C – PRQ-39 Storage temperature TSTG -55 – 150 – – PRQ-40 ESD robustness ESD robustness all pins (HBM) VESD(HBM) -2 – 2 kV ESD robustness, Human Body Model “HBM” according to AEC Q100-002 PRQ-53 ESD robustness all pins (CDM) VESD(CDM) -500 – 500 V ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D PRQ-41 ESD robustness corner pins (CDM) VESD(CDM) CR -750 – 750 V ESD robustness, Charged Device Model “CDM” according to AEC Q100-011 Rev.D PRQ-54 1) Not subject to production test, specified by design Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation. TLD1173-1ET Datasheet Datasheet 8 Rev.1.00 2024-10-14

4.2 Functional range

TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Voltages Supply voltage for operating range VS(func) 5.5 – 18 V – PRQ-33 Extended supply voltage for operating range VS(ext) 4.5 – 36 V – PRQ-71 Currents Channel output current ISENSE(func) 5 – 400 mA – PRQ-224 Power dissipation Max. static and dynamic power dissipation Pmax 1.5 W TA = 85°C and RthJA =

42 K/W

Junction temperature TJ(func) -40 – 150 °C – PRQ-72 Note: Within the functional or operating range, the IC operates as described in the circuit description. Within the Extended Operation range, parameters deviations are possible. The electrical characteristics are specified within the conditions given in the electrical characteristics table.

4.3 Thermal resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org Table 5 Thermal resistance VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Junction to top ΨJTOP – 8 – K/W 1) PRQ-34 Junction to case RthJC – 8 – K/W 2) PRQ-49 Junction to ambient 1s0p board RthJA1 – 64 – K/W 3) TA = 85°C PRQ-48 Junction to ambient 2s2p board RthJA2 – 42 – K/W 4) TA = 85°C PRQ-180 1) Specified ΨJTOP is derived under natural convention conditions and provide a correlation between the junction temperature and the temperature on the package top surface. TA = 85°C. Total power dissipation = 1.5 W 2) Specified RthJC is simulated at natural convention on a cold plate setup (all pins and exposed pad are fixed at ambient temperature). TA = 85°C. Total power dissipation = 1.5 W TLD1173-1ET Datasheet Datasheet 9 Rev.1.00 2024-10-14

3) Specified RthJA1 is generated in accordance with JEDEC JESD51-3 standards at natural convection on FR4 1s0p board. The simulation has and homogenously over all power stages 4) Specified RthJA2 is generated in accordance with JEDEC JESD51-5,-7 standards at natural convection on FR4 2s2p board. The simulation has been performed on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers ( 2 x 70 μm Cu, 2 x 35 μm Cu). A total of six thermal via (∅ = 0.3 mm, plating 25 μm) is placed under the exposed pad contacting the first inner copper layer. Total power dissipation 1.5W distributed statically and homogenously over all power stages TLD1173-1ET Datasheet Datasheet 10 Rev.1.00 2024-10-14

5 Internal supply

This chapter describes the internal supply, its main parameters and functionality.

5.1 Description

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied at the EN/DEN pin is above VEN(th), the device is ready to deliver output current from the output stage after the power on reset time tPOR. When the supply voltage VS is below the threshold VSUV(th), the internal Power-ON-Reset (POR) function holds the device in reset state. The power on reset time tPOR has to be taken into account under relevant application conditions, i.e. with PWM control from VS. t t 10% tPOR 100% t V EN/DEN IOUT V S V EN(th) V SUV(th) Figure 3 Power on reset timing diagram If the voltage applied at the EN/DEN pin is below VEN(th) for more than tSLEEP the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to IVS(sleep).

5.2 Electrical characteristics

Table 6 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Current consumption, sleep mode IVS(sleep) – – 3 µA VEN/DEN = 0 V TJ = 150°C PRQ-85 Current consumption, active mode (no fault) IVS(active) – 2.5 3.5 mA VEN/DEN = 5.5 V VACC/PWMI = 2.4 V IREF pin left open PRQ-154 (table continues...) TLD1173-1ET Datasheet Datasheet 11 Rev.1.00 2024-10-14

Table 6 (continued) Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Current consumption during fault condition (1-fail-all-OFF) IVS(fault, ERRN) – – 850 µA VEN/DEN = 5.5 V VERRN = 0 V D pin open PRQ-87 VS undervoltage threshold VSUV(th) 3.5 – 4.5 V – PRQ-89 EN/DEN outputs enable threshold VEN(th) 0.6 – 1.8 V – PRQ-159 EN/DEN outputs enable hysteresis VEN(hys) 80 120 – mV 1) PRQ-160 EN/DEN pull-down current IEN/DEN(PD) – – 5 µA VEN/DEN = 3 V PRQ-161 EN/DEN pull-down current IEN/DEN(PD) – – 150 µA VEN/DEN = 18 V PRQ-371 Power on reset delay time tPOR – – 75 µs VS rising edge from 0 V to

8 V to 10% of output

VEN/DEN = 5.5 V VACC/PWMI ≥ 2.4 V PRQ-164 Sleep mode filter time tSLEEP 15 – 45 ms – PRQ-109 1) Not subject to production test, specified by design TLD1173-1ET Datasheet Datasheet 12 Rev.1.00 2024-10-14

6 Power stage

The power stage sinks from the OUT pin an output current IOUT which is a function of the external sense resistor placed at SENSE pin. The maximum output current is limited by the power dissipation Pmax and used cooling areas. OUT SENSE GND Current sink Thermal protection Output current regulation R SENSE IOUT Figure 4 Power stage block diagram

6.1 Output current regulation

The output current regulation block controls the LEDs current by regulating the voltage drop VSENSE(reg) on the external low-side current-sense resistor RSENSE placed between SENSE pin and GND. When the LEDs current is in regulation, the LEDs current value can be calculated by using the following equation: ISENSE = VSENSE reg RSENSE (1) For an operating output current control loop, the power stage dropout voltage (VDR,CS), the VSENSE(reg) voltage, the forward voltage VD_RP of the reverse polarity protection diode (when used) and the minimum supply voltage have to be considered in the LED string design. To grant a proper control of the output current the following equation has to be satisfied: VS ≥ VSENSE reg + VDR, CS + VLED_STRING + VD_RP (2) In case the supply voltage drops below the minimum requested, the LEDs current is no longer properly regulated. Consequently, a lower current is delivered and the voltage across the RSENSE resistor is lower than the expected VSENSE(reg). Note: The R SENSE has to be placed as close as possible to the pin VSENSE to avoid current regulation instability.

6.2 Thermal protection

A thermal protection function is integrated into the device to prevent IC damage under fault conditions described in the datasheet. Fault conditions are considered as "outside" the normal operating range. Protective functions are not designed for continuous operations. The thermal protection function is achieved by temperature monitoring of the power stage. As soon as the junction temperature exceeds the overtemperature threshold TJSD:

• The output current is disabled by turning off the power stage
• The ERRN/DEN pin is pulled low
• The current consumption is below IVS(fault, ERRN) Once the junction temperature falls below TJSD - TJ(hys): TLD1173-1ET Datasheet

Datasheet 13 Rev.1.00 2024-10-14

• The power stage recovers to normal operation
• The ERRN/DEN pin is released

6.3 Electrical characteristics

Table 7 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Leakage currents Output leakage current IOUT(leak) – – 1 µA 1) TJ = 85°C VOUT ≤ 16 V VACC/PWMI = 0 V VEN/DEN = 5.5 V PRQ-116 Output leakage current IOUT(leak) – – 5 µA TJ = 150°C VOUT ≤ 16 V VACC/PWMI = 0 V VEN/DEN = 5.5 V PRQ-118 Sense regulation voltage accuracy SENSE voltage regulation accuracy VSENSE(reg) 384 400 416 mV VACC/PWMI ≥ 2.4 V PRQ-120 SENSE voltage regulation accuracy VSENSE(reg) 95 100 105 mV VACC/PWMI = 0.9 V PRQ-121 SENSE voltage regulation accuracy VSENSE(reg) 14 20 26 mV VACC/PWMI = 0.5 V PRQ-123 Power stage drop out Power stage drop out voltage VDR,CS – – 0.6 V IOUT = 400 mA PRQ-124 Thermal protection thresholds Overtemperature shutdown threshold TJSD 165 175 185 °C 2) PRQ-131 Overtemperature hysteresis TJ(hys) 5 10 15 °C 2) PRQ-132 1) Not subject to production test, specified by design 2) Not subject to production test, specified by design TLD1173-1ET Datasheet Datasheet 14 Rev.1.00 2024-10-14

7 Power shift

The device manages high power dissipation (higher than allowed by the thermal impedance RthJA of the application) by separating the LED current into two current branches:

• One current sink path through an external drop element (power resistor) and the internal power shift
• One current sink path through the internal power stage The current flowing into the power shift path and the one flowing into the power stage path are dynamically adjusted in order to obtain that the sum of IOUT and IPS currents is equal to the regulated ISENSE current. The distribution of the current between the power shift path and the power stage path is defined by the power shift resistor value, the load and the applied battery voltage VS. In order to proper dimension the resistor value the following parameters have to be considered:
• Maximum current IPS intended to flow into the power shift path at maximum battery operative voltage VS(PEAK)
• Forward voltage VLED_STRING of the output LED load and forward voltage VD_RP of the reverse polarity protection diode
• Voltage drop on the internal power shift element (VPS_INT = IPS x RPS_INT(ON))
• Regulated VSENSE voltage The resistor can then be calculated using the following formula: RPS = VS PEAK − VD_RP − VLED_STRING − VPS_INT − VSENSE IPS (3) VS OUT SENSE GND V S(max) R SENSE PS R PS V D_RP V LED_STRING V RPS V SENSE Figure 5 Power shift resistor diagram Note: Please consider that if the R PS is set to 0 Ω all the LED current flows inside the internal power shift path leading to a possible overheating of the device up to the thermal shut-down. TLD1173-1ET Datasheet

Datasheet 15 Rev.1.00 2024-10-14

7.1 Electrical characteristics

Table 8 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Power shift ON resistance RPS_INT(ON) – – 3 Ω 1) IPS = 400 mA PRQ-275 Power shift leakage current IPS(leak) – – 1 µA 1) TJ = 85°C VPS ≤ 16 V VACC/PWMI = 0 V VEN/DEN = 5.5 V PRQ-277 Power shift leakage current IPS(leak) – – 3 µA TJ = 150°C VPS ≤ 16 V VACC/PWMI = 0 V VEN/DEN = 5.5 V PRQ-287 Power shift ratio IPS/ISENSE 0.95 – – – VPS - VSENSE > 1.5 V VACC/PWMI ≥ 0.9 V PRQ-279 SENSE voltage regulation accuracy VSENSE(reg) 384 400 416 mV VACC/PWMI ≥ 2.4 V PRQ-408 SENSE voltage regulation accuracy VSENSE(reg) 95 100 105 mV VACC/PWMI = 0.9 V ISENSE > 20 mA PRQ-410 SENSE voltage regulation accuracy VSENSE(reg) 14 20 28 mV VACC/PWMI = 0.5 V ISENSE > 20 mA PRQ-414 1) Not subject to production test, specified by design TLD1173-1ET Datasheet Datasheet 16 Rev.1.00 2024-10-14

8 PWM control

PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string. The PWM modulation is performed via the ACC/PWMI pin. The power stage and the power shift are disabled if the voltage applied on the ACC/PWMI pin is lower than VPWM(OFF) while they are enabled if the voltage applied on the PWMI/ACC pin is higher than VPWM(ON). In Figure 6 two examples of PWM dimming are shown via the ACC/PWMI input pin: 1. In case a resistor is needed on the ACC/PWMI input pin to apply analog current control (i.e. binning or thermal derating) the PWM signal can be applied using an open drain output from the PWM generator 2. In case the analog current control function is not needed a push-pull output from the PWM generator can be used to apply the PWM modulation ACC/PWMI OUT SENSE PS Power stage Power shift PWM control Open drain PWM generator (i.e. uC, timer) R ACC PWM signal ACC/PWMI OUT SENSE PS Power stage Power shift PWM control Push pull PWM generator (i.e. uC, timer) PWM signal Figure 6 PWM control via ACC/PWMI input pin The PWM signal can be applied via the EN/DEN pin as well to allow PWM modulation from the battery line. Indeed by applying a proper filtering on the VS pin to avoid to trigger the VS undervoltage threshold, the tPOR delay time would be applied only on the first PWM pulse generation after the exit from sleep state, like shown in Figure 9. When applied on the EN/DEN pin the PWM signal has a frequency range fPWM to avoid to turn-off the channel by triggering the tSLEEP filter time. The power stage and the power shift of the channel are enabled if the voltage applied on the EN/DEN pin is higher than VEN(th) while they are disabled if the voltage applied on the EN/DENx pin is lower than VEN(th). TLD1173-1ET Datasheet Datasheet 17 Rev.1.00 2024-10-14

Figure 7 PWM control via EN/DEN input pin When the voltage applied on the ACC/PWMI pin is below VPWM(OFF), the load diagnostic is disabled unless a fault was previously detected. As well, when the voltage applied on the EN/DEN pin is below VDEN(th), the load diagnostic is disabled unless a fault was previously detected. In particular, if a fault is already present when the voltage applied on the ACC/PWMI pin is below VPWM(OFF) or the voltage applied on EN/DEN pin is below VDEN(th) the diagnostic is kept active until the fault condition disappears, after that it is then disabled. The PWM control block implements a slope control of the VSENSE voltage in order to improve EMC performances. The slew rate timings are defined by dV/dtON and dV/dtOFF parameters. V ACC/PWMI t t 20% 80% tON V SENSE 100% tOFF V ACC V PWM(OFF) d V/ d tON d V/ d tOFF Figure 8 PWMI control timing diagram for VACC/PWMI ≥ 2.4 V TLD1173-1ET Datasheet Datasheet 18 Rev.1.00 2024-10-14

t t 20% 80% tON VSENSE 100% tOFF VEN(th) dV/dtON dV/dtOFF tPOR tOFF Device in SLEEP state Device in ACTIVE state 1/f PWM 10% tON dV/dtON dV/dtOFF Figure 9 PWM control on EN/DEN timing diagrams for VACC/PWMI ≥ 2.4 V

8.1 Electrical characteristics

Table 9 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. PWM turn off threshold VPWM(OFF) 0.35 0.4 – V – PRQ-145 PWM turn on threshold VPWM(ON) – – 0.45 V – PRQ-261 PWM frequency range fPWM 100 – – Hz 1) PRQ-146 PWM turn on time tON – – 20 µs 1) VSENSE rising to 80% of regulation VACC/PWMI ≥ 2.4 V PRQ-147 PWM turn off time tOFF – – 20 µs 1) VSENSE falling to 20% of regulation VACC/PWMI falling from ≥

2.4 V to less than

VPWM(OFF) PRQ-148 VSENSE rising slew rate dV/dtON 15 35 50 mV/µs 1) VSENSE rising from 20% to 80% of regulation VACC/PWMI ≥ 2.4 V PRQ-149 VSENSE falling slew rate dV/dtOFF -50 -35 -15 mV/µs 1) VSENSE falling from 80% to 20% of regulation VACC/PWMI falling from ≥

2.4 V to less

than VPWM(OFF) PRQ-150 1) Not subject to production test, specified by design TLD1173-1ET Datasheet Datasheet 19 Rev.1.00 2024-10-14

9 Analog output current control

The analog output current control function adjusts the VSENSE voltage by sensing the applied voltage on the ACC/ PWMI pin VACC/PWMI. As described in Chapter 6 the output current provided by the channel is a direct function of the regulated voltage VSENSE. In this way by adjusting the voltage applied on the ACC/PWMI pin it is possible to control the output current. ISENSE = 0 . 2 × VACC/PWMI − 0 . 08 V RSENSE (4) The relation between the ACC/PWMI voltage VACC/PWMI and the respective regulated voltage VSENSE is shown in the Figure 10. V SENSE(100%) Analog current control enabledOFF ON @ 100% 2.4 V V SENSEx V ACC/PWMI V SENSE(5%)

0.5 VV PWM(OFF)

V SENSE( 25 %) 0.9 V Figure 10 Analog output current control The voltage on ACC/PWMI can be set by applying an accurate external resistor on the ACC/PWMI pin. In case the resistor is placed in another PCB (i.e. binning resistor) it is recommended to add capacitor of 220 nF close to the ACC/ PWMI pin. The ACC/PWMI pin outputs a constant current based on the IREF output current and the ACC current ratio IACC/IIREF. Note: In case the analog output current control function is not needed it is recommended to put 100 k Ω pull-down resistor on the IREF pin to proper bias the ACC/PWMI voltage to avoid wrong VSENSE setting. TLD1173-1ET Datasheet Datasheet 20 Rev.1.00 2024-10-14

1) Analog output current control set via external reference 2) Analog output current control set by IREF current ACC/PWMI R ACC IREF R IREF ACC/PWMI IREF Voltage reference GND 2) Analog output current control not used ( V SENSE = 400 mV typ.) ACC/PWMI IREF R IREF R IREF = 100 K Ω Figure 11 Analog output current control configurations

9.1 Electrical characteristics

Table 10 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. ACC current ratio IACC/IIREF 4.85 5 5.15 – 20 μA ≤ IIREF ≤ 250 μA PRQ-253 TLD1173-1ET Datasheet Datasheet 21 Rev.1.00 2024-10-14

10 Current reference generation

The current reference generation block, outputs an accurate output reference current with low temperature shift. The voltage on the IREF pin is regulated in the VIREF range. It turns out that the reference current can be set by placing an external resistor from IREF pin to GND and can be calculated using the following formula: IIREF = VIREF RIREF (5) Note: The R IREF has to be placed as close as possible to the pin IREF to avoid current regulation instability.

10.1 Electrical characteristics

Table 11 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. IREF regulated voltage VIREF 1.164 1.2 1.236 V – PRQ-268 IREF current range IIREF – – 250 μA – PRQ-269 IREF capacitance CIREF – – 0.22 nF 1) PRQ-273 1) Not subject to production test, specified by design TLD1173-1ET Datasheet Datasheet 22 Rev.1.00 2024-10-14

11 Load diagnostics

Several diagnosis features are integrated:

• Open load detection (OL)
• Short to supply detection (SC)
• Power shift short to supply detection (SC)
• Overtemperature thermal detection (OT) The behavior of the device during overload conditions that lead to an excess of internal heating, up to overtemperature condition, is already described in chapter Thermal protection. An open load condition is detected if the voltage across the power stage VDR = VOUT - VSENSE is below the threshold VDR(OL) for at least a filter time tfault. A short to supply condition is detected if the output voltage drop over the load VS - VOUT is below the threshold VOUT(SC) for at least a filter time tfault. A power shift short to supply condition is detected if the power shift voltage drop VS - VPS is below the threshold VPS(SC) for at least a filter time tfault. If an OL condition is detected on the OUT pin or a SC condition is detected on one of the OUT or PS pins, a pull-down current IOUT(fault) flows inside the OUT pin replacing the configured output current. Note: The I OUT(fault) current is limited by the actual load impedance, e.g. it is reduced to zero with an ideal open load.

11.1 Diagnostics enable

As soon as the voltage applied at the supply pin VS is above VSUV(th) and the voltage applied to the EN/DEN pin is above VDEN(th), the device is ready to detect and report fault conditions via ERRN/DEN pin. There are several possibilities to program the output enable and diagnosis enable via EN/DEN pin, like a resistor divider from VS to GND, a Zener diode from EN/DEN to VS and also a logic control pin (e.g. from a microcontroller output). EN/DEN V DEN(th) V EN(th) VS V SUV(th) OUT Control OUT Diagnosis Control Internal Supply Figure 12 EN/DEN block diagram

11.2 ERRN/DEN pin

The device is able to report a detected failure in its driven load and react to a fault detected by another LED driver in the system if a shared error network is implemented (i.e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open-drain diagnostic output pin ERRN/DEN. All devices sharing a common error network are capable to detect the fault from any of the channels driven by the Basic+ family. TLD1173-1ET Datasheet Datasheet 23 Rev.1.00 2024-10-14

The open-drain ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND when a fault condition is detected for at least a filter time tfault. Therefore, an active low state can be detected at ERRN/DEN pin when VERRN < VERRN(fault) and the relative faulty output channel is switched off. Similarly, when the fault is removed, ERRN/DEN pin is back in high impedance state and the channel reactivation is completed as illustrated in Figure 13. V ERRN(fault) fault no fault ERRN/DEN V ERRN(DEN) OUT Control OUT Diagnosis Control R ERRN(ON) Figure 13 ERRN/DEN pin block diagram To enable the possibility to decouple the VDEN(th) threshold from the VEN(th) threshold to have the device turning on as soon as needed independently from the diagnostic enable threshold, VDEN(th), the DEN functionality is duplicated on the ERRN/DEN pin. The diagnostic reporting on ERRN/DEN pin and "open load" , "short to supply" and the "power shift short to supply" protections are disabled, unless a fault was previously detected, as soon as one of the following condition is verified:

• The voltage on the ERRN/DEN pin is VERRN(fault) < VERRN/DEN ≤ VERRN(DEN)
• The voltage on EN/DEN pin is below VDEN(th) When the ERRN/DEN pin applies a pull-down resistor RERRN(ON) towards GND the VERRN(DEN) threshold is masked to avoid unwanted toggling of the voltages on the ERRN/DEN pin.

11.3 D pin

The D pin is designed for two main purposes:

• To react to error conditions in LED arrays according to the implementation fault management policy, in systems where multiple LED chains are used for a given function as illustrated in Figure 14
• To extend the channel's deactivation delay time of a value tD, adding a small signal capacitor from the D-pin to GND. In this way, an unstable or noisy fault condition may be prevented from switching off all the channels of a given light function (i.e. driven by several ICs sharing the same error network) The functionality of the D-pin is shown in the simplified block diagram illustrated in Figure 15. GND D GND D C D D GND 1) 1-fail-all-ON configuration 2) 1-fail-all-OFF configuration 3) 1-fail-all-OFF configuration with delay time Figure 14 D pin configurations TLD1173-1ET Datasheet

Datasheet 24 Rev.1.00 2024-10-14

V D(th) ERRN = H ERRN = L ID(PD) D C D ID(fault) ERRN = H ERRN = L Figure 15 D pin block diagram In normal operative status (no fault) a pull-down current ID(PD) is sunk from the D-pin to GND. If there is a fault condition (for at least a filter time tfault) in one of the LED channels driven by the IC or in any of the devices sharing the same ERRN error network line, a pull-up current ID(fault) is instead sourced from the D-pin. If a capacitive or open load is applied at this pin (1-fail-all-OFF), its voltage starts rising. When VD(th) is reached at D- pin, all the channels driven by the device are switched off and if other devices share the same ERRN/DEN and D-pins nodes, all the devices turn their outputs off. Alternatively, if the D-pin is tied to GND (1-fail-all-ON), only the channel that has been detected with a fault is safely deactivated. The capacitor value used at the D-pin, CD, sets the delay times tD(set/reset) according to the following equations: tD set = CD × VD tℎ ID fault (6) tD reset = CD × VD CL − VD tℎ − VD ℎys ID PD (7)

11.4 Fault management

With D pin open or connected with a capacitor to GND configuration, it is possible to switch off all the channels which share a common error network, without the need of an auxiliary microcontroller. For more details refer also to the timing diagram. If there is a fault condition at the output or the power shift, the ERRN/DEN pin applies a pull-down resistance RERRN(ON) towards GND and (with proper dimensioning of the external pull-up resistor) reaches a voltage level below VERRN(fault). After tD(set), the voltage VD(th) is reached at D pin. The ERRN/DEN low voltage can also be used as input signal for a microcontroller to perform the desired diagnosis policy. The OL and SC error conditions are not latched: as soon as the fault condition is no longer present, for at least a filter time tfault, ERRN/DEN goes back to high impedance. When its voltage is above VERRN(fault), the D pin voltage starts decreasing and after tD(reset) goes below (VD(th) - VD(th,hys)). TLD1173-1ET Datasheet Datasheet 25 Rev.1.00 2024-10-14

t VOUT t VD(th) VD t VERRN(fault) VERRN/DEN open load occurs open load disappears VDR(OL) + VSENSE tD(reset) tD(set) VD(hys) VD(CL) t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault open load occurs open load disappears tfault tD(set) tfault tD(reset) VD(hys) Figure 16 Open load condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor) t VOUT t VD(th) VD t VERRN(fault) VERRN/DEN short led occurs short led disappears VS - VOUT(SC) tD(reset) tD(set) VD(hys) VD(CL) t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault short led occurs short led disappears tfault tD(set) tfault tD(reset) VD(hys) Figure 17 Output short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor) TLD1173-1ET Datasheet Datasheet 26 Rev.1.00 2024-10-14

t VPS t VD(th) VD t VERRN(fault) VERRN/DEN short led + RPS occurs short led + RPS disappears VS - VPS(SC) tD(reset) tD(set) VD(hys) VD(CL) t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault short led + RPS occurs short led + RPS disappears tfault tD(set) tfault tD(reset) VD(hys) Figure 18 Power shift short to supply condition timing diagram example in 1-fail-all-OFF configuration (D pin open or connected to external capacitor) With D pin connected to GND, it is possible to deactivate only the channel under fault condition, still sharing ERRN pin in a common error network with other devices of Basic+ family. If there is a fault condition at the output or the power shift, the ERRN pin applies a pull-down resistance RERRN(ON) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy. The OL and SC error conditions are not latched: as soon as the fault condition is no longer present (for at least for a filter time tfault) ERRN/DEN goes back to high impedance and the output stage is activated again. t VOUT t VERRN(fault) VERRN/DEN open load occurs open load disappears VDR(OL) + VSENSE t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault open load occurs open load disappears tfault tfault Figure 19 Open load condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND) TLD1173-1ET Datasheet Datasheet 27 Rev.1.00 2024-10-14

t VOUT t VERRN(fault) VERRN/DEN t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault tfault tfault short led occurs short led disappears VS - VOUT(SC) short led occurs short led disappears Figure 20 Output short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND) t VPS t VERRN(fault) VERRN/DEN t VPWM(OFF) VACC/PWMI t IOUT IOUT(fault) tfault tfault tfault tfault tfault VS - VPS(SC) short led + RPS occurs short led + RPS disappears short led + RPS occurs short led + RPS disappears Figure 21 Power shift short to supply condition timing diagram example in 1-fail-all-ON configuration (D pin shorted to GND)

11.5 Electrical characteristics

Table 12 Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. ERRN/DEN pin ERRN fault threshold VERRN(fault) 0.7 – 0.9 V – PRQ-193 (table continues...) TLD1173-1ET Datasheet Datasheet 28 Rev.1.00 2024-10-14

Table 12 (continued) Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. ERRN ON resistance RERRN(ON) – – 350 Ω IERRN/DEN = 2 mA Fault condition VEN/DEN > VDEN(th) PRQ-379 ERRN diagnosis enable threshold VERRN(DEN) 2.1 – 2.3 V – PRQ-255 ERRN pull-down current IERRN_PD – – 2 µA No fault condition VEN/DEN > VDEN(th) PRQ-380 Diagnosis enable DEN diagnosis enable threshold VDEN(th) 2.3 – 2.7 V – PRQ-244 Protections OL detection threshold VDR(OL) 0.2 – 0.4 V VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) PRQ-285 OUT SC detection threshold VOUT(SC) 0.8 – 1.35 V VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) PRQ-286 PS SC detection threshold VPS(SC) 0.8 – 1.35 V VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) PRQ-292 Fault detection current IOUT(fault) – – 650 µA OL or SC fault condition VEN/DEN > VDEN(th) VERRN/DEN < VERRN(fault) PRQ-294 D pin Threshold voltage for function de-activation VD(th) 1.4 1.7 2 V VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) PRQ-299 Threshold hysteresis VD(hys) 70 – – mV VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) Not subject to production test, specified by design PRQ-300 Fault pull-up current ID(fault) 20 35 50 µA OL or SC fault condition VEN/DEN > VDEN(th) VERRN/DEN < VERRN(fault) VD = 2 V PRQ-301 (table continues...) TLD1173-1ET Datasheet Datasheet 29 Rev.1.00 2024-10-14

Table 12 (continued) Electrical characteristics VS = VS(func), TJ = TJ(func), all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Pull-down current ID(PD) 40 60 95 µA No fault conditions VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) VD = 1.4 V PRQ-302 Internal clamp voltage VD(CL) 2 – 3 V OL or SC fault condition VEN/DEN > VDEN(th) VERRN/DEN < VERRN(fault) D-pin open PRQ-303 Timings Fault to ERRN delay tfault 40 – 120 µs VEN/DEN > VDEN(th) VERRN/DEN > VERRN(DEN) PRQ-304 TLD1173-1ET Datasheet Datasheet 30 Rev.1.00 2024-10-14

Note: The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

12.1 Application diagram

Note: This figure is a simplified example of an application circuit. The function must be verified in the application. Supply protection TLD1173-1ET VS EN/DEN ACC/PWMI OUT SENSE GND R1R2 CVS VS RERRNERRN/DEN RSENSE RNTC IREF RIREF D PS RPS DRP TLD1173-1ET VS EN/DEN ACC/PWMI OUT SENSE GND ERRN/DEN RSENSE IREF D PS RPS CVS Figure 22 Application diagram example in a shared network with "one fail all off" fault management and central thermal derating TLD1173-1ET Datasheet Datasheet 31 Rev.1.00 2024-10-14

Figure 23 PG-TFDSO-16 package outline png TLD1173-1ET Datasheet Datasheet 32 Rev.1.00 2024-10-14

Revision history

Rev. 1.00 2024-10-14 • Initial document release TLD1173-1ET Datasheet Datasheet 33 Rev.1.00 2024-10-14

All referenced product or service names and trademarks are the property of their respective owners. Edition 2024-10-14 Published by Infineon Technologies AG

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