TLC876CPW

TLC876M_07 TI | Alldatasheet

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TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

/C006810-Bit Resolution 20 MSPS Sampling Analog-to-Digital Converter (ADC) /C0068Power Dissipation. . . 107 mW Typ /C00685-V Single Supply Operation /C0068Differential Nonlinearity . . .±0.5 LSB Typ /C0068No Missing Codes /C0068Power Down (Standby) Mode /C0068Three State Outputs /C0068Digital I/Os Compatible With 5-V or 3.3-V Logic /C0068Adjustable Reference Input /C0068Small Outline Package (SOIC), Super Small Outline Package (SSOP), or Thin Small Outline Package (TSOP) /C0068Pin Compatible With the Analog Devices AD876

applications

/C0068Communications /C0068Multimedia /C0068Digital Video Systems /C0068High-Speed DSP Front-End...T MS320C6x

description

The TLC876 is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (ADC). The speed, resolution, and single-supply operation are suited for applications in video, multimedia, imaging, high-speed acquisition, and commu- nications. The low-power and single-supply operation satisfy requirements for high-speed portable applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Force and sense connections to the reference inputs provide a more accurate internal reference voltage to the reference resistor string. A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or 3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output data is straight binary coding. A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the fifth stages operate on the four preceding samples. The TLC876C is characterized for operation from 0°C to 70°C, the TLC876I is characterized for operation from –40°C to 85°C, and the TLC876M is characterized for operation over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. AGND DRV DD DRGND DGND AV DD AIN CML REFBS REFBF NC REFTF REFTS DGND AGND DV DD STBY OE CLK (TOP VIEW) NC – No internal connection DB, DW, OR PW PACKAGE PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2000, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000

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(DB) SMALL OUTLINE (DW) TSSOP (PW) 0°C to 70°C TLC876CDB TLC876CDW TLC876CPW –40°C to 85°C TLC876IDB TLC876IDW TLC876IPW –55°C to 125°C — TLC876MDW — functional block diagram ADC DAC ADC DAC ADC DAC ADC Correction Logic Output Buffers SHA † SHA † GAIN SHA † GAIN SHA † GAIN AIN (MSB) D9 (LSB) D0 † Sample and hold amplifier 22 2 2 ADC DAC SHA † GAIN

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 equivalent input and output circuits DV DD DGND DRV DD DRGND DV DD DRV DD DGND DRGND AV DD AGND AV DD AV SS AV DD AGND REFTF REFTS Internal Reference Voltage AV DD AGND AV DD AV SS REFBF REFBS Internal Reference Voltage D0–D9 OUTPUT CIRCUIT ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT REFERENCE INPUT CIRCUIT D0–D9 CLK AIN 0.5 pF typ

30 W typ

0.3 pF

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000

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NAME NO. I/O DESCRIPTION AGND 1, 19 Analog ground AIN 27 I Analog input AV DD 28 5-V analog supply CLK 15 I Clock input CML 26 O Bypass for an internal bias point. Typically a 0.1 mF capacitor minimum is connected from this terminal to ground. DGND 14, 20 Digital ground DV DD 18 5-V digital supply DRV DD 2 3.3-V/5-V digital supply. Supply for digital input and output buffers. DRGND 13 3.3-V/5-V digital ground. Ground for digital input and output buffers. D0–D9 3–12 O Digital data out. D0:LSB, D9:MSB OE 16 I Output enable. When OE = low or NC, the device is in normal operating mode. When OE = high, D0–D9 are high impedance. REFBF 24 I Reference bottom force REFBS 25 I Reference bottom sense REFTF 22 I Reference top force REFTS 21 I Reference top sense STBY 17 I Standby enable. When STBY = low or NC, the device is in normal operating mode. When STBY = high, the device is in standby mode. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Reference voltage input range to AGND, VI(REFTF), VI(REFBF), VI(REFBS), † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C ‡ TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING DB 1353 mW 10.82 mW/°C 866 mW 703 mW — DW 1598 mW 12.78 mW/ °C 1023 mW 831 mW 320 mW PW 1207 mW 9.65 mW/°C 772 mW 627 mW — ‡ This is the inverse of the traditional junction-to-ambient thermal resistance (RQ JA). Thermal resistance is not production tested, and values given are for informational purposes only.

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions analog and reference inputs MIN NOM MAX UNIT Reference input voltage (top), VI(REFT) VI(REFB) + 1 3.6 4.5 V Reference input voltage (bottom), VI(REFB) 0 1.6 VI(REFT) – 1 V Analog input voltage, VI(AIN) 1 2 Vpp power supply MIN NOM MAX UNIT AV DD † 4.5 5.25 Supply voltage DV DD † 4.5 5.25 V DRV DD 3 5.25 † The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications. digital inputs MIN NOM MAX UNIT DRV DD = 3 V 2.4 High-level input voltage, VIH DRV DD = 5 V 4 V DRV DD = 5.25 V 4.2 DRV DD = 3 V 0.6 Low-level input voltage, VIL DRV DD = 5 V 1 V DRV DD = 5.25 V 1.05 Clock period, tc (see Figure 1) 50 ns Pulse duration, clock high, tw(CLKH) 23 25 ns Pulse duration, clock low, tw(CLKL) 23 25 ns TLC876C 0 70 Operating free-air temperature, TA TLC876I –40 85 °C TLC876M –55 125

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000

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electrical characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V, fCLK = 20 MSPS (unless otherwise noted) power supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AV DD † 17 25 mA IDD Operating supply currentDV DD † 2.7 5 mA DRV DD 25 100 mA PD Power dissipation 107 150 mW PD(STBY) Standbypower STBY = High CLK running 45 85 mWPD(STBY) Standby pow er STBY = High CLK inhibited at VDD or 0 V 15 35 mW † The voltage difference between AVDD and DVDD terminals cannot exceed 0.5 V to maintain performance specifications. digital logic inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IIH High-level input current, STBY, OE DV DD = 5 V 1.9 mA IIH High-level input current, all other inputs DV DD = 5 V 10 mA IIL Low-level input current DV DD = 5V –50 50 mA IIL(CLK) Low-level input current, CLK DV DD = 5V –10 10 mA C i Input capacitance 5 pF logic outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH =5 0mA DRV DD = 3 V 2.4 VOH High-level output voltage IOH = 50 mA DRV DD = 5 V 3.8 V IOH = 0.5 mA DRV DD = 5 V 2.4 IOL =5 0mA DRV DD = 3.6 V 0.7 VOL Low-level output voltage IOL = 50 mA DRV DD = 5.25 V 1.05 V IOL = 0.6 mA DRV DD = 5.25 V 0.4 C o Output capacitance 5 pF IOZ High-impedance-state output current –10 10 mA

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics at AVDD = DVDD = 5 V, DRVDD = 3.3 V, VI(REFT) = 3.6 V, VI(REFB) = 1.6 V, fCLK = 20 MSPS (unless otherwise noted) dc accuracy PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Integral nonlinearity (INL) ± 1.5 LSB Differential nonlinearity (DNL) (see Note 1) ± 0.5 <± 1 LSB Offset error –0.4 %FSR Gain error 0.2 %FSR NOTE 1: A differential nonlinearity error of less than ±1 LSB ensures no missing codes. analog input PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C i Input capacitance 5 pF reference input PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R ref Reference input resistance 350 500 W Iref Reference input current 4 mA Reference top offset voltage 35 mV Reference bottom offset voltage 35 mV dynamic performance† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT All suffixes fI = 1 MHz 8.5 Eff ti b f bit (ENOB) All suffixes fI = 3.58 MHz, TA = 25°C 8 8.5 BitEffective number of bits (ENOB) C and I suffixesfI = 3.58 MHz, 8 8.5 Bits M suffix I , TA = Full Range 7.5 All suffixes fI = 10 MHz 8.1 All suffixes fI = 1 MHz 53 Signal-to-total harmonic distortion+noise All suffixes fI = 3.58 MHz, TA = 25°C 50 53 dBSignal to total harmonic distortion+noise (S/(THD+N)) C and I suffixesfI = 3.58 MHz, 50 53 dB M suffix I , TA = Full Range 47 All suffixes fI = 10 MHz 51 fI = 1 MHz –63 Total harmonic distortion (THD) fI = 3.58 MHz –62 –56 dB fI = 10 MHz –61 Spurious free dynamic range fI = 3.58 MHz –64 dB BW Analog input full-power bandwidth 200 MHz Differential phase 0.5 degrees Differential gain 1% † The voltage difference between AVDD and DVDD cannot exceed 0.5 V to maintain performance specifications. At input clock rise times less than 20 ns, the offset full-scale error increases approximately by a factor of (20/tr)0.5 where tr equals the actual rise time in nanoseconds.

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NOTE 2: The conversion rate can be a minimum of 10 kHz without degradation in specified performance. Figure 1. Timing Diagram Figure 2. Output Enable to Data Output Timing Diagram Figure 3. Standby Timing

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Figure 9. Differential Nonlinearity

TLC876M, TLC876I, TLC876C 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS SLAS140E – JULY 1997 – REVISED OCTOBER 2000

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definitions of specifications and terminology integral nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. This parameter is sometimes referred to as linearity error. differential nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than /C00341 LSB ensures no missing codes. This parameter is sometimes referred to as differential error. offset error The first transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual first code transition from that point. gain error The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage applied to the REFBF terminal). The last transition should occur for an analog value 1 1/2 LSB below nominal positive full scale (the voltage applied to the REFTF terminal). Gain error is the deviation of the actual difference between the first and last code transitions from the ideal difference between the first and last code transitions. pipeline delay (latency) The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle. reference top/bottom offset Resistance between the reference input and comparator input tap points causes offset errors. These errors can be nulled out by using the force-sense connection as shown in the driving the reference terminals section. driving the analog input Figure 12 shows an equivalent input circuit of the TLC876 sample-and-hold amplifier and it represents an excellent first order approximation. The total equivalent capacitance, C E, is typically less than 5 pF and the input source must be able to charge or discharge this capacitance to 10-bit accuracy in the sample period of one half of a clock cycle. When the switch S1 closes, the input source must charge or discharge the capacitor C E from the voltage already stored on CE (the previously captured sample) to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the switch resistance RSW (50 W ) of S1 and quickly settle (within 1/2 CLK period), and, therefore, the source is driving a low input impedance. However, when the source voltage equals the value previously stored on C E, the hold capacitor requires no input current to maintain the charge and the equivalent input impedance is extremely high. Adding series resistance between the output of the source and the AIN terminal reduces the drive requirements placed on the source, as shown in Figure 13. To maintain the frequency performance outlined in the specifications, the resistor should be limited to 200 W minus the source resistance or less. The maximum source resistance, R S, for 10-bit, 1/2 LSB accuracy is given by equation 1.

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the external input circuit in Figure 14. the value must be sufficient for the application. as 1 V for a 2 V peak-to-peak input signal swing. Figure 15. Bias Current and Offset input requirements of the TLC876. Figure 16 shows an amplifier in an inverting mode with ac signal gain of –1. where REFBF = 1.6 V, the dc output level is 2.6 V which is approximately equal to (V(REFTF) – V(REFBF)/2.

0 V dc –

are wide bandwidth single supply op-amps. Figure 16. Bipolar Level Shift

500 W C (Equivalent)

10 W 5 W 5 W 5 W

Figure 17. TLC876 Equivalent Reference Structure

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voltage is 2 Vpp. The full-scale input span is given by equation 3. reference must provide approximately 4 mA for a 2-V drop across the internal resistor array. this voltage without degrading the typical performance.

2 V Span

1 V Span

Figure 18. TLC876 Reference Ranges impedance changes at the reference inputs. recover from the transients and settle to the desired level of accuracy prior to the rising edges of CLK.

140 W (± 1%)

250 W (± 1%)

Figure 19. Low Cost Reference Circuit power supply rejection and reduced accuracy due to the variability of the internal and external resistors. maintaining stability. The operational amplifiers are connected as voltage followers.

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Figure 20. Kelvin Connection Reference Using an Operational Amplifier Figure 21. Kelvin Connection Reference Using an Operational Amplifier

should be connected as close to reference terminals as possible.

4 V VN1

4 V VN2

Figure 22. Recommended Bypassing for the Reference fall times to support 20 MSPS operation. The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency. Figure 8 illustrates this tradeoff between clock rates and a reduction in power consumption. Each of the digital control inputs, OE and STBY, has an input buffer powered from the DRVDD supply terminal. DRV DD can be set to 3.3 V, lowering the nominal input threshold of all digital inputs to (3.3 V)/2 = 1.65 V, typically. V(REFTS) = 4 V and V(REFBS) = 2 V. of the TLC876 drops significantly (see electrical characteristics table).

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Table 1. Output Data Format

4 V 0 1 1 1 1 1 1 1 1 1 1

3 V 0 1 0 0 0 0 0 0 0 0 0

2 V 0 0 0 0 0 0 0 0 0 0 0

critical analog circuitry. The system design should minimize the analog lead-in to reduce potential noise pickup. drivers below the specified 20 pF level. data sheets for compatibility with the TLC876 digital specifications.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-9954001NXD ACTIVE SOIC DW 28 1 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC876CDB OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876CDBLE OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876CDBR OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876CDW OBSOLETE SOIC DW 28 TBD Call TI Call TI TLC876CDWR OBSOLETE SOIC DW 28 TBD Call TI Call TI TLC876CPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI TLC876CPWR OBSOLETE TSSOP PW 28 TBD Call TI Call TI TLC876IDB OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876IDBLE OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876IDBR OBSOLETE SSOP DB 28 TBD Call TI Call TI TLC876IDW OBSOLETE SOIC DW 28 TBD Call TI Call TI TLC876IDWR OBSOLETE SOIC DW 28 TBD Call TI Call TI TLC876IPW OBSOLETE TSSOP PW 28 TBD Call TI Call TI TLC876IPWLE OBSOLETE TSSOP PW 28 TBD Call TI Call TI TLC876IPWR OBSOLETE TSSOP PW 28 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 19-Jan-2007 Addendum-Page 1

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