TLC8044 TI1 | Alldatasheet
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Color or Gray Scale Operation /C0068Signals Processed in the Digital Domain /C0068Differential RGB Input Multiplexer /C0068Three 8-bit DACs for CCD Offset Level Shifting With Bipolar Correction Range /C0068Two Sampling Modes: – DAC Referenced – Correlated Double Sampling (CDS) /C006812-Bit ADC with 6 MSPS Operation /C0068Digital dc Restoration /C0068Pixel-By-Pixel Offset and Shading (Gain) Compensation /C0068Global Gain Adjust for Each Color (Channel) /C0068Compatible with 600 dpi CCD Image Sensors /C0068Global Offset Adjust for Each Color (Channel) /C0068Output Word Length Programmable to 8, 10, 12, or 16 Bits /C0068Programmable Threshold Detector for Each Color (Channel) /C0068Dual Internal Default Registers for Even/Odd Pixel Offset Correction /C006868-Terminal PLCC Package
applications
/C0068Handy Scanners /C0068Flatbed Scanners
description
The TLC8044 is a 12-bit analog-to-digital interface subsystem for charge-coupled device (CCD) image sensors and scanners. An input multiplexer allows color operation with a single on-chip 12-bit ADC. The TLC8044 uses DSP circuits to correct for nonideal CCD image sensor and scanning system characteristics. Cost effective gray scale operation is obtained using a single multiplexer input. The TLC8044 three-channel input multiplexer and sampling function has two basic modes of operation: normal sampling and correlated double sampling. The internal sample and hold allows all three channels to be sampled simultaneously in color operation. Three DACs (8 bits + sign) are provided to allow bipolar adjustment of the dc level of the signal at the ADC input. Digital dc restoration is provided following the ADC. Variations in offset and luminance across a scan are dynamically corrected on a pixel-by-pixel basis, using calibration data provided by an external data store. Provisions are made for global adjustments of gain, contrast and color balance, and offset for brightness. The output word length can be programmed to 8, 10, 12, or 16 bits, and a programmable threshold detector is provided for use during calibration and OCR applications. The TLC8044 is characterized for operation from 0°C to 70°C. AVAILABLE OPTIONS PACKAGE TA CHIP CARRIER (FN) 0°C to 70°C TLC8044FN PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997
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(TOP VIEW) OP8 OP9 87 6 5493 OP2 OP3 OP4 OP5 OP6 OP7 POC2 POC1 POC0 RESET POC9 POC8 POC7 POC6 POC5 POC4 POC3 16 86 72 35 36 37 38 39 66 65 27POC11 POC10 OP10 OP11 64 63 62 61 4041 42 43 RT RB RU RL OP12 OP13 OP14 OP15 OP0 OP1 DV DD2
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 POST OFFICE BOX 655303 DALLAS, TEXAS 75265• 3 functional block diagram 12- Bit ADC REF 12 DC Restore Pixel Offset Adjust Global Offset Adjust 3:1 MUX Reg R Reg G Reg B Global Gain Adjust 1616 Serial Interface 8-Bit + Sign DACB 8-Bit + Sign DACR 8-Bit + Sign DACG SDI SCK SEN RINP RINN GINP GINN MCLK Video Sample/MUX Timing Control 3:1 MUX Reg Re Reg Ge Reg Be 3:1 MUX Reg Ro Reg Go Reg Bo 3:1 MUX Reg R Reg G Reg B 3:1 MUX Reg R Reg G Reg B 3:1 MUX Reg R Reg G Reg B 2:1 MUX Pixel Shading AdjustMUX MUX Output Word Length Select Threshold Detect 16 16 VSMP BINP BINN DETOP ORNG OE OP CC ONE POC PSC CDS RU RT RB RL DAC
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997
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NAME NO. TYPE I/O DESCRIPTION AGND 47 Analog I Analog ground (0 V) AV DD 48 Analog Positive analog supply (5 V) BINN 45 Analog I Negative blue channel input video BINP 46 Analog I Positive blue channel input video CC1,0 10, 11 Digital O Color code outputs. CC0 and CC1 indicate which channel the current output sample was taken DAC 44 Analog O Buffered midpoint of ADC reference string. DAC is used internally to set DAC reference voltages. DETOP 13 Digital O Threshold detector output (active high). DETOP indicates that the current output pixel has exceeded the internally programmed threshold for that channel. DGND 14 Digital I Digital ground (0 V) DV DD 1,2 60, 1 Digital I Positive digital supply (5 V) GINN 49 Analog I Negative green channel input video GINP 50 Analog I Positive green channel input video MCLK 55 Digital I Master clock. MCLK is applied at either six times or twice the input pixel rate for color and monochrome operation, respectively. MCLK is divided by two internally to define the ADC sample rate and to provide the clock source for the DSP section. OE 53 Digital I Output 3-state control. Outputs are enabled when OE = 0. ONE 59 Digital I Odd not even. ONE defines the even and odd pixels when the internal pixel offset correction registers are in use (even = 0, odd = 1). OP15–OP0 61-68, 2-9 Digital O Digital 16-bit output (3-state). In 8-, 10-, and 12-bit output modes, OP15 is used to indicate that the output pixel is negative; i.e., OP15 can be used as an under range indicator. OP15 is active high when indicating under range. ORNG 12 Digital O Over range signal (active high). In 8-, 10-, and 12-bit output modes, this signal indicates that the current output pixel has exceeded the maximum achievable for the output word length in use. POC11–POC0 27-38 Digital I Pixel offset coefficient input. The POC11–POC0 12-bit word is applied at the multiplexed pixel rate (i.e., three samples per pixel period in color mode) to correct offset errors in a pixel-by-pixel fashion. PSC11–PSC0 15-26 Digital I Pixel shading coefficient input. The PSC11–PSC0 12-bit quantity is applied at the multiplexed pixel rate (i.e., three samples per pixel period in color mode) to correct shading effects in a pixel-by-pixel fashion. RESET 39 Digital I Reset input (active high). RESET forces a reset of all internal registers in the TLC8044. RINN 51 Analog I Negative red channel input video RINP 52 Analog I Positive red channel input video RU, RT, RB, RL 42, 40, 41, 43 Analog I ADC reference terminals. The voltage applied between RT (full scale) and RB (zero level). define the ADC reference range. RU and RL, upper and lower resistor terminals, are used to derive optimum reference voltages from an external 5-V reference. SCK 57 Digital I Serial clock. Serial interface clock signal. SDI 58 Digital I Serial data in. Serial interface input data signal. SEN 56 Digital I Serial enable VSMP 54 Digital I Video sample synchronization pulse. VSMP applied synchronously with MCLK specifies the point in time that the input is sampled. The timing of internal multiplexing between the R, G, and B channels is derived from this signal.
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltages applied to DVDD 1 and DVDD 2 are measured with respect to the DGND terminal. AVDD is measured with respect to the AGND terminal. For the following specifications, unless otherwise noted, AGND and DGND are tied togather (and represent 0 volts) and are referred to simply as GND. When the voltages applied to DVDD 1, DVDD 2, and AVDD are equal, they are referred to simply as VDD , unless otherwise noted. recommended operating conditions total device MIN NOM MAX UNIT Supply voltage, VCC 4.75 5.25 V digital inputs MIN NOM MAX UNIT High-level input voltage, VIH 0.9 VDD V Low-level input voltage, VIL 0.1 VDD V input multiplexer TEST CONDITIONS MIN NOM MAX UNIT Setup time, input video before MCLK↑, tsu(V) 10 ns Hold time, input video after MCLK↑, th(V) 25 ns Setup time, reset video before MCLK↑, tsu(R) CDS mode only 10 ns Hold time, reset video after MCLK↑, th(R) CDS mode only 25 ns serial interface MIN NOM MAX UNIT Cycle time, MCLK, tcyc1 83.3 ns Pulse duration, MCLK high, tw1(MCLKH) 37.5 ns Pulse duration, MCLK low, tw2(MCLKL) 37.5 ns Setup time, VSMP↑ to MCLK↑,tsu(D) 10 ns Hold time, MCLK↑ to VSMP↓, th(D) 10 ns Setup time, POC/PCS to MCLK↓, tsu(P) 10 ns Hold time, MCLK↓ to POC/PCS, th(P) 30 ns Cycle time, SCK, tcyc2 83.3 ns Pulse duration, SCK high, tw3(SCKH) 37.5 ns Pulse duration, SCK low, tw4(SCKL) 37.5 ns Setup time, SDI to MCLK↑, tsu(S) 10 ns Hold time, MCLK↑ to SDI change, th(S) 10 ns Setup time, SCK↑ to SEN↑, tsu(SCE) 20 ns Setup time, SEN↓ to SCK↑, tsu(SEC) 20 ns Pulse duration, SEN high, tw(SEN) 50 ns
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997
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electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted) total device PARAMETER MIN TYP MAX UNIT ICC Supply current, active 80 130 mA ICC Supply current, standby 8 10 mA digital inputs PARAMETER MIN TYP MAX UNIT IIH High-level input current 1 µA IIL Low-level input current 1 µA C i Input capacitance 10 pF digital outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = –1 mA VDD - 0.75 V VOL Low-level output voltage IOL = 1 mA 0.75 V IOZ High-impedance output current 1 µA input multiplexer PARAMETER MIN TYP MAX UNIT Channel-to-channel gain matching 0.5% 5% VICR Common mode input voltage 0.5 4.5 V reference string PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Z Impedance, RT to RB 595 850 1105 Ω Z Impedance, RU to RL 1190 1700 2210 Ω Vref(RT) Reference voltage, top VI(RU) = 5 V,VI(RL) = 0 V 3.7125 3.75 3.7875 V Vref(RB) Reference voltage, bottom VI(RU) = 5 V,VI(RL) = 0 V 1.2375 1.25 1.2625 V Vref(DAC) DAC reference voltage VI(RU) = 5 V,VI(RL) = 0 V 2.475 2.5 2.525 V 8-bit DACs PARAMETER MIN TYP MAX UNIT Resolution 8 Bits Zero-scale voltage 0 10 mV Full-scale voltage Vref(DAC) -10 Vref(DAC) +10 mV Differential nonlinearity (DNL) 0.1 /C01161 LSB Integral nonlinearity (INL) 0.4 1 LSB
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted) (continued) 12-bit ADC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bits Sampling rate 6 MSPS Full-scale transition error voltage at xINP (see Note 2) Single-ended mode, VI(xINN) = 2.5 V, DAC code = 000H –100 100 mV Zero-scale transition error voltage at xINP (see Note 3) Single-ended mode, VI(xINN) = 2.5 V, DAC code = 000H –100 100 mV Full-scale transition error voltage, VI(xINP) – VI(xINN) (see Note 2) Differential mode, DAC code = 000H –25 25 mV Zero-scale transition error voltage, VI(xINP) – VI(xINN) (see Note 3) Differential mode, DAC code = 000H –25 25 mV Differential nonlinearity (DNL) (see Note 4) 1.5 LSB Maximum number of missing codes 0 8 CODES Integral nonlinearity (INL) (see Note 5) ±2 ±5 LSB NOTES: 2. The full-scale transition at xINP is the difference between the signal input voltage that causes the 4094 to 4095 transition and the measured reference voltage Vref(RT). 3. The zero-scale transition at xINP is the difference between the signal input voltage that causes the 0 to 1 transition and the reference voltage Vref(RB). 4. Differential nonlinearity (DNL) is the difference between the measured value between any two adjacent codes and the ideal 1 LSB value. 5. Integral nonlinearity (INL) is the maximum deviation of the output from the ideal straight line between zero and the full-scale value. switching characteristics PARAMETER MIN TYP MAX UNIT tpd(D) Propagation delay time, MCLK↓ to output valid 50 75 ns ten(PZE) Enable time, output, OE↓ to data valid 70 75 ns tdis(PEZ) Disable time, output, OE↑ to high impedance 70 25 ns
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Figure 1. Detailed Video Input Timing – Color Mode Figure 2. Detailed Video Input Timing – Monochrome Mode
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Figure 5. Detailed Digital Timing – Serial Interface Figure 6. Differential Linearity With Code Figure 7. Integral Linearity With Code
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION general CCD system operation CCD image sensor array output summary Figure 8 shows a simplified CCD image sensor linear array system with typical CCD array inputs and outputs. The inputs for the shift gate (SH), reset, and two-phase clock drive the array. An electronic charge proportional to the light input is generated by a photo diode for each pixel of the array. The charge for each pixel is transferred in parallel into the analog CCD shift register using the shift gate input and then shifted out serially using a two-phase clock. At the CCD output (OS terminal), the array converts the charge for each pixel into a voltage using a capacitor and source follower MOS transistor. The charge on this capacitor is reset for each pixel by the reset pulse input. A typical output signal then includes a reset period, a dark period, and a period containing video output for each pixel, as shown in Figure 9. This signal sits on a varying dc offset of typically 5 V and is negative going for an increase in video output. An output (DOS terminal) also provides only the dc level from the CCD array.
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Figure 8. System Diagram
Figure 9. A Typical Charge-Coupled Display (CCD) Output Signal
- The video output waveform first has to be removed from the varying dc level on which it sits and shifted in
level to be compatible with an interface device running from a single 5-V supply rail.
- Gain has to be applied to bring the signal up to the full-scale range of the analog-to-digital converter (ADC)
corrections are needed on a pixel-by-pixel basis.
- Dynamic gain adjustment is needed to compensate for the fall off in output from the center to the ends of
compensate for the pixel-by-pixel variation in black dc levels obtained from different CCD array elements.
- DC restoration may optionally be required. Global adjustments of gain and offset across a whole scan are
respectively used to correct color balance and contrast and to change brightness.
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Figure 10. Scanner System Relative CCD Pixel Output TLC8044 and that the offset can be adjusted out by the TLC8044 internal DACs. gain factor (G) over this 1/3 to 3 range. of a single fast 12-bit ADC and DSP channel. with respect to the input reference levels. The DACs are updated through the serial interface.
amplifier with differential outputs is placed between the CCD image sensor and the TLC8044. synchronization between R, G, and B inputs is achieved through the serial interface. hex) and -2.5 V corresponding to zero scale (output code 000 hex). be capacitively decoupled externally. and code required in each case. the single-ended mode, resulting in the required DAC values shown in Table 1. Table 1. Single-Ended Mode Input Voltage Ranges Table 2. Differential Mode Input Voltage Ranges
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997
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analog-to-digital converter (continued) The examples in Tables 1 and 2 assume that the ADC reference terminals RT and RB are set to 3.75 V and 1.25 V, respectively. The signals shown in the tables cover the full-scale range of the ADC. In practice, a reduced range is used to allow some headroom, accomodating a wider range of input offset voltages. The ADC output code can be inverted under control of the serial interface. When not in use, the ADC can also be put into standby mode through the serial interface to reduce system power consumption. sample modes Two input sampling modes are provided, normal and correlated double sampling (CDS). Sampling mode selection is made through the serial interface. All video input timing and sampling is performed relative to the rising edge of the MCLK clock input signal. MCLK is applied to twice the required ADC conversion rate. Synchronization of sampling and channel multiplexing to the incoming video signals is performed by the VSMP input synchronization pulse. Table 3 is a summary of the device operating modes. normal sampling mode Figure 11(a) and Figure 11(b) show the timing of signals in normal sampling mode for both color and monochrome operation. In color operation, all three input channels are sampled at the same instant on the first rising edge of MCLK after the VSMP pulse. An internal timing circuit then controls the multiplexing of the three channels to the ADC input in the R,G,B sequence. In this mode, VSMP is applied at the input pixel rate, and ADC conversions are performed at three times the input pixel rate. For monochrome (single channel) operation, VSMP is again applied at the input pixel rate, however, for monochrome, the ADC is supplied with a continuous stream of samples from a single input channel. Input channel selection in this mode is achieved through the serial interface. In both color and monochrome operation, a simple external delay circuit can be used to align the video data with the sampling instant, provided that the CCD clocks are generated from MCLK. Detailed timings for both cases are shown in Figures 3 and 4.
Table 3. Mode Summary
1 Color Yes 2 MSPS
2 Monochrome Yes 2 MSPS
3 Fast
4 Max speed
† Only indicates relevant register bits.
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Figure 11. Normal Mode Input Timing Figure 12. CDS Mode Input Timing
that exists at both the reset level and the video level. Figure 13(b) shows relative timing. Figure 13. Samplified Correlated Double Sampling diagram with all four CDS timing options.
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correlated double sampling mode (continued) To perform CDS input sampling, the device should be set up in single-ended mode with the differential inputs of each channel (xINP, xINN) connected together to the video input signal. For positive going input signals, i.e., white signal level greater than the reset level, the offset DACs should be set to the maximum negative value (DAC code 1FF hex). This configuration sets the zero signal level (video input equal to the reset level) at the ADC zero-scale code transition. Increasing the DAC code towards zero moves the zero signal level up from the ADC zero-scale code transition. For negative-going input signals, i.e., white signal level less than the reset level, the DACs should be set to the maximum positive value (DAC code 0FF hex). This configuration sets the zero signal level at the ADC full-scale code transition. The polarity of the ADC output signal can be inverted under control of the serial interface data. The multiplexing shown in Figure 12 refers to color operation, however the same overall timing scheme applies to monochrome CDS operation, in that a single input sample is applied to the ADC per VSMP period. Thus the maximum sampling rate in monochrome CDS mode is limited to one third of the maximum rate achievable in normal monochrome sampling mode. digital image processing The digital image processing functions following the ADC as shown in the functional block diagram include the following:
- DC restore: This allows fine adjustment of the dc video level at the ADC output with adjustment values being programmed through the serial interface.
- Pixel-by-pixel offset compensation: This uses offset coefficients that are either externally supplied at the multiplexed channel rate or supplied from internal default registers whose values are programmed through the serial interface.
- Compensation for pixel-by-pixel shading curve nonuniformity and photo response nonuniformity within the sensor: Coefficients are externally supplied at the multiplexed channel rate. Default registers are provided for use during calibration.
- Global offset adjust: Offset adjust over the whole scan for each channel to give brightness control. Values are programmed through the serial interface.
- Global gain adjust: Independent gain adjust over the whole scan for each channel to give contrast and color balance control. Gain values are programmed through the serial interface.
- Programmable output word length selection: The output word length can be programmed to 8, 10, 12, or 16 bits through the serial interface.
- Programmable threshold detector with independent thresholds for each channel. Global adjustments are implemented after the pixel-by-pixel compensations allowing calibrations and modifications in operational use without having to recalibrate the pixel-by-pixel factors. DC restore The dc restore block is used for fine adjustment of the dc signal level at the ADC output by adding a value stored in an internal register. Separate level adjust registers are provided for each channel (color) with multiplexing between channels controlled internally. The level adjust registers are programmed through the serial interface as 12-bit 2s complement numbers with a range of ±0.5 of the ADC full scale, allowing 1-bit resolution in adjustment of the ADC output. The dc adjustment registers are reset to zero.
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION pixel offset compensation The output of the dc restore circuit is passed to an adder which performs pixel-by-pixel offset compensation. Compensation values can either be supplied externally at the multiplexed pixel rate, allowing different correction values for each pixel in the array, or supplied from internal default values programmed through the serial bus. Selection between the two sources is controlled through the serial bus. Two sets of internal default registers are provided to allow correction values to be stored internally for use on even and odd pixels with selection between the two sets under control of the ONE terminal (ONE low for even registers, ONE high for odd registers). This feature allows correction of differing dc offsets output on even and odd pixels, which occur in some CCD sensors, using internally stored data. Pixel offset correction values are input or stored as 12-bit 2s complement numbers. Programmable internal scaling is provided which allows the offset correction factors to cover ±0.5, ±0.25, ±0.125, or ±0.0625 of the ADC full-scale range. The internal pixel correction registers are reset to zero. pixel shading compensation This stage is implemented as a digital multiplier which corrects for nonuniform shading using externally supplied 12-bit unsigned values. The external correction factors are supplied at the multiplexed pixel rate. The external correction range is from 0 to 4, which allows shading nonuniformity of up to 75% (i.e., the minimum input signal is 25% of the peak) to be corrected without loss of resolution in the high gain pixels at the center of the scan. Internal default registers are provided to set the gain through this block during calibration. The internal registers default to a value of 1 (equivalent to decimal 1024 in this range) on reset. global offset adjust Global offset adjust is provided by an adder using three independent bipolar offset coefficients set through the serial interface. A range of ±4 times the ADC full-scale range in steps of a half output LSB is provided. This range allows the output signal to be shifted across the entire range of the 16-bit output bus. The global offset coefficients are programmed as 16-bit 2s complement numbers, which default to zero on reset. global gain adjust Global gain adjust is provided by a multiplier using gain values set through the serial interface. Three independent 16-bit gain values with a range of 0 to 2 are stored (one for each channel). The default value of the global gain coefficients is 1 (equivalent to decimal 32768 in this range). threshold detector The threshold detector operates on the output signal from the global gain adjust stage, comparing the signal to individual threshold levels for each color channel, which are programmed through the serial interface. If the signal exceeds the threshold, the DETOP terminal is forced high. Two basic modes of operation can be programmed, either multiplexing between the three channels in sequence with the internal data, or operating continuously on one of the three channels. The input signals to the threshold detector are represented as 16-bit bipolar 2s complement numbers. Threshold values should be programmed as 15-bit unipolar numbers in the range 0 to 32767. effect of image processing on ADC output The combined effect of the image processing sections on the ADC output is summarized by the formula in the note following Table 4. All values are shown in decimal. Examples of the process are given in Table 4. Examples 1–8 show the results with no pixel offset scaling. Examples 9–11 show the added effect of pixel offset scaling. All examples use a half range ADC value (2048) for the ADC output (ADCOP). If defaults are used throughout, then the output of the ADC is output directly on the OP0–OP11 bus as listed in Table 4, example 1.
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Table 4. Examples of Image Processing on ADC Output
functions as an under range signal in 16-bit unipolar clipping mode. into the device on the rising edge of SCK. The data stream comprises 6 address bits and two 8-bit data words. Figure 14. Serial Interface Timing diagrams are shown in Figure 15, 16, and 17.
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Table 5. Serial Interface Register Map
000000 Setup
000001 Setup
000010 Reserved 1
000011 Software reset 1
2 D7 D6 D5 D4 D3 D2 D1
‡ The address decoding is applicable for default pixel gain in monochrome mode.
Table 6. Control Bit Descriptions
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Figure 15. System Timing – Color Mode
† The CC(10) output state is defined via the serial bus in monochrome mode. Figure 16. System Timing – Monochrome Mode
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NOTE A: All thresholds are set to 10 hex. Figure 17. Timing of Threshold Detector Output DETOP
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 – JUNE 1997 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
running the TLC8044 at 4-megasamples/sec in CDS monochrome mode The TLC8044 can be set up to provide a 4-megasample/sec throughput when in CDS monochrome mode; however, the VSMP input must run continuously at 4 MHz. The following paragraphs describe operation of the TLC8044 in monochrome mode (sampling one channel only). The maximum sample rate in color CDS mode is 2-megasamples/channel/sec. In CDS mode, the video signal is sampled both during the reset phase and when video information is present with timing defined to a VSMP input. The difference between these two samples forms the input to the ADC. In monochrome mode, all samples are taken from one input video channel. The device is set up as listed in Table 6. See Tables 4 and 5 for offset DAC values in CDS mode. System timing is shown in Figure 18. MCLK clocks the device at 12 MHz (as normal). VSMP, which controls the sample rate, is run at 4 MHz. A reset sample is taken on the rising edge of MCLK after VSMP is asserted. The corresponding video sample is taken on the next MCLK rising edge. Compensation coefficients (pixel offset and pixel shading) are sampled on the falling edge of MCLK 26.5 periods after the initial reset sample. The processed digital outputs appear on OP0–OP15 41.5 MCLK periods after the initial reset sample. In Figure 18 the system timing diagram shows a negative-going video sample. The polarity of the ADC output signal can be inverted under control of the serial interface. Setup and hold times are specified in the recommended operating conditions table. Table 7. Relevant Register Settings
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2.64 MCLK From Reset Sample
41.5 MCLK From Reset Sample
Figure 18. System Timing – CDS Mode at 4-Megasamples/Sec
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC8044CFN OBSOLETE PLCC FN 68 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1
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