TLC545C TI | Alldatasheet
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TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00688-Bit Resolution A/D Converter /C0068Microprocessor Peripheral or Stand-Alone Operation /C0068On-Chip 20-Channel Analog Multiplexer /C0068Built-in Self-Test Mode /C0068Software-Controllable Sample and Hold /C0068Total Unadjusted Error...± 0.5 LSB Max /C0068Timing and Control Signals Compatible With 8-Bit TLC540 and 10-Bit TLC1540 A/D Converter Families /C0068CMOS Technology PARAMETER TL545 TL546 Channel Acquisition Time Conversion Time (Max) Sampling Rate (Max) Power Dissipation (Max) 1.5 µs 9 µs 76 x 103 15 mW 2.7 µs 17 µs 40 x 103 15 mW
description
The TLC545 and TLC546 are CMOS analog-to-digital converters built around an 8-bit switched capacitor successive-approximation analog-to-digital converter. They are designed for serial interface to a microprocessor or peripheral via a 3-state output with up to four control inputs including independent SYSTEM CLOCK, I/O CLOCK, chip select (CS ), and ADDRESS INPUT. A 4-MHz system clock for the TLC545 and a 2.1-MHz system clock for the TLC546 with a design that includes simultaneous read/write operation allowing high-speed data transfers and sample rates of up to 76,923 samples per second for the TLC545, and 40,000 samples per second for the TLC546. In addition to the high-speed converter and versatile control logic, there is an on-chip 20-channel analog multiplexer that can be used to sample any one of 19 inputs or an internal self-test voltage, and a sample-and-hold that can operate automatically or under microprocessor control. The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally switched capacitor design allows low-error (± 0.5 LSB) conversion in 9 µs for the TLC545, and 17 µs for the TLC546, over the full operating temperature range. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 INPUT A9 INPUT A10 INPUT A11 INPUT A12 GND V CC SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A18 INPUT A17 INPUT A16 INPUT A15 INPUT A14 INPUT A13 N PACKAGE (TOP VIEW) 321 13 14 ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A18 INPUT A17 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 INPUT A9 INPUT A10 15 16 1718 INPUT A12 GND INPUT A13 INPUT A14 INPUT A15 INPUT A16 INPUT A3 INPUT A2 INPUT A1 INPUT A0 FN PACKAGE (TOP VIEW) 28 27 26
12 INPUT A11
V SYSTEM CLOCK I/O CLOCK CC
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(FN) PLASTIC DIP (N) 0°C to 70°C TLC545CFN TLC545CN –40°C to 85°C TLC545IFN TLC546IFN TLC545IN TLC546IN description (continued) The TLC545C and the TLC546C are characterized for operation from 0°C to 70°C. The TLC545I and the TLC546I are characterized for operation from –40°C to 85°C. functional block diagram SYSTEM CLOCK CS I/O CLOCK ADDRESS INPUT 8-Bit Analog-to-Digital Converter (Switched-capacitors) REF–REF+ DATA OUT 8-to-1 Data Selector and Driver Control Logic and I/O Counters Output Data Register Input Multiplexer Self-Test Reference Input Address Register Sample and Hold 20-Channel Analog Multiplexer INPUTS A10 A11 A12 A13 A14 A15 A16 A17 A18 22 21
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP C i = 60 pF TYP (equivalent input capacitance)
5 MΩ TYP
A0–A18 INPUT A0–A18 operating sequence Access Cycle B (see Note C) B0B2 C4 twH(CS) Don’t Care B0B1B2B3B4B5B6B7 C3 C2 C1 C0 LSBMSB Conversion Data B MSBMSB LSB Hi-Z State Don’t Care MSB LSB (see Note B) MSB Previous Conversion Data A A7 A6 A5 A4 A3 A2 A1 A0 LSB B1B3 MSB Don’t See Note A tconv Sample Cycle B 88 765432765432 I/O CLOCK CS DATA OUT ADDRESS INPUT Care Access Cycle C Sample Cycle C Hi-Z State NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK↓ after CS↓ for the channel whose address exists in memory at that time. B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6–A0) will be clocked out on the first seven I/O CLOCK falling edges. C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time has elapsed.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions TLC545 TLC546 UNIT MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.5 4.75 5 5.5 V Positive reference voltage, Vref+ (see Note 2) 0 VCC VCC +0.1 0 VCC VCC +0.1 V Negative reference voltage, Vref– (see Note 3) –0.1 0 VCC –0.1 0 VCC V Differential reference voltage, Vref+ – Vref– (see Note 3) 0 VCC VCC +0.2 0 VCC VCC +0.2 V Analog input voltage (see Note 3) 0 VCC 0 VCC V High-level control input voltage, VIH 2 2 V Low-level control input voltage, VIL 0.8 0.8 V Setup time, address bits at data input before I/O CLOCK↑, tsu(A) 200 400 ns Address hold time, th 0 0 ns Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 2) 3 3 System clock cycles I/O CLOCK frequency, fclock(I/O) 0 2.048 0 1.1 MHz SYSTEM CLOCK frequency, fclock(SYS) fclock(I/O) 4 fclock(I/O) 2.1 MHz Pulse duration, CS high during conversion, twH(CS) 36 36 System clock cycles Pulse duration, SYSTEM CLOCK high, twH(SYS) 110 210 ns Pulse duration, SYSTEM CLOCK low, twL(SYS) 100 190 ns Pulse duration, I/O CLOCK high, twH(I/O) 200 404 ns Pulse duration, I/O CLOCK low, twL(I/O) 200 404 ns System fclock(SYS) ≤ 1048 kHz 30 30 ns Clock transition time System fclock(SYS) > 1048 kHz 20 20 ns (see Note 4) I/O fclock(I/O) ≤ 525 kHz 100 100 nsI/O fclock(I/O) > 525 kHz 40 40 ns O perating free air temperature TA TLC545C, TLC546C 0 70 0 70 Operating free-air temperature, TA TLC545I, TLC546I –40 85 –40 85 °C NOTES: 2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed. 3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied to REF– convert as all “0”s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends to increase. 4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC545 or fclock(I/O) = 1.1 MHz for TLC546 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage (DATA OUT) VCC = 4.75 V, IOH = –360 µA 2.4 V VOL Low-level output voltage VCC = 4.75 V, IOL = 3.2 mA 0.4 V IOZ Off state (high impedance state) ouput current VO = VCC , CS at VCC 10 µAIOZ Off-state (high-impedance state) ouput current VO = 0, CS at VCC –10 µA IIH High-level input current VI = VCC 0.005 2.5 µA IIL Low-level input current VI = 0 –0.005 –2.5 µA ICC Operating supply current CS at 0 V 1.2 2.5 mA Selected channel leakage current Selected channel at VCC , Unselected channel at 0 V 0.4 1 µASelected channel leakage current Selected channel at 0 V, Unselected channel at VCC –0.4 –1 µA ICC + Iref Supply and reference current Vref+ = VCC , CS at 0 V 1.3 3 mA C i Input capacitance Analog inputs 7 55 pFC i Input capacitance Control inputs 5 15 pF † All typical values are at TA = 25°C.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC545 or 1.1 MHz for TLC546, fclock(SYS) = 4 MHz for TLC545 or 2.1 MHz for TLC546 PARAMETER TEST CONDITIONS TLC545 TLC546 UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT EL Linearity error See Note 5 ± 0.5 ± 0.5 LSB EZS Zero-scale error See Note 6 ± 0.5 ± 0.5 LSB EFS Full-scale error See Note 6 ± 0.5 ± 0.5 LSB Total unadjusted error See Note 7 ± 0.5 ± 0.5 LSB Self-test output code INPUT A19 address = 10011 (see Note 8) 01111101 (125) 10000011 (131) 01111101 (125) 10000011 (131) tconv Conversion time See Operating Sequence 9 17 µs Total access and conversion time See Operating Sequence 13 25 µs tacq Channel acquisition time (sample cycle) See Operating Sequence 3 3 I/O clock cycles tv Time output data remains valid after I/O CLOCK↓ 10 10 ns td Delay time, I/O CLOCK to DATA OUT valid 300 400 ns ten Output enable time See Parameter 150 150 ns tdis Output disable time See Parameter Measurement Information 150 150 ns tr(bus) Data bus rise time 300 300 ns tf(bus) Data bus fall time 300 300 ns NOTES: 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is internally generated and is used for test purposes.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION See Note B 0.4 V 2.4 V tf Output tr 0.8 V 2.4 V 0.8 V td DATA OUT VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES VOLTAGE WAVEFORMS FOR DELAY TIME VCC 3 kΩ 3 kΩ VCC See Note B SYSTEM CLOCK 50% 50% 0 V 0 V tPLZ I/O CLOCK VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES Output Waveform 1 (see Note C) tPHZ tPZH VOH90% 10% tPZL 0 V VCC 50% CS LOAD CIRCUIT FOR tPZL AND tPLZ LOAD CIRCUIT FOR tPZH AND tPHZ LOAD CIRCUIT FOR td, tr, AND tf See Note B C L (see Note A) Output Under Test Test Point 3 kΩ 1.4 V Output Waveform 2 (see Note C) C L (see Note A) Output Under Test Test Point C L (see Note A) Output Under Test Test Point NOTES: A. C L = 50 pF for TLC545 and 100 pF for TLC546 B. ten = tPZH or tPZL , tdis = tPHZ or tPLZ C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
This time must be less than the converter sample time shown in the timing diagrams.
- Noise and distortion for the source must be equivalent to the resolution of the converter.
- R s must be real at the input frequency. R s ri VS VC 50 pF MAX 1 kΩ MAX Driving Source† TLC545/6 C i VI
Figure 1. Equivalent Input Circuit Including the Driving Source
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions as system clock, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs; CS , ADDRESS INPUT, I/O CLOCK, and SYSTEM CLOCK. These control inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer. The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 µs respectively, while complete input-conversion-output cycles can be repeated at a maximum of 13 and 25 µs, respectively. The system clock and I/O clock are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using the I/O CLOCK. SYSTEM CLOCK will drive the “conversion crunching” circuitry so that the control hardware and software need not be concerned with this task. When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and I/O CLOCK are disabled. This feature allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals on additional A/D devices when additional TLC545/TLC546 devices are used. Thus, the above feature serves to minimize the required control logic terminals when using multiple A/D devices. The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is: 1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges and then a falling edge of the SYSTEM CLOCK after a CS transition before the transition is recognized. The MSB of the previous conversion result automatically appears on DATA OUT. 2. A new positive-logic multiplexer address is shifted in on the first five rising edges of I/O CLOCK. The MSB of the address is shifted in first. The negative edges of these five I/O clocks shift out the second, third, fourth, fifth, and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage. 3. Two clock cycles are then applied to I/O CLOCK and the seventh and eighth conversion bits are shifted out on the negative edges of these clock cycles. 4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36 system clock cycles to allow for the conversion function. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on the I/O CLOCK line, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress. A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling circuitry points must be minimized. In this case, the following special points must be considered in addition to the requirements of the normal control sequence previously described. 1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock signal is used for the conversion clock also. 2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address. Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise, additional common clock cycles are recognized as I/O CLOCKS and shift in an erroneous address. For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time. This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid I/O clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling the analog input until the eighth valid falling edge of the I/O clock. The control circuitry or software must then immediately lower the I/O clock signal to initiate the hold function at the desired point in time and to start conversion.
TLC545C, TLC545I, TLC546C, TLC546I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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