TLC540I_14 TI1 | Alldatasheet
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TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 8-Bit Resolution A/D Converter /C0068 Microprocessor Peripheral or Stand-Alone Operation /C0068 On-Chip 12-Channel Analog Multiplexer /C0068 Built-In Self-Test Mode /C0068 Software-Controllable Sample and Hold /C0068 Total Unadjusted Error... ± 0.5 LSB Max /C0068 TLC541 Is Direct Replacement for Motorola MC145040 and National Semiconductor ADC0811. TLC540 Is Capable of Higher Speed /C0068 Pinout and Control Signals Compatible With TLC1540 Family of 10-Bit A/D Converters /C0068 CMOS Technology PARAMETER TLC540 TLC541 Channel Acquisition Sample Time Conversion Time (Max) Samples per Second (Max) Power Dissipation (Max) 2 µs 9 µs 75 x 103 12.5 mW 3.6 µs 17 µs 40 x 103 12.5 mW
description
The TLC540 and TLC541 are CMOS A/D converters built around an 8-bit switched- capacitor successive-approximation A/D converters. They are designed for serial interface to a microprocessor or peripheral via a 3-state output with up to four control inputs, including independent SYSTEM CLOCK, I/O CLOCK, chip select (CS ), and ADDRESS INPUT. A 4-MHz system clock for the TLC540 and a 2.1-MHz system clock for the TLC541 with a design that includes simultaneous read/write operation allow high-speed data transfers and sample rates of up to 75,180samples per second for the TLC540 and 40,000 samples per second for the TLC541. In addition to the high-speed converter and versatile control logic, there is an on-chip 12-channel analog multiplexer that can be used to sample any one of 11 inputs or an internal self-test voltage, and a sample-and-hold that can operate automatically or under microprocessor control. AVAILABLE OPTIONS PACKAGE TA SO PLASTIC DIP (DW) PLASTIC DIP (N) CHIP CARRIER (FN) –40°C to 85°C — TLC541IDW TLC540IN TLC541IN TLC540IFN TLC541IFN –55°C to 125°C — TLC541MN — Copyright 2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 GND V CC SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A10 INPUT A9 DW OR N PACKAGE (TOP VIEW) 3 2 1 20 19 91 0 1 1 1 2 1 3 I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 FN PACKAGE (TOP VIEW)INPUT A2 INPUT A1 INPUT A0 INPUT A10 REF– SYSTEM CLOCK INPUT A8 GND INPUT A9 VCC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued) The converters incorporated in the TLC540 and TLC541 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A switched-capacitor design allows low-error (± 0.5 LSB) conversion in 9 µs for the TLC540 and 17 µs for the TLC541 over the full operating temperature range. The TLC540I and TLC541I are characterized for operation from –40°C to 85°C.The TLC541M is characterized for operation from –55°C to 125°C. functional block diagram SYSTEM CLOCK CS I/O CLOCK ADDRESS INPUT 8-Bit Analog-to-Digital Converter (Switched-Capacitors) REF–REF+ DATA OUT 8-to-1 Data Selector and Driver Control Logic and I/O Counters Output Data Register Input Multiplexer Self-Test Reference Input Address Register Sample and Hold 12-Channel Analog Multiplexer Analog Inputs A10 14 13 typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP C i = 60 pF TYP (equivalent input capacitance)
5 MΩ TYP
A0–A10 INPUT A0–A10
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating sequence ADDRESS INPUT Hi-Z B0B1B2B3B4B5B6B7 C3 C2 C1 C0 LSBMSB Conversion Data B MSBMSB LSB Hi-Z State Don ’t Care MSBLSBMSB (See Note B) A7 A6 A5 A4 A3 A2 A1 A0 State LSB B0B1B2 MSB Don’t Care Sample Cycle C Access Cycle C See Note A tconv Sample Cycle B Access Cycle B (see Note C) 88 765432765432 I/O CLOCK CS DATA OUT Don ’t Care twH(CS) Previous Conversion Data A NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated on the 8th falling edge of I/O CLOCK after CS goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, I/O CLOCK must remain low for at least 36 system clock cycles to allow conversion to be completed. B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6–A0) will be clocked out on the first seven I/O CLOCK falling edges. C. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time has elapsed. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions TLC540 TLC541 UNIT MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.5 4.75 5 5.5 V Positive reference voltage, Vref+ (see Note 2) 2.5 VCC VCC +0.1 2.5 VCC VCC +0.1 V Negative reference voltage, Vref– (see Note 2) –0.1 0 2.5 – 0.1 0 2.5 V Differential reference voltage, Vref+ – Vref– (see Note 2) 1 VCC VCC +0.2 1 VCC VCC +0.2 V Analog input voltage (see Note 2) 0 VCC 0 VCC V High-level control input voltage, VIH 2 2 V Low-level control input voltage, VIL 0.8 0.8 V Setup time, address bits at data input before I/O CLOCK↑, tsu(A) 200 400 ns Hold time, address bits after I/O CLOCK↑,th(A) 0 0 ns Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3) 3 3 System clock cycles CS high during conversion, twH(CS) 36 36 System clock cycles I/O CLOCK frequency, fclock(I/O) 0 2.048 0 1.1 MHz Pulse duration, SYSTEM CLOCK frequency, fclock(SYS) fclock(I/O) 4 fclock(I/O) 2.1 MHz Pulse duration, SYSTEM CLOCK high, twH(SYS) 110 210 MHz Pulse duration, SYSTEM CLOCK low, twL(SYS) 100 190 MHz Pulse duration, I/O clock high, twH(I/O) 200 404 ns Pulse duration, I/O clock low, twL(I/O) 200 404 ns System fclock(SYS) ≤ 1048 kHz 30 30 Clock transition time System fclock(SYS) > 1048 kHz 20 20 ns(see Note 4) I/O fclock(I/O) ≤ 525 kHz 100 100 ns I/O fclock(I/O) > 525 kHz 40 40 Operating free-air temperature, TA TLC540I, TLC541I –40 85 –40 85 °C NOTES: 2. Analog input voltages greater than that applied to REF + convert as all 1s (11111111), while input voltages less than that applied to REF – convert as all 0s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 3. To minimize errors caused by noise at CS, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum chip select setup time has elapsed. 4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC540 or fclock(I/O) = 1.1 MHz for TLC541 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage, DATA OUT VCC = 4.75 V,IOH = 360 µA 2.4 V VOL Low-level output voltage VCC = 4.75 V,IOL = 1.6 mA 0.4 V IOZ Off state (high impedance state) output current VO = VCC , CS at VCC 10 µAIOZ Off-state (high-impedance state) output current VO = 0, CS at VCC –10 µA IIH High-level input current VI =VCC 0.005 2.5 µA IIL Low-level input current VI = 0 –0.005 –2.5 µA ICC Operating supply current CS at 0 V 1.2 2.5 mA Selected channel leakage current Selected channel at VCC , Unselected channel at 0 V 0.4 1 µASelected channel leakage current Selected channel at 0 V, Unselected channel at VCC –0.4 –1 µA ICC + Iref Supply and reference current Vref+ = VCC , CS at 0 V 1.3 3 mA C i Input capacitance Analog inputs 7 55 pFC i Input capacitance Control inputs 5 15 pF † All typical values are at TA = 25°C.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, VCC = Vref+ – 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC540 or 1.1 MHz for TLC541, fclock(SYS) = 4 MHz for TLC540 or 2.1 MHz for TLC541 PARAMETER TEST CONDITIONS TLC540 TLC541 UNITPARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT EL Linearity error See Note 5 ± 0.5 ± 0.5 LSB EZS Zero–scale error See Notes 2 and 6 ± 0.5 ± 0.5 LSB EFS Full-scale error See Notes 2 and 6 ± 0.5 ± 0.5 LSB Total unadjusted error See Note 7 ± 0.5 ± 0.5 LSB Self-test output code Input A11 address = 1011, (see Note 8) 01111101 (125) 10000011 (131) 01111101 (125) 10000011 (131) tconv Conversion time See operating sequence 9 17 µs Total access and conversion time See operating sequence 13.3 25 µs ta Channel acquisition time (sample cycle)See operating sequence 4 4 I/O clock cylces tv Time output data remains valid after I/O CLOCK↓ 10 10 ns td Delay time, I/O CLOCK↓ to data output valid 300 400 ns ten Output enable time See Parameter 150 150 ns tdis Output disable time See Parameter Measurement Information 150 150 ns tr(bus) Data bus rise time 300 300 ns tf(bus) Data bus fall time 300 300 ns NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (11111111) while input voltages less than that applied to REF – convert to all 0s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION See Note B 0.4 V 2.4 V tf Output tr 0.8 V 2.4 V 0.8 V td DATA OUT VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES VOLTAGE WAVEFORMS FOR DELAY TIME VCC 3 kΩ 3 kΩ VCC See Note B SYSTEM CLOCK 50% 50% 0 V 0 V tPLZ I/O CLOCK VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES Output Waveform 1 (see Note C) tPHZ tPZH VOH90% 10% tPZL 0 V VCC 50% CS LOAD CIRCUIT FOR tPZL AND tPLZ LOAD CIRCUIT FOR tPZH AND tPHZ LOAD CIRCUIT FOR td, tr, AND tf See Note B C L (see Note A) Output Under Test Test Point 3 kΩ 1.4 V Output Waveform 2 (see Note C) C L (see Note A) Output Under Test Test Point C L (see Note A) Output Under Test Test Point NOTES: A. C L = 50 pF for TLC540 and 100 pF for TLC541. B. ten = tPZH or tPZL , tdis = tPHZ or tPLZ . C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
simplified analog input analysis Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by (1) where R t = Rs + ri V C /C0043 V S/C04661–e–tc/C0324 R tC i/C0467 The final voltage to 1/2 LSB is given by (2)VC (1/2 LSB) = VS – (VS /512) Equating equation 1 to equation 2 and solving for time tc gives (3) and tc (1/2 LSB) = Rt × Ci × ln(512) (4) V S /C0042 /C0466V S/C0324 512/C0467 /C0043 V S/C04661–e–tc/C0324 R tC i/C0467 Therefore, with the values given the time for the analog input signal to settle is (5)tc (1/2 LSB) = (Rs + 1 kΩ ) × 60 pF × ln(512) This time must be less than the converter sample time shown in the timing diagrams. R s ri VS VC 50 pF MAX 1 kΩ MAX Driving Source† TLC540/1 C i VI VI = Input Voltage at INPUT A0–A10 VS = External Driving Source Voltage R s = Source Resistance ri = Input Resistance C i = Equivalent Input Capacitance † Driving source requirements:
- Noise and distortion for the source must be equivalent to the resolution of the converter.
- R s must be real at the input frequency.
Figure 1. Equivalent Input Circuit Including the Driving Source
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such functions as analog multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs [two clocks, chip select (CS ), and address]. These control inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer. With judicious interface timing, with TLC540 a conversion can be completed in 9 µs, while complete input- conversion-output cycles can be repeated every 13 µs. With TLC541 a conversion can be completed in 17 µs, while complete input-conversion-output cycles are repeated every 25 µs. Furthermore, this fast conversion can be executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor. The system and I/O clocks are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to SYSTEM CLOCK, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion crunching circuitry so that the control hardware and software need not be concerned with this task. When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals on additional A/D devices when additional TLC540/541 devices are used. In this way, the above feature serves to minimize the required control logic terminals when using multiple A/D devices. The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is: 1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized. This technique is used to protect the device against noise when the device is used in a noisy environment. The MSB of the previous conversion result automatically appears on DATA OUT. 2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage. 3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are shifted out on the negative edges of these clock cycles. 4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36 system clock cycles to allow for the conversion function. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress. A new conversion can be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.
TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
It is possible to connect SYSTEM CLOCK and I/O clock together in special situations in which controlling circuitry points must be minimized. In this case, the following special points must be considered in addition to the requirements of the normal control sequence previously described. 1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock signal is used for the conversion clock also. 2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address. Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise, additional common clock cycles are recognized as I/O CLOCKS and will shift in an erroneous address. For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time. This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid I/O clock cycle until the moment at which the analog signal must be converted. The TLC540/TLC541 continues sampling the analog input until the eighth falling edge of the I/O clock. The control circuitry or software then immediately lowers the I/O clock signal and holds the analog signal at the desired point in time and start conversion. Detailed information on interfacing to most popular microprocessors is readily available from the factory.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC540IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC540IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC540IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC540IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC540IFN ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC540IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC540IFNR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC540IFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC540IN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC540INE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC541IDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC541IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC541IDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC541IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC541IFN ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC541IFNG3 ACTIVE PLCC FN 20 46 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC541IFNR ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC541IFNRG3 ACTIVE PLCC FN 20 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM TLC541IN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC541INE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC541MN OBSOLETE PDIP N 20 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2009 Addendum-Page 1
http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 27-Aug-2009 Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC540IDWR SOIC DW 20 2000 367.0 367.0 45.0 TLC541IDWR SOIC DW 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 Pack Materials-Page 2
MPLC004A – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95
20 PIN SHOWN
0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018
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