TLC532A TI1 | Alldatasheet
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Technical content
REF – GND 2 – 1 (MSB) 2 – 2 2 – 3 2 – 4 2 – 5 2 – 6 2 – 7 2 – 8 (LSB) R/ W CLK RS CS REF + (A1) V CC A10/D1 A11/D2 A12/D3 A13/D4 A14/D5 A15/D6 R Analog Inputs Analog/ Digital Inputs I/O Data Bus 3212 8 2 7 12 13 A10/D1 A11/D2 A12/D3 – 3 2 – 4 2 – 5 2 – 6 2 – 7 2 – 8 (LSB) R/ W 42 6 14 15 16 17 18 CLK RS CS R A15/D6 A14/D5 A13/D4 GND REF – REF + (A1) V FN PACKAGE (TOP VIEW) CC – 1(MSB) – 2 N PACKAGE (TOP VIEW) ADDRESS/CONTROL DISCRIPTION X L L L H FUNCTION TABLE CS R CLK H H H H X Reset Write bus data to control register Read data from analog conversion register Read data from digital register No response X L H H X R/W X H L H X RS H=High-level, L = Low-level, X = Irrelevant ↓=High-to-low transition, ↑ = Low-to-high transition † For proper operation, RESET must be low for at least three lock cycles. TLC532AI, TLC532AM, TLC533AI, TLC533AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Copyright 1986, Texas Instruments Incorporated
- LinCMOS Technology
- 8-Bit Resolution
- Total Unadjusted Error...±0.5 LSB Max
- Ratiometric Conversion
- Access Plus Conversion Time: TLC532A ...1 5 µs Max TLC533A ...3 0 µs Max
- 3-State, Bidirectional I/O Data Bus
- 5 Analog and 6 Dual-Purpose Inputs
- On-Chip 12-Channel Analog Multiplexer
- Three On-Chip 16-Bit Data Registers
- Software Compatible With Larger TL530 and TL531 (21-Input Versions)
- On-Chip Sample-and-Hold Circuit
- Single 5-V Supply Operation
- Low Power Consumptio n... 6.5 mW Typ
- Improved Direct Replacements for Texas Instruments TL532 and TL533, National Semiconductor ADC0829, and Motorola MC14442
description
The TLC532A and TLC533A are monolithic LinCMOS peripheral integrated circuits each designed to interface a microprocessor for analog data acquisition. These devices are complete peripheral data acquisition systems on a single chip and can convert analog signals to digital data from up to 11 external analog terminals. Each device operates from a single 5-V supply and contains a 12-channel analog multiplexer, and 8-bit ratiometric analog-to-digital (A/D) converter, a sample-and-hold circuit, three 16-bit registers, and microprocessor-compatible control circuitry. Additional features include a built-in self-test, sixmultipurpose (analog or digital) inputs, five external analog inputs, and an 8-pin input/output (I/O) data port. The three on-chip data registers store the control data, the conversion results, and the input digital data that can be accessed via the microprocessor data bus in two bytes LinCMOS is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TLC532AI, TLC532AM, TLC533AI, TLC533AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 752652 description (continued) (most-significant byte first). In this manner, a microprocessor can access up to 11 external analog inputs or 6 digital signals and the positive reference voltage that may be used for self-test. The A/D conversion uses the successive-approximation technique and switched-capacitor circuitry. This method eliminates the possibility of missing codes, nonmonotonicity, and a need for zero or full-scale adjustment. Any one of 11 analog inputs (or self-test) can be converted to an 8-bit digital word and stored within 10 µs for the TLC532A or 20 µs for theTLC533A after instructions from the microprocessor are recognized. The on-chip sample-and-hold circuit automatically minimizes errors due to noise on the analog inputs. Furthermore, differential high-impedance reference inputs are available to help isolate the analog circuitry from the logic and supply noises while easing ratiometric conversion and scaling. The TLC532AI and TLC533AI are characterized for operation from – 40°C to 85°C. The TLC532AM and TLC533AM are available in both the N and FN plastic packages and are characterized for operation from – 55°C to 125°C. functional description The TLC532A and TLC533A provide direct interface to a microprocessor-based system. Control of the TLC532A and TLC533A is handled via the 8-line TTL-compatible 3-state data bus, the three control inputs (R/W, RS, and CS), and the CLK input. Each device contains three 16-bit internal registers — the control register, the analog conversion data register, and the digital data register. A high level at the R/W input and a low level at the CS input set the device to output data on the 8-line data bus for the processor to read. A low level at the R/W input and a low level at the CS input set the device to receive instructions into the internal control register on the 8-line data bus from the processor. When the device is in the read mode and the RS input is low, the processor reads the data contained in the analog conversion data register. However, when the RS input is high, the processor reads the data contained in the digital-data register. The control register is a write-only register into which the microprocessor writes command instructions for the device to start A/D conversion and to select the analog channel to be converted. The analog conversion data register is a read-only register that contains the current converter status and most recent conversion results. The digital data register is also a read-only register that holds the digital input logic levels from the six dual-purpose inputs. Internally each device contains a byte pointer that selects the appropriate byte during two cycles of the CLK input in a normal 16-bit microprocessor instruction. The internal pointer automatically points to the most significant (MS) byte after the first complete clock cycle any time that the CS is at the high level for at least one clock cycle. The device treats the next signal on the 8-line data bus as the MS byte. A low level at the CS input activates the inputs and outputs and an internal function decoder. However, no data is transferred until the CLK goes high. The internal byte pointer first points to the MS byte of the selected register during the first clock cycle. After the first clock cycle in which the MS byte is accessed, the internal pointer switches to the LS byte and remains there for as long as CS is low. The MS byte of any register may be accessed by either an 8-bit or a 16-bit microprocessor instruction; however, the LS byte may only be accessed by a 16-bit microprocessor instruction. Normally, a 2-byte word is written or read from the controlling processor, but a single byte can be read by the processor by manipulating the CS input. This can be used to read conversion status from the analog conversion data register or the digital multipurpose input levels from the digital data register. The format and content of each 2-byte word is shown in Figures 1 through 3.
TLC532AI, TLC532AM, TLC533AI, TLC533AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 functional description (continued) A conversion cycle starts after a 2-byte instruction is written to the control register and the start conversion (SC) bit is a logic high. This 2-byte instruction also selects the input analog channel to be converted. The status (EOC) bit in the analog conversion data register is reset, and it remains reset until the conversion is complete, at which time the status bit is set again. After conversion, the results are loaded into the analog conversion data register. These results remain in the analog conversion data register until the next conversion cycle is complete. If a new conversion command is entered into the control register while the conversion cycle is in progress, the on-going conversion is aborted and a new channel acquisition cycle begins immediately. The reset input R allows the device to be externally forced to a known state. When a low level is applied to the R input for a minimum of three clock periods, the SC bit is cleared. The A/D converter is then idled and all the outputs are placed in the high-impedance off-state. However, the content of the analog conversion data register is not affected by the R input going to a low level. Detailed information on interfacing to most popular microprocessors is readily available from the factory. functional block diagram Data Bus Control Logic Digital Data Register (Read Only) 12-Channel Multiplexer 115 Analog MUX Address Control Register (Write Only) Analog Conversion Register (Read Only) 8-Bit Analog-to-Digital Converter (Switched Capacitors) Sample and Hold (2 – 8 – 2 – 1) R/W CS RS R CLOCK REF + REF – Data Bus Analog/Digital Input (A10/D1 – A15/D6) External Analog Input (A0, A2 – A5)
TLC532AI, TLC532AM, TLC533AI, TLC533AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986
4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265•
typical operating sequence 1 23 1 23456 2 8 9 2 9 0 twL (reset) Don’t Care tsu(A) Don’t Care tsu(CS) tsu(CS) tsu(A) Don’t Care (see Note A) (see Note B) tsu(bus) HI-Z State HI-Z State ten ten ten Don’t Care Don’t Care CLOCK R R/W CS RS DATA BUS ten (see Note C) (see Note D) (see Note F)(see Note E) = HI-Z States Start Conversion Cycle If SC Bit Is Logic One (High) Write Cycle Read Cycle Write Cycle tsu(A) tsu(A) tsu(bus) tsu(bus) Don’t Care ten ten ten ten tsu(A) tsu(A) tsu(A) tsu(bus) Don’t Care Don’t Care ten MS Byte LS Byte LS Byte LS Byte LS Byte MS Byte LS Byte MS Byte LS Byte MS Byte LS Byte PARAMETER MEASUREMENT INFORMATION (see Note C) (see Note A) NOTES: A. This is a 16-bit input instruction from the microprocessor being sent to the control data register. B. This is the 2-byte (16-bit) content of the digital data register being sent to the microprocessor. C. This is the LS byte (8-bit) content of the analog conversion data register being sent to the microprocessor. D. This is the LS byte (8-bit) content of the digital data register being sent to the microprocessor. E. These are MS byte (8-bit), LS byte (8-bit), and LS byte (8-bit) content of the analog conversion data register or digital data register being sent to the microprocessor. F. This is the 2-byte (16-bit) content of the analog conversion data register being sent to the microprocessor.
NOTES: A. The reset pulse (R low) is required only during powerup. B. The most significant byte output of Data Out occurs when CLK is high. When CLK is low, Data Out is in the high-impedance (off) state. bus for as long as CLK is kept high. Figure 1. Read or Write Cycle Voltage Waveforms
Unused Bits (X) – The MS byte bits 2 – 1 through 2 – 7 and LS byte bits 2 – 1 through 2 – 4 of the control register are not used internally. begins immediately after the completion of the control register write.
1 REF + (A1)
Figure 2. Word Format and Content for Control Register 2-Byte Write Figure 3. Word Format and Content for Analog Conversion Data Register 1-Byte and 2-Byte Read are read from these bits. A digital value is given for each pin even if some or all of these pins are being used as analog inputs. Analog Multiplexer Address (A0-A3) – The address of the selected analog channel presently addressed is given by these bits. Unused Bits (X) – LS byte bits 2 – 3 through 2 – 8 of the digital data register are not used. Figure 4. Word Format And Content For Digital Data Register 1-Byte and 2-Byte Read
TLC532AI, TLC532AM, TLC533AI, TLC533AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those under absolute maximum ratings may causr permanent damage to the device. This is a stress rating only, and functional operation of the devise at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. recommended operating conditions TLC532A TLC533A UNIT MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VCC 4.75 5 5.5 4.75 5 5.5 V Positive reference voltage, VREF+ See Note 2 2.5 VCC VCC + 0.1 2.5 VCC VCC + 0.1 V Negative reference voltage, VREF– See Note 2 – 0.1 0 2.5 – 0.1 0 2.5 V Differential reference voltage, VREF+ – VREF– 1 VCC VCC + 0.2 1 VCC VCC + 0.2 V Clock input VCC – 0.8 VCC – 0.8 High-level input voltage, VIH All other digital inputs 2 2 V Low-level input voltage, VIL Any digital input 0.8 0.8 V Setup time, CS low before CLK ↑, tsu(CS) 75 100 ns Setup time, Address (R/W and RS) before CLK ↑, tsu(A) 100 145 ns Setup time, Data bus input before start conversion, tsu(bus) 140 185 ns Hold time, Control (R/W, RS, and CS) after start conversion, th(C) 10 20 ns Hold time, Data bus input after start conversion, th(bus) 15 20 ns Pulse duration of control during read, tw(C) 305 575 ns Pulse druation, reset low, twL(reset) 3 3 Clock Cycles Pulse duration, clock high, tw(CLKH) 230 440 ns Pulse duration,clock low, tw(CLKL) 200 410 ns Clock rise time, tr(CLK) 15 25 ns Clock fall time, tf(CLK) 16 30 ns O perating free air temperature TA TLC__AM – 55 125 – 55 125 °COperating free-air temperature, TA TLC__AI – 40 85 – 40 85 NOTE 2: Analog input voltages greater than or equal to that applied to the REF+ terminal convert to all ones (11111111), while input voltages equal to or less than that applied to the REF– terminal convert to all zeros (00000000). For proper operation, the positive reference voltage, VREF+ , must be at least 1 V greater than the negative reference voltage, VREF– . In addition, unadjusted errors may increase as the differential reference voltage, VREF+ – VREF– , falls below 4.75 V.
TLC532AI, TLC532AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 752658 electrical characteristics over recommended operating free-air temperature range, VREF+ = VCC , VREF– at ground, fCLK = 2 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage IOH = – 1.6 mA 2.4 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V IIH High level input current Any digital or Clock input VIH =55V µAIIH High-level input current Any control input VIH = 5.5 V µA IIL Low level input current Any digital or Clock input VIL=0 – 10 µAIIL Low-level input current Any control input VIL = 0 – 1 µA IOZ Off state (high impdance state) output current VO = VCC 10 µAIOZ Off-state (high-impdance state) output current VO = 0 – 10 µA II Analog input current (see Note 3) VI = 0 to VCC ±500 nA Leakage current between selected channel and all other analog channels VI = 0 to VCC , Clock input at 0 V ±400 nA C i Input capacitance Digital pins 3 thru 10 4 30 pFC i Input capacitance Any other input pin 2 15 pF ICC + IREF+ Supply current plus reference current VCC = VREF+ = 5.5 V, Outputs open 1.5 3 mA ICC Supply current VCC = 5.5 V 1.4 2 mA NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle. operating chacteristics over recommended ranges VCC , VREF+ , and operating free-air temperature, VREF– at ground, fclock = 2 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Linearity error (see Note 4) ±0.5 LSB Zero error (see Note 5) ±0.5 LSB Full-scale error (see Note 5) ±0.5 LSB Total unadjusted error (see Note 6) ±0.5 LSB Absolute accuracy error (see Note 7) ±1 LSB tconv Conversion time (including channel acquisition time) 30 Clock Cycles tacq Channel acquisition time prior to starting conversion 10 Clock Cycles ten Data output enable time (see Note 8) C L = 50 pF, RL = 3 kΩ 250 ns tdis Data output disable time C L = 50 pF, RL = 3 kΩ 10 ns t (bus)Data output rise time High-impedance to high level C L =5 0pFR L =3k Ω 150 nstr(bus) Data output rise time Low-to-high level C L = 50 pF, R L = 3 kΩ 300 ns tf(bus) Data output fall time High-impedance to low level C L =5 0pFR L =3k Ω 150 nstf(bus) Data output fall time High-to-low level C L = 50 pF, R L = 3 kΩ 300 ns † Typical values are at VCC = 5 V, TA = 25°C. NOTES: 4. Linearity error is the deviation from the best straight line through the A/D transfer characteristics. 5. Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 6. Total unadjusted error is the sum of liinearity, zero, and full-scale errors. 7. Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step. This includes all errors including inherent quantization error, which is the ±0.5 LSB uncertainty caused by the A/D converters’ finite resolution. 8. If chip-select setup time, tsu(CS), is less than 0.14 µs, the effective data output enable time, ten, may extend such that tsu(CS) + ten is equal to a maximum of 0.475 µs.
TLC532AI, TLC532AM LinCMOS 8-BIT ANALOG-TO-DIGITAL PERIPHERALS WITH 5 ANALOG AND 6 DUAL-PURPOSE INPUTS SLAS070 – D2819, NOVEMBER 1983 – REVISED SEPTEMBER 1986 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 electrical characteristics over recommended ranges VCC , VREF+ , and operating free-air temperature, VREF– at ground, fCLK = 1.048 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level output voltage IOH = – 1.6 mA 2.4 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V IIH High level input current Any digital or Clock input VIH =55V µAIIH High-level input current Any control input VIH = 5.5 V µA IIL Low level input current Any digital or Clock input VIL=0 – 10 µAIIL Low-level input current Any control input VIL = 0 – 1 µA IOZ Off state (high impdance state) output current VO = VCC 10 µAIOZ Off-state (high-impdance state) output current VO = 0 – 10 µA II Analog input current (see Note 3) VI = 0 to VCC ±500 nA Leakage current between selected channel and all other analog channels VI = 0 to VCC , Clock input at 0 V ±400 nA C i Input capacitance Digital pins 3 thru 10 4 30 pFC i Input capacitance Any other input pin 2 15 pF ICC + IREF+ Supply current plus reference current VCC = VREF+ = 5.5 V, Outputs open 1.5 3 mA ICC Supply current VCC = 5.5 V 1.2 2 mA NOTE 3: Analog input current is an average of the current flowing into a selected analog channel input during one full conversion cycle. operating chacteristics over recommended operating free-air temperature range, VREF+ = VCC , VREF– at ground, fCLK = 1.048 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT Linearity error (see Note 4) ±0.5 LSB Zero error (see Note 5) ±0.5 LSB Full-scale error (see Note 5) ±0.5 LSB Total unadjusted error (see Note 6) ±0.5 LSB Absolute accuracy error (see Note 7) ±1 LSB tconv Conversion time (including channel acquisition time) 30 Clock Cycles tacq Channel acquisition time prior to starting conversion 10 Clock Cycles ten Data output enable time See Note 8 C L = 50 pF, RL = 3 kΩ 335 ns tdis Data output disable time C L = 50 pF, RL = 3 kΩ 10 ns t (bus)Data bus output rise time High-impedance to high level C L =5 0pFR L =3k Ω 150 nstr(bus) Data bus output rise time Low-to-high level C L = 50 pF, R L = 3 kΩ 300 ns tf(bus) Data bus output fall time High-impedance to low level C L =5 0pFR L =3k Ω 150 nstf(bus) Data bus output fall time High-to-low level C L = 50 pF, R L = 3 kΩ 300 ns † Typical values are at VCC = 5 V, TA = 25°C. NOTES: 4 Linearity error is the deviation from the best straight line through the A/D transfer characteristics. 5 Zero error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 6 Total unadjusted error is the sum of liinearity, zero, and full-scale errors. 7 Absolute accuracy error is the maximum difference between an analog value and the nominal midstep value within any step. This includes all errors including inherent quantization error, which is the ±0.5 LSB uncertainty caused by the A/D converters’ finite resolution. 8 If chip-select setup time, tsu(CS), is less than 0.14 µs, the effective data output enable time, ten, may extend such that tsu(CS) + ten is equal to a maximum of 0.475 µs.
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