TLC4501IDG4

TLC4501_16 TI1 | Alldatasheet

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TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Self-Calibrates Input Offset Voltage to 40 µV Max /C0068 Low Input Offset Voltage Drift...1 µV/°C /C0068 Input Bias Current...1 p A /C0068 Open Loop Gain . . . 120 dB /C0068 Rail-To-Rail Output Voltage Swing /C0068 Stable Driving 1000 pF Capacitive Loads /C0068 Gain Bandwidth Product. . . 4.7 MHz /C0068 Slew Rate. . . 2.5 V/µs /C0068 High Output Drive Capability . . .±50 mA /C0068 Calibration Time. . . 300 ms /C0068 Characterized From –55°C to 125°C /C0068 Available in Q-Temp Automotive HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards

description

The TLC4501 and TLC4502 are the highest precision CMOS single supply rail-to-rail operational amplifiers available today. The input offset voltage is 10 µV typical and 40 µV maximum. This exceptional precision, combined with a 4.7-MHz bandwidth, 2.5-V/µs slew rate, and 50-mA output drive, is ideal for multiple applications including: data acquisition systems, measurement equipment, industrial control applications, and portable digital scales. These amplifiers feature self-calibrating circuitry which digitally trims the input offset voltage to less than 40 µV within the first 300 ms of operation. The offset is then digitally stored in an integrated successive approximation register (SAR). Immediately after the data is stored, the calibration circuitry effectively drops out of the signal path, shuts down, and the device functions as a standard operational amplifier. Power-On Reset IN+ OUT A/D Control Logic Oscillator D/A SAR GND IN– VDD 5 V Calibration Circuitry Offset Control3 Figure 1. Channel One of the TLC4502 Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. LinEPIC and Self-Cal are trademarks of Texas Instruments. processing does not necessarily include testing of all parameters.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued) Using this technology eliminates the need for noisy and expensive chopper techniques, laser trimming, and power hungry, split supply bipolar operational amplifiers. NC VDD + 2OUT 2IN – 2IN + NC 1OUT 1IN – 1IN + V DD –/GND 3 2 1 20 19 91 0 1 1 1 2 1 3 NC 2OUT NC 2IN– NC NC 1IN– NC 1IN+ NC NC 1OUT NC 2IN+ NC NC NC NC VDD+ VDD –/GND TLC4502 FK PACKAGE (TOP VIEW) NC – No internal connection 1OUT 1IN – 1IN + VDD –/GND VDD + 2OUT 2IN– 2IN+ TLC4502 D OR JG PACKAGE (TOP VIEW) NC 1IN – 1IN + VDD –/GND NC VDD + OUT NC TLC4501 D PACKAGE (TOP VIEW) TLC4502 U PACKAGE (TOP VIEW) AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25°C SMALL OUTLINE † (D) CHIP CARRIER (FK) CERAMIC DIP (JG) CERAMIC FLAT PACK (U) 40 µV TLC4501ACD — — — 0°Ct o7 0°C 50 µV TLC4502ACD — — — 0°C to 70°C 80 µV TLC4501CD — — — 100 µV TLC4502CD — — — 40 µV TLC4501AID — — — 40°Ct o1 2 5°C 50 µV TLC4502AID — — — –40°C to 125°C 80 µV TLC4501ID — — — 100 µV TLC4502ID — — — 40°Ct o1 2 5°C 50 µV TLC4502AQD — — — –40°C to 125°C 100 µV TLC4502QD — — — 55°Ct o1 2 5°C 50 µV TLC4502AMD TLC4502AMFKB TLC4502AMJGB TLC4502AMUB –55°C to 125°C 100 µV TLC4502MD TLC4502MFKB TLC4502MJGB TLC4502MUB † The D package is also available taped and reeled.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to VDD –/GND. 2. Differential voltages are at IN+ with respect to IN–. Excessive current flows when an input is brought below VDD – – 0.3 V. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°CPACKAGE A POWER RATING ABOVE T A = 25°C A POWER RATING A POWER RATING A POWER RATING D FK 725 mW 1375 W 5.8 mW/°C 11 0 W/ °C 464 mW 880 W 377 mW 715 W 145 mW

275 WFK

11.0 mW/°C 8 4 mW/°C 880 mW 672 mW 715 mW 546 mW 275 mW 210 mWJG U 1050 mW 675 mW 8.4 mW/ C 5.4 mW/°C 672 mW 432 mW 546 mW 350 mW 210 mW 135 mW recommended operating conditions TLC4502C TLC4502I TLC4502Q TLC4502M UNIT MIN MAX MIN MAX MIN MAX MIN MAX UNIT Supply voltage, VDD 4 6 4 6 4 6 4 6 V Input voltage range, VI VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 V Common-mode input voltage, VIC VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 VDD – VDD+ – 2.3 V Operating free-air temperature, TA 0 70 –40 125 –40 125 –55 125 °C

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V, GND = 0 (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC450xC UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT TLC4501 –80 10 80 VIO Input offset voltage VDD = ± 2.5 V, VO = 0, TLC4501A Full range –40 10 40 µVVIO Input offset voltage DD , VIC = 0, O , R S = 50 Ω TLC4502 Full range –100 10 100 µV TLC4502A –50 10 50 α VIO Temperature coefficient of input Full range 1 µV/°Cα VIO offset voltage Full range 1 µV/°C IIO Input offset current VDD = ± 2.5 V, VO = 0, 25°C 1 60 pAIIO Input offset current VDD ± 2.5 V, VIC = 0, VO 0, R S = 50 Ω Full range 500 pA IIB Input bias current 25°C 1 60 pAIIB Input bias current Full range 500 pA IOH = – 500 µA 25°C 4.99 VOH High-level output voltage IOH = 5m A 25°C 4.9 V IOH = – 5 mA Full range 4.7 VIC = 2.5 V, IOL = 500 µA 25°C 0.01 VOL Low-level output voltage VIC =25V IOL =5m A 25°C 0.1 V VIC = 2.5 V, IOL = 5 mA Full range 0.3 AVD Large-signal differential voltage VIC = 2.5 V, VO = 1 V to 4 V, 25°C 200 1000 V/mVAVD gg g amplification IC , R L = 1 kΩ , O , See Note 4 Full range 200 V/mV R I(D) Differential input resistance 25°C 10 kΩ R L Input resistance See Note 4 25°C 1012 Ω C L Common-mode input capacitance f = 10 kHz, P package 25°C 8 pF zO Closed-loop output impedance AV = 10, f = 100 kHz 25°C 1 Ω CMRR Common mode rejection ratio VIC = 0 to 2.7 V, VO = 2.5 V, 25°C 90 100 dBCMRR Common -mode rejection ratio IC , O , R S = 1 kΩ Full range 85 dB kSVR Supply-voltage rejection ratio VDD =4Vt o6V V IC = 0 No load 25°C 90 100 dBkSVR yg j (∆VDD ± /∆VIO) VDD = 4 V to 6 V, VIC = 0, No load Full range 90 dB TLC4501/A 25°C 1 1.5 IDD Supply current VO =25V No load TLC4501/A Full range 2 mAIDD Supply current VO = 2.5 V, No load TLC4502/A 25°C 2.5 3.5 mA TLC4502/A Full range 4 VIT(CAL) Calibration input threshold voltage Full range 4 VVIT(CAL) Calibration input threshold voltage Full range 4 V † Full range is 0°C to 70°C. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, VDD = 5 V PARAMETER TEST CONDITIONS TA † TLC450xC, TLC450xAC UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR Slew rate at unity gain VO =05Vt o25V C L = 100pF 25°C 1.5 2.5 V/µs SR Slew rate at unity gain VO = 0.5 V to 2.5 V, C L = 100 pF Full range 1 V/µs V Equivalent input noise voltage f = 10 Hz 25°C 70 nV/√HVn Equivalent input noise voltage f = 1 kHz 25°C 12 nV/√H z VN(PP) Peak-to-peak equivalent input noisef = 0.1 to 1 Hz 25°C 1 µVVN(PP) q voltage f = 0.1 to 10 Hz 25°C 1.5 µV In Equivalent input noise current 25°C 0.6 fA/√Hz VO = 0.5 V to 2.5 V, f1 0 k H AV = 1 25°C 0.02% THD + N Total harmonic distortion plus noisef = 10 kHz, R L = 1 kΩ , AV = 10 25°C 0.08%R L 1 kΩ , C L = 100 pF AV = 100 25°C 0.55% Gain-bandwidth product f = 10 kHz, C L = 100 pF R L = 1 kΩ , 25°C 4.7 MHz BOM Maximum output swing bandwidth VO(PP) = 2 V, R L = 1 kΩ , AV = 1, C L = 100 pF 25°C 1 MHz t Settling time AV = –1, Step = 0.5 V to 2.5 V,to 0.1% 25°C 1.6 µsts Settling time R L = 1 kΩ , C L = 100 pF to 0.01% 25°C 2.2 µs φm Phase margin at unity gain R L = 1 kΩ , C L = 100 pF 25°C 74 Calibration time 25°C 300 ms † Full range is 0°C to 70°C. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V, GND = 0 (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC450xI UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT TLC4501 –80 10 80 VIO Input offset voltage VDD = ± 2.5 V, VO = 0, TLC4501A Full range –40 10 40 µVVIO Input offset voltage DD , VIC = 0, O , R S = 50 Ω TLC4502 Full range –100 10 100 µV TLC4502A –50 10 50 α VIO Temperature coefficient of input Full range 1 µV/°Cα VIO offset voltage Full range 1 µV/°C VDD = ± 2.5 V, VO = 0, 25°C 1 60 IIO Input offset current DD VIC = 0, O R S = 50 Ω –40°C to 85°C 500 pA Full range 5 nA 25°C 1 60 IIB Input bias current VDD = ± 2.5 V, VIC = 0, VO = 0, R S = 50 Ω –40°C to 85°C 500 pA Full range 10 nA IOH = – 500 µA 25°C 4.99 VOH High-level output voltage IOH = 5m A 25°C 4.9 V IOH = – 5 mA Full range 4.7 VIC = 2.5 V, IOL = 500 µA 25°C 0.01 VOL Low-level output voltage VIC =25V IOL =5m A 25°C 0.1 V VIC = 2.5 V, IOL = 5 mA Full range 0.3 AVD Large-signal differential voltage VIC = 2.5 V, VO = 1 V to 4 V, 25°C 200 1000 V/mVAVD gg g amplification IC , R L = 1 kΩ , O , See Note 4 Full range 200 V/mV R I(D) Differential input resistance 25°C 10 kΩ R L Input resistance See Note 4 25°C 1012 Ω C L Common-mode input capacitance f = 10 kHz, P package 25°C 8 pF zO Closed-loop output impedance AV = 10, f = 100 kHz 25°C 1 Ω CMRR Common mode rejection ratio VIC = 0 to 2.7 V, VO = 2.5 V, 25°C 90 100 dBCMRR Common -mode rejection ratio IC , O , R S = 1 kΩ Full range 85 dB kSVR Supply-voltage rejection ratio VDD =4Vt o6V V IC = 0 No load 25°C 90 100 dBkSVR yg j (∆VDD ± /∆VIO) VDD = 4 V to 6 V, VIC = 0, No load Full range 90 dB TLC4501/A 25°C 1 1.5 IDD Supply current VO =25V No load TLC4501/A Full range 2 mAIDD Supply current VO = 2.5 V, No load TLC4502/A 25°C 2.5 3.5 mA TLC4502/A Full range 4 VIT(CAL) Calibration input threshold voltage Full range 4 VVIT(CAL) Calibration input threshold voltage Full range 4 V † Full range is –40°C to 125°C. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, VDD = 5 V PARAMETER TEST CONDITIONS T † TLC450xI, TLC450xAI UNITPARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR Slew rate at unity gain VO =05Vt o25V C L = 100pF 25°C 1.5 2.5 V/µs SR Slew rate at unity gain VO = 0.5 V to 2.5 V, C L = 100 pF Full range 1 V/µs V Equivalent input noise voltage f = 10 Hz 25°C 70 nV/√HVn Equivalent input noise voltage f = 1 kHz 25°C 12 nV/√H z VN(PP) Peak-to-peak equivalent input noisef = 0.1 to 1 Hz 25°C 1 µVVN(PP) q voltage f = 0.1 to 10 Hz 25°C 1.5 µV In Equivalent input noise current 25°C 0.6 fA/√Hz VO = 0.5 V to 2.5 V, f1 0 k H AV = 1 25°C 0.02% THD + N Total harmonic distortion plus noisef = 10 kHz, R L = 1 kΩ , AV = 10 25°C 0.08%R L 1 kΩ , C L = 100 pF AV = 100 25°C 0.55% Gain-bandwidth product f = 10 kHz, C L = 100 pF R L = 1 kΩ , 25°C 4.7 MHz BOM Maximum output swing bandwidth VO(PP) = 2 V, R L = 1 kΩ , AV = 1, C L = 100 pF 25°C 1 MHz t Settling time AV = –1, Step = 0.5 V to 2.5 V,to 0.1% 25°C 1.6 µsts Settling time R L = 1 kΩ , C L = 100 pF to 0.01% 25°C 2.2 µs φm Phase margin at unity gain R L = 1 kΩ , C L = 100 pF 25°C 74 Calibration time 25°C 300 ms † Full range is –40°C to 125°C. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V, GND = 0 (unless otherwise noted) PARAMETER TEST CONDITIONS TA † TLC4502Q, TLC4502M UNITA MIN TYP MAX VIO Input offset voltage VDD = ± 2.5 V, VO = 0, TLC4502 Full range –100 10 100 µVVIO Input offset voltage DD , VIC = 0, O , R S = 50 Ω TLC4502A Full range –50 10 50 µV α VIO Temperature coefficient of input Full range 1 µV/°Cα VIO offset voltage Full range 1 µV/°C IIO Input offset current VDD = ± 2.5 V, VO = 0, 25°C 1 60 nAIIO Input offset current VDD ± 2.5 V, VIC = 0, VO 0, R S = 50 Ω 125°C 5 nA IIB Input bias current 25°C 1 60 nAIIB Input bias current 125°C 10 nA IOH = – 500 µA 25°C 4.99 VOH High-level output voltage IOH = 5m A 25°C 4.9 V IOH = – 5 mA Full range 4.7 VIC = 2.5 V, IOL = 500 µA 25°C 0.01 VOL Low-level output voltage VIC =25V IOL =5m A 25°C 0.1 V VIC = 2.5 V, IOL = 5 mA Full range 0.3 AVD Large-signal differential voltage VIC = 2.5 V, VO = 1 V to 4 V, 25°C 200 1000 V/mVAVD gg g amplification IC , R L = 1 kΩ , O , See Note 4 Full range 200 V/mV R I(D) Differential input resistance 25°C 10 kΩ R L Input resistance See Note 4 25°C 1012 Ω C L Common-mode input capacitance f = 10 kHz, P package 25°C 8 pF zO Closed-loop output impedance AV = 10, f = 100 kHz 25°C 1 Ω CMRR Common mode rejection ratio VIC = 0 to 2.7 V, VO = 2.5 V, 25°C 90 100 dBCMRR Common -mode rejection ratio IC , O , R S = 1 kΩ Full range 85 dB kSVR Supply-voltage rejection ratio VDD = 4 V to 6 V, VIC = VDD /2, 25°C 90 100 dBkSVR yg j (∆VDD ± /∆VIO) DD , IC DD , No load Full range 90 dB IDD Supply current VO =25V No load 25°C 2.5 3.5 mAIDD Supply current VO = 2.5 V, No load Full range 4 mA VIT(CAL) Calibration input threshold voltage Full range 4 VVIT(CAL) Calibration input threshold voltage Full range 4 V † Full range is –40°C to 125°C for Q suffix, –55°C to 125°C for M suffix. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics, VDD = 5 V PARAMETER TEST CONDITIONS TA † TLC4502Q, TLC4502M, TLC4502AQ, TLC4502AM UNIT MIN TYP MAX SR Slew rate at unity gain VO = 0.5 V to 2.5 V,C L = 100 pF 25°C 1.5 2.5 V/µs SR Slew rate at unity gain O , See Note 4 L Full range 1 V/µs V Equivalent input noise voltage f = 10 Hz 25°C 70 nV/√HVn Equivalent input noise voltage f = 1 kHz 25°C 12 nV/√H z VN(PP) Peak-to-peak equivalent input noisef = 0.1 to 1 Hz 25°C 1 µVVN(PP) q voltage f = 0.1 to 10 Hz 25°C 1.5 µV In Equivalent input noise current 25°C 0.6 fA/√Hz VO = 0.5 V to 2.5 V, f1 0 k H AV = 1 25°C 0.02% THD + N Total harmonic distortion plus noisef = 10 kHz, R L = 1 kΩ , AV = 10 25°C 0.08%R L 1 kΩ , C L = 100 pF AV = 100 25°C 0.55% Gain-bandwidth product f = 10 kHz, C L = 100 pF R L = 1 kΩ , 25°C 4.7 MHz BOM Maximum output swing bandwidth VO(PP) = 2 V, R L = 1 kΩ , AV = 1, C L = 100 pF 25°C 1 MHz t Settling time AV = –1, Step = 0.5 V to 2.5 V,to 0.1% 25°C 1.6 µsts Settling time R L = 1 kΩ , C L = 100 pF to 0.01% 25°C 2.2 µs φm Phase margin at unity gain R L = 1 kΩ , C L = 100 pF 25°C 74 Calibration time 25°C 300 ms † Full range is –40°C to 125°C for Q suffix, –55°C to 125°C for M suffix. NOTE 4: R L and CL values are referenced to 2.5 V.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Distribution 2, 3, 4 VIO Input offset voltage vs Common-mode input voltage 5 α VIO Input offset voltage temperature coefficientDistribution 6, 7 VOH High-level output voltage vs High-level output current 8 VOL Low-level output voltage vs Low-level output current 9 VO(PP) Maximum peak-to-peak output voltage vs Frequency 10 IOS Short-circuit output current vs Free-air temperature 11 VO Output voltage vs Differential input voltage 12 AVD Large signal differential voltage amplificationvs Free-air temperature 13AVD Large-signal differential voltage amplificationvs Frequency 14 zo Output impedance vs Frequency 15 CMRR Common mode rejection ratio vs Frequency 16CMRR Common -mode rejection ratio qy vs Free-air temperature 17 SR Slew rate vs Load capacitance 18SR Slew rate vs Free-air temperature 19 Inverting large-signal pulse response 20 Voltage-follower large-signal pulse response 21 Inverting small-signal pulse response 22 Voltage-follower small-signal pulse response 23 Vn Equivalent input noise voltage vs Frequency 24 Input noise voltage Over a 10-second period 25 THD + N Total harmonic distortion plus noise vs Frequency 26 Gain-bandwidth product vs Free-air temperature 27 φ Phase margin vs Load capacitance 28 φm Phase margin vs Frequency 14 Gain margin vs Load capacitance 29 PSRR Power-supply rejection ratio vs Free-air temperature 30 Calibration time at –40°C 31 Calibration time at 25°C 32 Calibration time at 85°C 33 Calibration time at 125°C 34

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS DISTRIBUTION OF TLC4502 INPUT OFFSET VOLTAGE –40 –30 –20 –10 Percentage Of Amplification – % VIO – Input Offset Voltage – µV

339 Amplifier From 2 Wafer Lot

VDD =± 2.5 V TA = 40°C Figure 2 –60 –50 –40 –30 –20 –10

486 Amplifier From 8 Wafer Lot

VDD =± 2.5 V TA = 25°C VIO – Input Offset Voltage – µV Percentage of Amplifiers – % DISTRIBUTION OF TLC4502 INPUT OFFSET VOLTAGE Figure 3 Percentage Of Amplification – % DISTRIBUTION OF TLC4502 INPUT OFFSET VOLTAGE –50 –40 –30 –20 –10 VIO – Input Offset Voltage – µV

296 Amplifier From 2 Wafer Lot

VDD =± 2.5 V TA = 85°C Figure 4 Figure 5 –50 –150 –200 –3 –2 –10 – Input Offset Voltage – 150 INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 200 123 100 –100 VIC – Common-Mode Input Voltage – v VIO Vµ VDD = ± 2.5 V R S = 50 Ω TA = 25°C

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

α VIO – Temperature Coefficient – µV/°C

30 Amplifiers From 1 Wafer Lot

VDD =± 2.5 V TA = 25°C To –40°C –3 –20 1 Percentage Of Amplifiers – % DISTRIBUTION OF TLC4502 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT 23–1 Figure 7

30 Amplifiers From

1 Wafer Lot

VDD =± 2.5 V TA = 25°C To 85°C Percentage Of Amplifiers – % DISTRIBUTION OF TLC4502 INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 α VIO – Temperature Coefficient – µV/°C Figure 8 IOH – High-Level Output Current – mA 0.5 01 0 2 03 04 0 3.5 4.5 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 50 60 70 80 2.5 VDD = 5 V VIC = 2.5 V 1.5 TA = –40°C TA = 25°C VOH – High-Level Output Voltage – V ÁÁ ÁÁ VOH TA = 125°C TA = 85°C Figure 9 IOL – Low-Level Output Current – mA 0.75 0.25 01 02 03 0 4 05 0 – Low-Level Output Voltage – V 1.5 1.75 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 60 70 80 0.5 1.25 VOL VDD = 5 V VIC = 2.5 V TA = –40°C TA = 25°C TA = 85°C TA = 125°C

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VDD = 5 V R L = 1 kΩ C L = 100 pF TA = 25°C –20 –40 1 k f – Frequency – Hz LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE MARGIN vs FREQUENCY 10 k 100 k 1 M 10 M 100 M Phase Margin 180° 135° 90° 45° –45° –90° – Large-Signal DifferentialA VD Voltage Amplification – dB Figure 14 0.1 0.001 1000 100 – Output Impedance – 100 f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 0.01 1 k 10 k 100 k 1 M zO Ω AV = 1 AV = 100 AV = 10 Figure 15

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t – Time – µs 2.5 0.5 0 25 50 75 100 125 INVERTING LARGE-SIGNAL PULSE RESPONSE 4.5 150 175 200 3.5 1.5 VDD = 5 V R L = 1 kΩ C L = 100 pF AV = –1 TA = 25°C – Output Voltage – VVO Figure 21 t – Time – µs 2.5 0.5 0 25 50 75 100 125 3.5 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE 4.5 150 175 200

1.5 VDD = 5 V

R L = 1 kΩ C L = 100 pF AV = 1 TA = 25°C – Output Voltage – VVO Figure 22 t – Time – µs 2.5 2.49 2.48 2.47 0 20 40 60 80 100 120 2.505 2.515 INVERTING SMALL-SIGNAL PULSE RESPONSE 2.525 140 160 180 200 2.52 2.51 2.495 2.485 2.475 VDD = 5 V R L = 1 kΩ C L = 100 pF AV = –1 TA 25°C – Output Voltage – VVO Figure 23 t – Time – µs 2.5 2.49 2.48 2.47 0 50 100 150 2.51 2.52 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE 2.53 200 250 VDD = 5 V R L = 1 kΩ C L = 100 pF AV = 1 TA = 25°C – Output Voltage – VVO

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

R null = 50 Ω R null = 20 Ω R null = 0 Phase Margin PHASE MARGIN vs LOAD CAPACITANCE 100 1 k 10 k 100 k C L – Load Capacitance – pF 50 kΩ 50 kΩ VDD – VDD + R null C L VI + Figure 29 R null = 50 Ω R null = 20 Ω R null = 0 TA 25°C Gain Margin – dB GAIN MARGIN vs LOAD CAPACITANCE 100 1 k 10 k 100 k C L – Load Capacitance – pF Figure 30 TA – Free-Air Temperature – °C 115 110 105 100 –50 –25 0 25 50 PSRR – Power Supply Rejection Ratio – dB 120 125 POWER SUPPLY REJECTION RATIO vs FREE-AIR TEMPERATURE 130 75 100 125 VDD = 4 V To 6 V VIC = VO = VDD /2 Figure 31 –1.5 0 100 200 300 400 500 600 –0.5 t – Time – ms CALIBRATION TIME AT –40°C 0.5 700 800 900 1000 –2.5 – Output Voltage – VVO VDD = 2.5 V GND = –2.5 V R L = 1 kΩ to GND AV = –1 VI = 0

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

/C0068 The TLC4502 is designed to operate with only a single 5-V power supply, have true differential inputs, and remain in the linear mode with an input common-mode voltage of 0. /C0068 The TLC4502 has a standard dual-amplifier pinout, allowing for easy design upgrades. /C0068 Large differential input voltages can be easily accommodated and, as input differential-voltage protection diodes are not needed, no large input currents result from large differential input voltage. Protection should be provided to prevent the input voltages from going negative more than –0.3 V at 25°C. An input clamp diode with a resistor to the device input terminal can be used for this purpose. /C0068 For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor can be used from the output of the amplifier to ground. This increases the class-A bias current and prevents crossover distortion. Where the load is directly coupled, for example in dc applications, there is no crossover distortion. /C0068 Capacitive loads, which are applied directly to the output of the amplifier, reduce the loop stability margin. Values of 500 pF can be accommodated using the worst-case noninverting unity-gain connection. Resistive isolation should be considered when larger load capacitance must be driven by the amplifier. The following typical application circuits emphasize operation on only a single power supply. When complementary power supplies are available, the TLC4502 can be used in all of the standard operational amplifier circuits. In general, introducing a pseudo-ground (a bias voltage of V I/2 like that generated by the TLE2426) allows operation above and below this value in a single-supply system. Many application circuits shown take advantage of the wide common-mode input-voltage range of the TLC4502, which includes ground. In most cases, input biasing is not required and input voltages that range to ground can easily be accommodated. description of calibration procedure To achieve high dc gain, large bandwidth, high CMRR and PSRR, as well as good output drive capability, the TLC4502 is built around a 3-stage topology: two gain stages, one rail-to-rail, and a class-AB output stage. A nested Miller topology is used for frequency compensation. During the calibration procedure, the operational amplifier is removed from the signal path and both inputs are tied to GND. Figure 35 shows a block diagram of the amplifier during calibration mode.

Figure 35. Block Diagram During Calibration Mode still in place, it is detected in less than 1 µs and the device is shut down for another 5 ms. current is stored in the successive-approximation register (SAR). to reduce supply current and the associated noise.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The key operational-amplifier parameters CMRR, PSRR, and offset drift were optimized to achieve superior offset performance. The TLC4502 calibration DAC is implemented by a binary-weighted current array using a pseudo-R-2R MOSFET ladder architecture, which minimizes the silicon area required for the calibration circuitry, and thereby reduces the cost of the TLC4502. Due to the performance (precision, PSRR, CMRR, gain, output drive, and ac performance) of the TLC4502, it is ideal for applications like: /C0068 Data acquisition systems /C0068 Medical equipment /C0068 Portable digital scales /C0068 Strain gauges /C0068 Automotive sensors /C0068 Digital audio circuits /C0068 Industrial control applications It is also ideal in circuits like: /C0068 A precision buffer for current-to-voltage converters, a/d buffers, or bridge applications /C0068 High-impedance buffers or preamplifiers /C0068 Long term integration /C0068 Sample-and-hold circuits /C0068 Peak detectors The TLC4502 self-calibrating operational amplifier is manufactured using Texas instruments LinEPIC process technology and is available in an 8-pin SOIC (D) Package. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from –40°C to 125°C. The M-suffix devices are characterized for operation from –55°C to 125°C.

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V(REF) V O /C0043 V I/C0466R5 R3 /C0467/C04662R1 R G /C0041 1/C0467/C0041 V (REF) R G Where : R1 /C0043 R2, R3 /C0043 R4, and R5 /C0043 R6 TLC4502 TLC4502 TLC4502 VO Figure 38. Three Operational-Amplifier Instrumentation Amplifier Circuit Figure 39. Fixed Current-Source Circuit

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 43. High-Compliance Current-Sink Circuit

1 VOR1

Figure 44. Comparator With Hysteresis Circuit Figure 45. Low-Drift Detector Circuit

TLC4501, TLC4501A, TLC4502, TLC4502A FAMILY OF SELF-CALIBRATING (Self-Cal ) PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS SLOS221B – MAY 1998 – REVISED APRIL 2001 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Macromodel information provided was derived using MicrosimParts Release 8, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 46 are generated using the TLC4501 typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068 Maximum positive output voltage swing /C0068 Maximum negative output voltage swing /C0068 Slew rate /C0068 Quiescent power dissipation /C0068 Input bias current /C0068 Open-loop voltage amplification /C0068 Unity-gain frequency /C0068 Common-mode rejection ratio /C0068 Phase margin /C0068 DC output resistance /C0068 AC output resistance /C0068 Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). – + .subckt TLC4501 1 2 3 4 5 c1 11 12 1.4559E –12 c2 6 7 8.0000E –12 css 10 99 1.0000E –30 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx fb 7 99 poly(5) vb vc ve vlp vln 0 + 84.657E9 –1E3 1E3 85E9 –85E9 ga 6 0 11 12 236.25E –6 gcm 0 6 10 99 2.3625E –9 iss 10 4 dc 20.000E –6 hlim 90 0 vlim 1K j1 11 2 10 jx1 j2 12 1 10 jx2 r2 6 9 100.00E3 rd1 3 11 4.2328E3 rd2 3 12 4.2328E3 ro1 8 5 5.0000E –3 ro2 7 99 5.0000E –3 rp 3 4 5.0000E3 rss 10 99 10.000E6 vb 9 0 dc 0 vc 3 53 dc .92918 ve 54 4 dc .82918 vlim 7 8 dc 0 vlp 91 0 dc 67 vln 0 92 dc 67 .model dx D(Is=800.00E–18) .model dy D(Is=800.00E–18 Rs=1m Cjo=10p) .model jx1 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1) .model jx2 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1) .ends VDD+ RP IN – IN+ VDD – RD1 J1 J2 RSSISS RD2 DP VD DC EGND FB HLIM DLP DLN VLNVLP CSS VE DE OUT R2 6 VB GA VLIM RO1 RO2 GCM Figure 46. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation.

www.ti.com 17-Dec-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 5962-9753701QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9753701QPA TLC4502M 5962-9753702QHA ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9753702QHA TLC4502AM 5962-9753702QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9753702QPA TLC4502AM TLC4501ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501AC TLC4501AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501AI TLC4501AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501AI TLC4501AQD PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4501AQDR PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4501CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501C TLC4501CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501C TLC4501ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501I TLC4501IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501I TLC4501IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501I TLC4501IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4501I TLC4501QD PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4501QDR PREVIEW SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4502ACD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AC TLC4502ACDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AC TLC4502ACDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AC

www.ti.com 17-Dec-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC4502ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AC TLC4502AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AI TLC4502AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AI TLC4502AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502AI TLC4502AMD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 4502AM TLC4502AMJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9753702QPA TLC4502AM TLC4502AMUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 9753702QHA TLC4502AM TLC4502AQD OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4502AQDR OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 TLC4502CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502C TLC4502CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502C TLC4502CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502C TLC4502CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502C TLC4502ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502I TLC4502IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502I TLC4502IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502I TLC4502IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502I TLC4502MD OBSOLETE SOIC D 8 TBD Call TI Call TI -55 to 125 TLC4502MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 4502M

www.ti.com 17-Dec-2015 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC4502MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9753701QPA TLC4502M TLC4502QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C4502Q TLC4502QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM C4502Q TLC4502QDR OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 17-Dec-2015 Addendum-Page 4 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC4502, TLC4502A, TLC4502AM, TLC4502M :

• Catalog: TLC4502A , TLC4502
• Military: TLC4502M , TLC4502AM NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC4501AIDR SOIC D 8 2500 367.0 367.0 38.0 TLC4501IDR SOIC D 8 2500 367.0 367.0 38.0 TLC4502ACDR SOIC D 8 2500 367.0 367.0 38.0 TLC4502AIDR SOIC D 8 2500 367.0 367.0 38.0 TLC4502CDR SOIC D 8 2500 367.0 367.0 38.0 TLC4502IDR SOIC D 8 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2

MCER001A – JANUARY 1995 – REVISED JANUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) Seating Plane 4040107/C 08/96 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) MAX 0.130 (3,30) MIN 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0°–15° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

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