TLC070IDR

TLC070 TI | Alldatasheet

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Technical content

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 1WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Wide Bandwidth . . . 10 MHz /C0068High Output Drive − IOH . . . 57 mA at VDD − 1.5 V − IOL . . . 55 mA at 0.5 V /C0068High Slew Rate − SR+ . . . 16 V/µs − SR− . . . 19 V/µs /C0068Wide Supply Range . . . 4.5 V to 16 V /C0068Supply Current. . . 1.9 mA/Channel /C0068Ultralow Power Shutdown Mode IDD . . . 125 µA/Channel /C0068Low Input Noise Voltage...7 n V√Hz /C0068Input Offset Voltage...6 0 µV /C0068Ultra-Small Packages − 8 or 10 Pin MSOP (TLC070/1/2/3)

description

The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC07x. The BiMOS family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to single-supply systems and demand higher AC and dc performance. With performance rated from 4.5 V to 16 V across commercial (0°C to 70°C) and an extended industrial temperature range (−40°C to 125°C), BiMOS suits a wide range of audio, automotive, industrial and instrumentation applications. Familiar features like offset nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels of performance in a variety of applications. Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input impedance low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum performance features of both. AC performance improvements over the TL07x BiFET predecessors include a bandwidth of 10 MHz (an increase of 300%) and voltage noise of 7 nV/√Hz (an improvement of 60%). DC improvements include a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum) in the standard grade, and a power supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of impressive features is the ability to drive ±50-mA loads comfortably from an ultrasmall-footprint MSOP PowerPAD package, which positions the TLC07x as the ideal high-performance general-purpose operational amplifier family. FAMILY PACKAGE TABLE DEVICE NO. OF PACKAGE TYPES SHUTDOWN UNIVERSALDEVICE NO. OF CHANNELS MSOP PDIP SOIC TSSOP SHUTDOWN UNIVERSAL EVM BOARD TLC070 1 8 8 8 — Yes TLC071 1 8 8 8 — Refer to the EVMTLC072 2 8 8 8 — — Refer to the EVM Selection Guide TLC073 2 10 14 14 — Yes Selection Guide (Lit# SLOU060) TLC074 4 — 14 14 20 — (Lit# SLOU060) TLC075 4 — 16 16 20 Yes Copyright  2000−2006, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Operational Amplifier PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 2 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TLC070 and TLC071 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE SMALL OUTLINE † SYMBOL PLASTIC DIPTA SMALL OUTLINE (D)† SMALL OUTLINE (DGN)† SYMBOL PLASTIC DIP (P) 0°C to 70°C TLC070CD TLC071CD TLC070CDGN TLC071CDGN xxTIACS xxTIACU TLC070CP TLC071CP −40°C to 125°C TLC070ID TLC071ID TLC070IDGN TLC071IDGN xxTIACT xxTIACV TLC070IP TLC071IP −40°C to 125°C TLC070AID TLC071AID TLC070AIP TLC071AIP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC070CDR). TLC072 and TLC073 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE MSOP PLASTIC DIP PLASTIC DIPTA OUTLINE (D)† (DGN)† SYMBOL ‡ (DGQ) † SYMBOL ‡ DIP (N) DIP (P) 0°C to 70°C TLC072CD TLC073CD TLC072CDGN xxTIADV TLC073CDGQ xxTIADX TLC073CN TLC072CP −40°C to 125°C TLC072ID TLC073ID TLC072IDGN xxTIADW TLC073IDGQ xxTIADY TLC073IN TLC072IP −40°C to 125°C TLC072AID TLC073AID TLC073AIN TLC072AIP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC072CDR). ‡ xx represents the device date code. TLC074 and TLC075 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE (D)† PLASTIC DIP (N) TSSOP (PWP) † 0°C to 70°C TLC074CD TLC075CD TLC074CN TLC075CN TLC074CPWP TLC075CPWP −40°C to 125°C TLC074ID TLC075ID TLC074IN TLC075IN TLC074IPWP TLC075IPWP −40°C to 125°C TLC074AID TLC075AID TLC074AIN TLC075AIN TLC074AIPWP TLC075AIPWP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC074CDR).

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 3WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TLC07x PACKAGE PIN OUTS NC − No internal connection NULL IN− IN+ GND SHDN VDD OUT NULL TLC070 D, DGN OR P PACKAGE (TOP VIEW) NULL IN− IN+ GND NC VDD OUT NULL TLC071 D, DGN OR P PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ GND NC 1SHDN NC VDD 2OUT 2IN− 2IN+ NC 2SHDN NC (TOP VIEW) 1OUT 1IN− 1IN+ GND VDD 2OUT 2IN− 2IN+ TLC072 D, DGN, OR P PACKAGE (TOP VIEW) TLC073 D OR N PACKAGE 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 1/2SHDN 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT 3/4SHDN (TOP VIEW) TLC075 D OR N PACKAGE 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT (TOP VIEW) TLC074 D OR N PACKAGE 1OUT 1IN− 1IN+ GND 1SHDN VDD 2OUT 2IN− 2IN+ 2SHDN TLC073 DGQ PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 1/2SHDN NC NC 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT 3/4SHDN NC NC (TOP VIEW) TLC075 PWP PACKAGE (TOP VIEW) TLC074 PWP PACKAGE 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT NC NC NC 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT NC NC NC TYPICAL PIN 1 INDICATORS Printed or Molded Dot Bevel Edges Pin 1 Molded ”U” Shape Pin 1 Stripe Pin 1 Pin 1

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 4 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. DISSIPATION RATING TABLE PACKAGE θJC (°C/W) θJA (°C/W) TA ≤ 25°C POWER RATING D (8) 38.3 176 710 mW D (14) 26.9 122.3 1022 mW D (16) 25.7 114.7 1090 mW DGN (8) 4.7 52.7 2.37 W DGQ (10) 4.7 52.3 2.39 W N (14, 16) 32 78 1600 mW P (8) 41 104 1200 mW PWP (20) 1.40 26.1 4.79 W recommended operating conditions MIN MAX UNIT Supply voltage, VDD Single supply 4.5 16 VSupply voltage, VDD Split supply ±2.25 ±8 V Common-mode input voltage, VICR +0.5 VDD −0.8 V Shutdown on/off voltage level‡ VIH 2 VShutdown on/off voltage level‡ VOL 0.8 V Operating free-air temperature, TA C-suffix 0 70 °COperating free-air temperature, TA I-suffix −40 125 ‡ Relative to the voltage on the GND terminal of the device.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 5WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT TLC070/1/2/3, 25°C 390 1900 VIO Input offset voltage VDD = 5 V, TLC070/1/2/3, TLC074/5 Full range 3000 VVIO Input offset voltage VDD = 5 V, VIC = 2.5 V, TLC070/1/2/3A, 25°C 390 1400 µV VIC = 2.5 V, VO = 2.5 V, R S = 50 Ω TLC070/1/2/3A, TLC074/5A Full range 2000 VIO Temperature coefficient of input O R S = 50 Ω

1.2 V/°CαVIO

Temperature coefficient of input offset voltage 1.2 µV/°C 25°C 0.7 50 IIO Input offset current VDD = 5 V, TLC07XC Full range 100 pAIIO Input offset current VDD = 5 V, VIC = 2.5 V, TLC07XI Full range 700 pA VIC = 2.5 V, VO = 2.5 V, R = 50 Ω 25°C 1.5 50 IIB Input bias current VO = 2.5 V, R S = 50 Ω TLC07XC Full range 100 pAIIB Input bias current TLC07XI Full range 700 pA VICR Common-mode input voltage R S = 50 Ω 25°C 0.5 to 4.2 VVICR Common-mode input voltage R S = 50 Ω Full range 0.5 to 4.2 V IOH = −1 mA 25°C 4.1 4.3 IOH = −1 mA Full range 3.9 IOH = −20 mA 25°C 3.7 4 IOH = −20 mA Full range 3.5 VOH High-level output voltage V IC = 2.5 V IOH = −35 mA 25°C 3.4 3.8 VVOH High-level output voltage VIC = 2.5 V IOH = −35 mA Full range 3.2 V 25°C 3.2 3.6 IOH = −50 mA −40°C to 85°C 3 IOL = 1 mA 25°C 0.18 0.25 IOL = 1 mA Full range 0.35 IOL = 20 mA 25°C 0.35 0.39 IOL = 20 mA Full range 0.45 VOL Low-level output voltage V IC = 2.5 V IOL = 35 mA 25°C 0.43 0.55 VVOL Low-level output voltage VIC = 2.5 V IOL = 35 mA Full range 0.7 V 25°C 0.48 0.63 IOL = 50 mA −40°C to 85°C 0.7 IOS Short-circuit output current Sourcing 25°C 100 mAIOS Short-circuit output currentSinking 25°C 100 mA IO Output current VOH = 1.5 V from positive rail 25°C 57 mAIO Output current VOL = 0.5 V from negative rail 25°C 55 mA † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 6 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT AVD Large-signal differential voltageVO(PP) = 3 V, R L = 10 kΩ 25°C 100 120 dBAVD Large-signal differential voltage amplification VO(PP) = 3 V, R L = 10 kΩ Full range 100 dB ri(d) Differential input resistance 25°C 1000 G Ω C IC Common-mode input capacitance f = 10 kHz 25°C 22.9 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω CMRR Common-mode rejection ratio VIC = 1 to 3 V, R S = 50Ω 25°C 80 95 dBCMRR Common-mode rejection ratio V IC = 1 to 3 V, R S = 50Ω Full range 80 dB kSVR Supply voltage rejection ratioVDD = 4.5 V to 16 V,VIC = VDD /2, 25°C 80 100 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.5 V to 16 V, No load VIC = VDD /2, Full range 80 dB IDD Supply current (per channel) VO = 2.5 V, No load 25°C 1.9 2.5 mAIDD Supply current (per channel) VO = 2.5 V, No load Full range 3.5 mA IDD(SHDN) Supply current in shutdown mode (per channel) SHDN ≤ 0.8 V 25°C 125 200 AIDD(SHDN ) mode (per channel) (TLC070, TLC073, TLC075) SHDN ≤ 0.8 V Full range 250 µA † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 7WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR+ Positive slew rate at unity gainVO(PP) = 0.8 V, C L = 50 pF, 25°C 10 16 V/ sSR+ Positive slew rate at unity gainVO(PP) = 0.8 V, R L = 10 kΩ C L = 50 pF, Full range 9.5 V/µs SR− Negative slew rate at unity gainVO(PP) = 0.8 V, C L = 50 pF, 25°C 12.5 19 V/ sSR− Negative slew rate at unity gainVO(PP) = 0.8 V, R L = 10 kΩ C L = 50 pF, Full range 10 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 12 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 7 nV/√Hz In Equivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz VO(PP) = 3 V, AV = 1 0.002% THD + N Total harmonic distortion plus noise VO(PP) = 3 V, R L = 10 kΩ and 250 Ω, f = 1 kHz AV = 10 25°C 0.012%THD + N Total harmonic distortion plus noiseR L = 10 kΩ and 250 Ω, f = 1 kHz AV = 100 25 C 0.085% t(on) Amplifier turn-on time‡ R L = 10 kΩ 25°C 0.15 µs t(off) Amplifier turn-off time‡ R L = 10 kΩ 25°C 1.3 µs Gain-bandwidth product f = 10 kHz, R L = 10 kΩ 25°C 10 MHz V(STEP)PP = 1 V, AV = −1, 0.1% 0.18 ts Settling time AV = −1, C L = 10 pF, R L = 10 kΩ 0.01% 25°C 0.39 sts Settling time V(STEP)PP = 1 V, AV = −1, 0.1% 25°C 0.18 µs AV = −1, C L = 47 pF, R L = 10 kΩ 0.01% 0.39 φm Phase margin R L = 10 kΩ, C L = 50 pF 25°C 32° φm Phase margin R L = 10 kΩ, C L = 0 pF 25°C 40° Gain margin R L = 10 kΩ, C L = 50 pF 25°C 2.2 dBGain margin R L = 10 kΩ, C L = 0 pF 25°C 3.3 dB † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 8 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT TLC070/1/2/3, 25°C 390 1900 VIO Input offset voltage VDD = 12 V TLC070/1/2/3, TLC074/5 Full range 3000 VVIO Input offset voltage VDD = 12 V VIC = 6 V, TLC070/1/2/3A, 25°C 390 1400 µV VIC = 6 V, VO = 6 V, R S = 50 Ω TLC070/1/2/3A, TLC074/5A Full range 2000 VIO Temperature coefficient of input O R S = 50 Ω Temperature coefficient of input offset voltage 1.2 µV/°C 25°C 0.7 50 IIO Input offset current VDD = 12 V TLC07xC Full range 100 pAIIO Input offset current VDD = 12 V VIC = 6 V, TLC07xI Full range 700 pA VIC = 6 V, VO = 6 V, R = 50 Ω 25°C 1.5 50 IIB Input bias current VO = 6 V, R S = 50 Ω TLC07xC Full range 100 pAIIB Input bias current TLC07xI Full range 700 pA VICR Common-mode input voltage R S = 50 Ω 25°C 0.5 to 11.2 VVICR Common-mode input voltage R S = 50 Ω Full range 0.5 to 11.2 V IOH = −1 mA 25°C 11.1 11.2 IOH = −1 mA Full range 11 IOH = −20 mA 25°C 10.8 10.9 IOH = −20 mA Full range 10.7 VOH High-level output voltage V IC = 6 V IOH = −35 mA 25°C 10.6 10.7 VVOH High-level output voltage VIC = 6 V IOH = −35 mA Full range 10.3 V 25°C 10.4 10.5 IOH = −50 mA −40°C to 85°C 10.3 IOL = 1 mA 25°C 0.17 0.25 IOL = 1 mA Full range 0.35 IOL = 20 mA 25°C 0.35 0.45 IOL = 20 mA Full range 0.5 VOL Low-level output voltage V IC = 6 V IOL = 35 mA 25°C 0.4 0.52 VVOL Low-level output voltage VIC = 6 V IOL = 35 mA Full range 0.6 V 25°C 0.45 0.6 IOL = 50 mA −40°C to 85°C 0.65 IOS Short-circuit output current Sourcing 25°C 150 mAIOS Short-circuit output currentSinking 25°C 150 mA IO Output current VOH = 1.5 V from positive rail 25°C 57 mAIO Output current VOL = 0.5 V from negative rail 25°C 55 mA † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 9WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT AVD Large-signal differential voltageVO(PP) = 8 V, R L = 10 kΩ 25°C 120 140 dBAVD Large-signal differential voltage amplification VO(PP) = 8 V, R L = 10 kΩ Full range 120 dB ri(d) Differential input resistance 25°C 1000 G Ω C IC Common-mode input capacitance f = 10 kHz 25°C 21.6 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω CMRR Common-mode rejection ratio VIC = 1 to 10 V, R S = 50Ω 25°C 80 100 dBCMRR Common-mode rejection ratio V IC = 1 to 10 V, R S = 50Ω Full range 80 dB kSVR Supply voltage rejection ratioVDD = 4.5 V to 16 V,VIC = VDD /2, 25°C 80 100 dBkSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 4.5 V to 16 V, No load VIC = VDD /2, Full range 80 dB IDD Supply current (per channel) VO = 7.5 V, No load 25°C 2.1 2.9 mAIDD Supply current (per channel) VO = 7.5 V, No load Full range 3.5 mA IDD(SHDN) Supply current in shutdown mode (TLC070, TLC073, SHDN ≤ 0.8 V 25°C 125 200 AIDD(SHDN ) mode (TLC070, TLC073, TLC075) (per channel) SHDN ≤ 0.8 V Full range 250 µA † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 10 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 operating characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS TA † MIN TYP MAX UNIT SR+ Positive slew rate at unity gainVO(PP) = 2 V, C L = 50 pF, 25°C 10 16 V/ sSR+ Positive slew rate at unity gainVO(PP) = 2 V, R L = 10 kΩ C L = 50 pF, Full range 9.5 V/µs SR− Negative slew rate at unity gainVO(PP) = 2 V, C L = 50 pF, 25°C 12.5 19 V/ sSR− Negative slew rate at unity gainVO(PP) = 2 V, R L = 10 kΩ C L = 50 pF, Full range 10 V/µs Vn Equivalent input noise voltage f = 100 Hz 25°C 12 nV/√HzVn Equivalent input noise voltage f = 1 kHz 25°C 7 nV/√Hz In Equivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz VO(PP) = 8 V, AV = 1 0.002% THD + N Total harmonic distortion plus noise VO(PP) = 8 V, R L = 10 kΩ and 250 Ω, f = 1 kHz AV = 10 25°C 0.005%THD + N Total harmonic distortion plus noiseR L = 10 kΩ and 250 Ω, f = 1 kHz AV = 100 25 C 0.022% t(on) Amplifier turn-on time‡ R L = 10 kΩ 25°C 0.47 µs t(off) Amplifier turn-off time‡ R L = 10 kΩ 25°C 2.5 µs Gain-bandwidth product f = 10 kHz, R L = 10 kΩ 25°C 10 MHz V(STEP)PP = 1 V, AV = −1, 0.1% 0.17 ts Settling time AV = −1, C L = 10 pF, R L = 10 kΩ 0.01% 25°C 0.22 sts Settling time V(STEP)PP = 1 V, AV = −1, 0.1% 25°C 0.17 µs AV = −1, C L = 47 pF, R L = 10 kΩ 0.01% 0.29 φm Phase margin R L = 10 kΩ, C L = 50 pF 25°C 37° φm Phase margin R L = 10 kΩ, C L = 0 pF 25°C 42° Gain margin R L = 10 kΩ, C L = 50 pF 25°C 3.1 dBGain margin R L = 10 kΩ, C L = 0 pF 25°C dB † Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 11WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIO Input offset current vs Free-air temperature 3, 4 IIB Input bias current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 7 VOL Low-level output voltage vs Low-level output current 6, 8 Zo Output impedance vs Frequency 9 IDD Supply current vs Supply voltage 10 PSRR Power supply rejection ratio vs Frequency 11 CMRR Common-mode rejection ratio vs Frequency 12 Vn Equivalent input noise voltage vs Frequency 13 VO(PP) Peak-to-peak output voltage vs Frequency 14, 15 Crosstalk vs Frequency 16 Differential voltage gain vs Frequency 17, 18 Phase vs Frequency 17, 18 φm Phase margin vs Load capacitance 19, 20 Gain margin vs Load capacitance 21, 22 Gain-bandwidth product vs Supply voltage 23 SR Slew rate vs Supply voltage vs Free-air temperature 25, 26 THD + N Total harmonic distortion plus noise vs Frequency 27, 28 THD + N Total harmonic distortion plus noise vs Peak-to-peak output voltage 29, 30 Large-signal follower pulse response 31, 32 Small-signal follower pulse response 33 Large-signal inverting pulse response 34, 35 Small-signal inverting pulse response 36 Shutdown forward isolation vs Frequency 37, 38 Shutdown reverse isolation vs Frequency 39, 40 Shutdown supply current vs Supply voltage 41 Shutdown supply current vs Free-air temperature 42 Shutdown pulse 43, 44

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 15WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 TYPICAL CHARACTERISTICS Figure 25 −55 −35 −15 5 25 45 65 85 105 125 SLEW RATE vs FREE-AIR TEMPERATURE TA - Free-Air Temperature - °C VDD = 5 V R L = 600 Ω and 10 kΩ C L = 50 pF AV = 1 SR − Slew Rate − V/µ s Slew Rate + Slew Rate − Figure 26 −55 −35 −15 5 25 45 65 85 105 125 SLEW RATE vs FREE-AIR TEMPERATURE TA - Free-Air Temperature - °C VDD = 12 V R L = 600 Ω and 10 kΩ C L = 50 pF AV = 1 SR − Slew Rate − V/µ s Slew Rate + Slew Rate − Figure 27 TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 0.001 100 1k 0.01 0.1 10k 100k f − Frequency − Hz VDD = 5 V R L = 10 kΩ VO(PP) = 2 V AV = 100 AV = 10 AV = 1 Total Harmonic Distortion + Noise − % Figure 28 TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY Total Harmonic Distortion + Noise − % 0.001 100 1k 0.01 0.1 10k 100k f − Frequency − Hz AV = 100 VDD = 12 V R L = 10 kΩ VO(PP) = 12 V AV = 10 AV = 1 Figure 29 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE Total Harmonic Distortion + Noise − % 0.0001 0.25 0.75 0.01 0.1 1.25 1.75 VO(PP) − Peak-to-Peak Output Voltage − V 2.25 2.75 3.25 3.75 0.001

10 VDD = 5 V

AV = 1 f = 1 kHz R L = 250 Ω R L = 600 Ω R L = 10 kΩ Figure 30 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE Total Harmonic Distortion + Noise − % 0.0001 0.5 2.5 0.01 0.1 4.5 6.5 VO(PP) − Peak-to-Peak Output Voltage − V 8.5 10.5 0.001

10 VDD = 12 V

AV = 1 f = 1 kHz R L = 250 Ω R L = 600 Ω R L = 10 kΩ Figure 31 t − Time − µs LARGE SIGNAL FOLLOWER PULSE RESPONSE 1.4 1.6 1.8 2 − Output Voltage − VV O VI (1 V/Div) VO (500 mV/Div) VDD = 5 V R L = 600 Ω and 10 kΩ C L = 8 pF TA = 25°C Figure 32 t − Time − µs LARGE SIGNAL FOLLOWER PULSE RESPONSE 1.4 1.6 1.8 2 − Output Voltage − VV O VI (5 V/Div) VO (2 V/Div) VDD = 12 V R L = 600 Ω and 10 kΩ C L = 8 pF TA = 25°C Figure 33 SMALL SIGNAL FOLLOWER PULSE RESPONSE 0 0.1 0.3 0.4 t − Time − µs VO (50mV/Div) VI(100mV/Div) VDD = 5 V and 12 V R L = 600 Ω and 10 kΩ C L = 8 pF TA = 25°C − Output Voltage − VV O

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 19WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

high speed CMOS input amplifiers The TLC07x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of −10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance. This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their unity-gain bandwidth. However, the TLC07x with its 10-MHz bandwidth means that this pole normally occurs at frequencies where there is on the order of 5 dB gain left and the phase shift adds considerably. The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the feedback resistance is increased, the gain peaking increases at a lower frequency and the 180/C0095 phase shift crossover point also moves down in frequency, decreasing the phase margin. For the TLC07x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance pole. The TLC073 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only. Load capacitance had little effect on these measurements due to the excellent output drive capability of the TLC07x. 600 Ω 22 pF50 Ω 10 kΩ 10 pF IN With C F = 10 pF VDD = ±5 V AV = +1 R F = 10 kΩ R L = 600 Ω C L = 22 pF V I− Input Voltage − V 0.5 1.5 − Output Voltage − VV O t - Time - µs VIN VOUT −0.5 Figure 49. 1-V Step Response

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 21WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Three members of the TLC07x family (TLC070/3/5) have a shutdown terminal (SHDN) for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125 µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to V DD − (not system ground) to disable the operational amplifier. The amplifier’s output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turn-on and turn-off times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figures 37, 38, 39, and 40 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is configured as a voltage follower (A V = 1). The isolation performance is plotted across frequency using 0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals at ±6 V supplies. circuit layout considerations To achieve the levels of high performance of the TLC07x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. /C0068Ground planes − It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. /C0068Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. /C0068Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. /C0068Short trace runs/compact part placements − Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. /C0068Surface-mount passive components − Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 23WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. general PowerPAD design considerations (continued) 1. The thermal pad must be connected to the same voltage potential as the GND pin. 2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawing at the end of this document. There should be etch for the leads as well as etch for the thermal pad. 3. Place five holes (single and dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLC07x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 5. Connect all holes to the internal ground plane that is the same potential as the device GND pin. 6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLC07x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 8. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 9. With these preparatory steps in place, the TLC07x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θ JA, the maximum power dissipation is shown in Figure 54 and is calculated by the following formula: P D /C0043/C0466 TMAX –TA /C0113JA /C0467 Where: PD = Maximum power dissipation of TLC07x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W)

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 24 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 general PowerPAD design considerations (continued) TJ = 150°C −55 −40 −10 20 35 Maximum Power Dissipation − W MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 65 95 125 TA − Free-Air Temperature − °C Low-K Test PCB θJA = 52.3°C/W Low-K Test PCB θJA = 324°C/W −25 5 50 80 110 Low-K Test PCB θJA = 29.7°C/W Low-K Test PCB θJA = 176°C/W Low-K Test PCB θJA = 104°C/W NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 53. Maximum Power Dissipation vs Free-Air Temperature of the heat dissipation is at low output voltages with high output currents. currents and voltages should be used to choose the proper package.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 25WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Macromodel information provided was derived using MicrosimParts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using the TLC07x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): /C0068Maximum positive output voltage swing /C0068Maximum negative output voltage swing /C0068Slew rate /C0068Quiescent power dissipation /C0068Input bias current /C0068Open-loop voltage amplification /C0068Unity-gain frequency /C0068Common-mode rejection ratio /C0068Phase margin /C0068DC output resistance /C0068AC output resistance /C0068Short-circuit output current limit of Solid-State Circuits, SC-9, 353 (1974). PSpice and Parts are trademarks of MicroSim Corporation.

/C0084/C0076/C0067/C0048/C0055/C0048/C0044 /C0084/C0076/C0067/C0048/C0055/C0049/C0044 /C0084/C0076/C0067/C0048/C0055/C0050/C0044 /C0084/C0076/C0067/C0048/C0055/C0051/C0044 /C0084/C0076/C0067/C0048/C0055/C0052/C0044 /C0084/C0076/C0067/C0048/C0055/C0053/C0044 /C0084/C0076/C0067/C0048/C0055/C0120/C0065 /C0070/C0065/C0077/C0073/C0076/C0089 /C0079/C0070 /C0087/C0073/C0068/C0069/C0262/C0066/C0065/C0078/C0068/C0087/C0073/C0068/C0084/C0072 /C0072/C0073/C0071/C0072/C0262/C0079/C0085/C0084/C0080/C0085/C0084/C0262/C0068/C0082/C0073/C0086/C0069 /C0083/C0073/C0078/C0071/C0076/C0069 /C0083/C0085/C0080/C0080/C0076/C0089 /C0079/C0080/C0069/C0082/C0065/C0084/C0073/C0079/C0078/C0065/C0076 /C0065/C0077/C0080/C0076/C0073/C0070/C0073/C0069/C0082/C0083 SLOS219E − JUNE 1999 − REVISED SEPTEMBER 2006 26 WWW.TI.COM POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 − + VDD+ RP IN − IN+ VDD− VAD RD1 J1 J2 RSS ISS RD2 VE DE DP VC DC EGND VB FB GCM GA VLIM RO1 RO2 HLIM DLP DLN VLNVLP .subckt TLC07X_5V 1 2 3 4 5 c1 11 12 4.8697E−12 c2 6 7 8.0000E−12 css 10 99 4.0063E−12 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx fb 7 99 poly(5) vb vc ve vlp vln 0 6.9132E6 −1E3 1E3 6E6 −6E6 ga 6 0 11 12 457.42E−6 gcm 0 6 10 99 1.1293E−6 iss 3 10 dc 183.67E−6 ioff 0 6 dc .806E−6 hlim 90 0 vlim 1K j1 11 2 10 jx1 j2 12 1 10 jx2 r2 6 9 100.00E3 rd1 4 11 2.1862E3 rd2 4 12 2.1862E3 ro1 8 5 10 ro2 7 99 10 rp 3 4 2.4728E3 rss 10 99 1.0889E6 vb 9 0 dc 0 vc 3 53 dc 1.5410 ve 54 4 dc .84403 vlim 7 8 dc 0 vlp 91 0 dc 119 vln 0 92 dc 119 .model dx D(Is=800.00E−18) .model dy D(Is=800.00E−18 Rs=1m Cjo=10p) .model jx1 PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1) .model jx2 PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1) .ends *DEVICE=TLC07X_5V, OPAMP , PJF, INT * TLC07X − 5V operational amplifier ”macromodel” subcircuit * created using Parts release 8.0 on 12/16/99 at 08:38 * Parts is a MicroSim product. * connections: non-inverting input * inverting input * positive power supply * negative power supply * output Figure 54. Boyle Macromodel and Subcircuit

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC070AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC070AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC070CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDGN ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDGNG4 ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC070CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC070ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070IDGNG4 ACTIVE MSOP- Power PAD DGN 8 TBD Call TI Call TI TLC070IDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070IDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC070IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC070IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC071AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC071AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC071CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDGN ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDGNG4 ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC071CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC071ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDGN ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDGNG4 ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC071IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC071IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 2

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) (RoHS) TLC072AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC072AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC072CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDGN ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDGNG4 ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC072CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC072ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDGN ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDGNG4 ACTIVE MSOP- Power PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDGNR ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDGNRG4 ACTIVE MSOP- Power PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 3

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC072IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC072IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC072IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC073AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC073CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC073CDGQ ACTIVE MSOP- Power PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073CDGQG4 ACTIVE MSOP- Power PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC073CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC073IDGQ ACTIVE MSOP- Power PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073IDGQG4 ACTIVE MSOP- Power PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073IDGQR ACTIVE MSOP- Power PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073IDGQRG4 ACTIVE MSOP- Power PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC073IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC073INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 4

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC074AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC074AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC074AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC074AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC074AIPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC074CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC074CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC074CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC074ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLC074IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC074IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075AID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC075AIDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC075AIDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 5

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TLC075AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC075AIN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075AINE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075AIPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075CD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC075CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075CPWPRG4 ACTIVE HTSSOP PWP 20 TBD Call TI Call TI TLC075IDG4 ACTIVE SOIC D 16 TBD Call TI Call TI TLC075IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC075IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLC075IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075IPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC075IPWPRG4 ACTIVE HTSSOP PWP 20 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 6

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 Addendum-Page 7

MPDI001A – JANUARY 1995 – REVISED JUNE 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.015 (0,38) Gage Plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM MAX 0.430 (10,92) 4040082/D 05/98 0.200 (5,08) MAX 0.125 (3,18) MIN 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) 0.100 (2,54) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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