Interface

TLA2528IRTER.A

Texas Instruments

TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs REVISED APRIL 2020

Manufacturer: Texas Instruments

Document: 47 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse T parts

Online Datasheet

Read TLA2528IRTER.A online.

TLA2528 TI | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 47

Technical content

Example ApplicationsDevice Block Diagram ControllerTLA2528 I2C AVDD (VREF) AIN / GPIO AIN / GPIO AIN / GPIO AIN / GPIO AIN / GPIO AIN / GPIO AIN / GPIO AIN / GPIO VSIGNAL + nois e Reduced noise TLA2528 Controller TLA2528 AIN0 / GPIO0 AIN1 / GPIO1 AIN2 / GPIO2 AIN3 / GPIO3 ADC MUX GPO Write GPI Read Pin CFG AIN4 / GPIO4 AIN5 / GPIO5 AIN6 / GPIO6 AIN7 / GPIO7 Sequencer I2C Interface AVDD GND DVDD SDA SCL ADDR DECAP Programmable Averaging Filter Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLA2528 SBAS961A –MAY 2019–REVISED APRIL 2020 TLA2528Small,8-Channel,12-BitADCWithI2CInterfaceandGPIOs

1 Features

1• Small package size: – 3-mm × 3-mm WQFN

8 channels configurable as any combination of: – Up to 8 analog inputs, digital inputs, or digital outputs
GPIOs for I/O expansion: – Open-drain, push-pull digital outputs
Wide operating ranges: – AVDD: 2.35 V to 5.5 V – DVDD: 1.65 V to 5.5 V – –40°C to +85°C temperature range
I2C interface: – Up to 3.4 MHz (high-speed mode) – 8 configurable I2C addresses
Programmable averaging filters: – Programmable sample size for averaging – Averaging with internal conversions – 16-bit resolution for average output

2 Applications

Mobile robot CPU boards
Rack servers
Intra-DC interconnect (metro)

3 Description

The TLA2528 is an easy-to-use, 8-channel, multiplexed, 12-bit, successive approximation register analog-to-digital converter (SAR ADC). The eight channels can be independently configured as either analog inputs, digital inputs, or digital outputs. The device has an internal oscillator for ADC conversion processes. The TLA2528 communicates via an I2C-compatible interface and supports standard-mode (100 kHz), fast-mode (400 kHz), fast-mode plus (1 MHz), and high-speed mode (3.4 MHz). Up to eight I2C addresses can be selected for the TLA2528 by connecting a resistor on the ADDR pin. Device Information(1) PART NAME PACKAGE BODY SIZE (NOM) TLA2528 WQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. TLA2528 Block Diagram and Applications

11.1 Receiving Notification of Documentation Updates 35

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2019) to Revision A Page

16 AIN1/GPIO15AIN6/GPIO6

15 AIN0/GPIO06AIN7/GPIO7

14 SDA7AVDD

13 SCL8DECAP

5 Pin Configuration and Functions

(1) AI = analog input, DI = digital input, and DO = digital output. Pin Functions PIN FUNCTION(1) DESCRIPTION NAME NO. AIN0/GPIO0 15 AI, DI, DO Channel 0; configurable as either an analog input (default) or a general-purpose input/output (GPIO) AIN1/GPIO1 16 AI, DI, DO Channel 1; configurable as either an analog input (default) or a GPIO AIN2/GPIO2 1 AI, DI, DO Channel 2; configurable as either an analog input (default) or a GPIO AIN3/GPIO3 2 AI, DI, DO Channel 3; configurable as either an analog input (default) or a GPIO AIN4/GPIO4 3 AI, DI, DO Channel 4; configurable as either an analog input (default) or a GPIO AIN5/GPIO5 4 AI, DI, DO Channel 5; configurable as either an analog input (default) or a GPIO AIN6/GPIO6 5 AI, DI, DO Channel 6; configurable as either an analog input (default) or a GPIO AIN7/GPIO7 6 AI, DI, DO Channel 7; configurable as either an analog input (default) or a GPIO ADDR 11 AI Input for selecting the device I2C address. Connect a resistor to this pin from DECAP pin or GND to select one of the eight addresses. AVDD 7 Supply Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF decoupling capacitor to GND DECAP 8 Supply Connect a1-µF decoupling capacitor between the DECAP and GND pins for the internal power supply DVDD 10 Supply Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND GND 9 Supply Ground for the power supply; all analog and digital signals are referred to this pin voltage NC 12 No connection This pin must be left floating with no external connection SDA 14 DI, DO Serial data input or output for the I2C interface SCL 13 DI Serial clock for the I2C interface Thermal pad — Supply Exposed thermal pad; connect to GND.

SBAS961A –MAY 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: TLA2528 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) AINx/GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16. (3) Pin current must be limited to 10mA or less.

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT DVDD to GND –0.3 5.5 V AVDD to GND –0.3 5.5 V AINx/GPOx(2) GND – 0.3 AVDD + 0.3 V ADDR GND – 0.3 2.1 V Digital inputs GND – 0.3 5.5 V Current through any pin except supply pins(3) –10 10 mA Junction temperature, TJ –40 125 °C Storage temperature, Tstg –60 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY AVDD Analog supply voltage 2.35 3.3 5.5 V DVDD Digital supply voltage 1.65 3.3 5.5 V ANALOG INPUTS FSR Full-scale input range AINX (1) - GND 0 AVDD V TEMPERATURE RANGE TA Ambient temperature –40 25 85 ℃ (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLA2528 UNITRTE (WQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 49.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 53.4 °C/W RθJB Junction-to-board thermal resistance 24.7 °C/W ΨJT Junction-to-top characterization parameter 1.3 °C/W ΨJB Junction-to-board characterization parameter 24.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 9.3 °C/W

6.5 Electrical Characteristics

at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS CSH Sampling capacitance 12 pF DC PERFORMANCE Resolution No missing codes 12 bits DNL Differential nonlinearity ±0.45 LSB INL Integral nonlinearity ±0.5 LSB V(OS) Input offset error Post offset calibration ±0.3 LSB Input offset thermal drift Post offset calibration ±1 ppm/°C GE Gain error ±0.05 %FSR Gain error thermal drift ±1 ppm/°C AC PERFORMANCE SINAD Signal-to-noise + distortion ratio AVDD = 5 V, fIN = 2 kHz 73.2 dB AVDD = 3 V, fIN = 2 kHz 72.8 SNR Signal to noise ratio AVDD = 5 V, fIN = 2 kHz 73.3 dB AVDD = 3 V, fIN = 2 kHz 73 DECAP Pin CDECAP Decoupling capacitor on DECAP pin 0.1 1 4.7 µF Voltage output on DECAP pin CDECAP = 1 µF 1.8 V DIGITAL INPUT/OUTPUT (SCL, SDA) VIH Input high logic level All I2C modes 0.7 x DVDD 5.5 V VIL Input low logic level All I2C modes –0.3 0.3 x DVDD V VOL Output low logic level Sink current = 2 mA, DVDD > 2 V 0 0.4 V Sink current = 2 mA, DVDD ≤ 2 V 0 0.2 x DVDD IOL Low-level output current (sink) VOL = 0.4 V, standard and fast mode 3 mAVOL = 0.6 V, fast mode 6 VOL = 0.4 V, fast mode plus 20 GPIOs VIH Input high logic level 0.7 x AVDD AVDD + 0.3 V VIL Input low logic level –0.3 0.3 x AVDD V VOH Output high logic level GPO_DRIVE_CFG = push-pull, ISOURCE = 2 mA 0.8 x AVDD AVDD V VOL Output low logic level ISINK = 2 mA 0 0.2 x AVDD V IOH Output high source current VOH > 0.7 x AVDD 5 mA IOL Output low sink current VOL < 0.3 x AVDD 5 mA POWER SUPPLY CURRENTS IAVDD Analog supply current I2C high-speed mode, AVDD = 5 V 150 195 µA I2C fast mode plus, AVDD = 5 V 50 75 I2C fast mode, AVDD = 5 V 28 40 I2C standard mode, AVDD = 5 V 12 18 No conversion, AVDD = 5 V 7 12

SBAS961A –MAY 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: TLA2528 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) The device supports standard, full-speed, and fast modes by default on power-up. For selecting high-speed mode refer to the section on Configuring the Device for High-Speed I2C Mode. (2) Bus load (CB) consideration; CB ≤ 400 pF for fSCL ≤ 1 MHz; CB < 100 pF for fSCL = 3.4 MHz.

6.6 I2C Timing Requirements

MODE(1) UNITSTANDARD, FAST, AND FAST MODE PLUS HIGH SPEED MODE MIN MAX MIN MAX fSCL SCL clock frequency(2) 1 3.4 MHz tSUSTA START condition setup time for repeated start 260 160 ns tHDSTA Start condition hold time 260 160 ns tLOW Clock low period 500 160 ns tHIGH Clock high period 260 60 ns tSUDAT Data in setup time 50 10 ns tHDDAT Data in hold time 0 0 ns tR SCL rise time 120 80 ns tF SCL fall time 120 80 ns tSUSTO STOP condition hold time 260 60 ns tBUF Bus free time before new transmission 500 300 ns

6.7 Timing Requirements

at AVDD = 2.35 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. MIN MAX UNIT tACQ Acquisition time 300 ns

6.8 I2C Switching Characteristics

UNITSTANDARD, FAST, AND FAST MODE PLUS HIGH-SPEED MODE MIN MAX MIN MAX tVDDATA SCL low to SDA data out valid 450 200 ns tVDACK SCL low to SDA acknowledge time 450 200 ns tSTRETCH Clock stretch time in one-shot conversion mode 1400 1000 ns tSP Noise supression time constant on SDA and SCL 50 10 ns

(1) RST bit is automatically reset to 0b after tRST.

6.9 Switching Characteristics

maximum values at TA = –40°C to +85°C; typical values at TA = 25°C. NOTE: S = start, Sr = repeated start, and P = stop. Figure 1. I2C Timing Diagram

6.10 Typical Characteristics

Figure 2. DC Input Histogram Figure 3. Typical DNL Figure 4. Typical INL Figure 5. DNL vs Temperature Figure 6. INL vs Temperature Figure 7. DNL vs AVDD

Figure 20. Analog Supply Current vs Throughput

7 Detailed Description

7.1 Overview

The TLA2528 is a small, eight-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2C- compatible serial interface. The eight channels of the TLA2528 can be individually configured as either analog inputs, digital inputs, or digital outputs. The device uses an internal oscillator for conversion. The analog input channel selection can be auto-sequenced to simplify the digital interface with the host. The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution. The I2C serial interface supports standard-mode, fast-mode, fast-mode plus, and high-speed mode.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Multiplexer and ADC

Figure 21. Analog Inputs, GPIOs, and ADC Connections from the sampling capacitor.

7.3.2 Reference

The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process. between the AVDD and GND pins.

7.3.3 ADC Transfer Function

1 LSB = VREF / 2N

VREF = AVDD
N = 12 (1) Figure 22 and Table 1 detail the transfer characteristics for the device.

1 LSB (AVDD ±1 LSB)(AVDD/2 + 1 LSB)AVDD/2

Figure 22. Ideal Transfer Characteristics Table 1. Transfer Characteristics

1 LSB to 2 LSBs NFSC + 1 — 001

7.3.4 ADC Offset Calibration

to check the ADC offset calibration completion status.

7.3.5 I2C Address Selector

power-up event, until the next device reset, or until the device receives a command to program its own address. different addresses of the device. Figure 23. External Resistor Connection Diagram for the ADDR Pin

1621 AVDD LSB

(1) Tolerance for R1, R2 ≤ ±5%. Table 2. I2C Address Selection

7.3.6 Programmable Averaging Filter

to be averaged. As shown in Figure 24, the 16-bit result can be read out after the averaging operation completes. Figure 24. Averaging Example can be read in the RECENT_CHx_LSB and RECENT_CHx_MSB registers. Equation 2 provides the LSB value of the 16-bit average result.

7.3.7 General-Purpose I/Os (GPIOs)

outputs. Table 3 describes how the PIN_CFG and GPIO_CFG registers can be used to configure the channels.

Table 3. Configuring Channels as Analog Inputs or GPIOs GPI_VALUE register returns the logic level for all channels configured as digital inputs.

7.3.8 Oscillator and Timing Control

CLK_DIV[3:0] register fields. Table 4. Configuring Sampling Rate for Internal Conversion Start Control OSC_SEL and CLK_DIV[3:0] configuration.

7.3.9 Output Data Format

Figure 25 illustrates various I2C frames for reading data.

Read the ADC conversion result: Two 8-bit I2C packets are required (frame A).
Read the averaged conversion result: Two 8-bit I2C packets are required (frame B).
Read data with the channel ID appended: The 4-bit channel ID can be appended to the 12-bit ADC result by configuring the APPEND_STATUS field in the GENERAL_CFG register. When the channel ID is appended to the 12-bit ADC data, two I2C packets are required (frame C). If the channel ID is appended to the 16-bit average result, three I2C frames are required (frame D).

Figure 25. Data Frames for Reading Data

7.3.10 I2C Protocol Features

7.3.10.1 General Call

On receiving a general call (00h), the device provides an acknowledge (ACK).

7.3.10.2 General Call With Software Reset

On receiving a general call (00h) followed by a software reset (06h), the device resets itself.

7.3.10.3 General Call With a Software Write to the Programmable Part of the Slave Address

7.3.10.4 Configuring the Device for High-Speed I2C Mode

and remains in high-speed I2C mode until a STOP condition is received in an I2C frame.

7.4 Device Functional Modes

Table 5 lists the functional modes supported by the TLA2528. Table 5. Functional Modes

listed in Table 5 by writing the configuration registers for the desired mode.

7.4.1 Device Power-Up and Reset

is set, thus indicating a power-cycle or reset event. by recycling the power on the AVDD pin.

7.4.2 Manual Mode

steps for operating the device in manual mode. Figure 26. Device Operation in Manual Mode byte of output data is read. Figure 27. Starting a Conversion and Reading Data in Manual Mode

7.4.3 Auto-Sequence Mode

Figure 28. Device Operation in Auto-Sequence Mode

7.5 Programming

Table 6. I2C Frame Acronyms Table 7. Opcodes for Commands

7.5.1 Reading Registers

the Single Register Read and Reading a Continuous Block of Registers sections.

7.5.1.1 Single Register Read

or a RESTART condition in the I2C frame. NOTE: S = start, Sr = repeated start, and P = stop. Figure 29. Reading Register Data

7.5.1.2 Reading a Continuous Block of Registers

RESTART condition in the I2C frame. NOTE: S = start, Sr = repeated start, and P = stop. Figure 30. Reading a Continuous Block of Registers

7.5.2 Writing Registers

a register, or clear a few bits in a register.

7.5.2.1 Single Register Write

command, the master must provide a STOP or a RESTART condition in the I2C frame. NOTE: S = start, Sr = repeated start, and P = stop. Figure 31. Writing a Single Register

7.5.2.2 Set Bit

and bits with a value of 0 in the register data are not changed. Table 7 lists the opcodes for different commands. To end this command, the master must provide a STOP or RESTART condition in the I2C frame.

7.5.2.3 Clear Bit

commands. To end this command, the master must provide a STOP or a RESTART condition in the I2C frame.

7.5.2.4 Writing a Continuous Block of Registers

The I2C master must provide an I2C command, as shown in Figure 32, to write a continuous block of registers. STOP or a RESTART condition in the I2C frame. NOTE: S = start, Sr = repeated start, and P = stop. Figure 32. Writing a Continuous Block of Registers

7.6 TLA2528 Registers

reserved locations and the register contents should not be modified. Table 8. TLA2528 Registers access types in this section. Table 9. TLA2528 Access Type Codes

7.6.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x80]

SYSTEM_STATUS is shown in Figure 33 and described in Table 10. Return to the Summary Table.

Figure 33. SYSTEM_STATUS Register Table 10. SYSTEM_STATUS Register Field Descriptions 7 RSVD R 1b This bit must read 1b.

6 SEQ_STATUS R 0b Sequencer Status

5 I2C_SPEED R 0b I2C high-speed status

4 RESERVED R 0b Reserved. Reads return 0b. 3 OSR_DONE R/W 0b OSR status. Clear this bit by writing 1b to this bit. 0b = OSR in progress; data not ready. 1b = OSR complete; data ready. the device or power cycle AVDD. 1b = Device configuration not loaded correctly. 1 RESERVED R 0b Reserved. Reads return 0b. or device is power cycled. Write 1 to this bit to clear the flag. 0b = No brown out from last time this bit was cleared. 1b = Brown out condition detected or device power cycled.

7.6.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]

GENERAL_CFG is shown in Figure 34 and described in Table 11. Return to the Summary Table. Figure 34. GENERAL_CFG Register Table 11. GENERAL_CFG Register Field Descriptions 7-4 RESERVED R 0b Reserved. Reads return 0b. 3 CNVST W 0b Intiate start of conversion. Readback of this bit will return 0. 1b = Initiate start of conversion. 2 CH_RST R/W 0b Force all channels to be analog inputs. configuration in other registers. 1 CAL R/W 0b Calibrate ADC offset.

Table 11. GENERAL_CFG Register Field Descriptions (continued) 0 RST W 0b Software reset all registers to default values.

7.6.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]

DATA_CFG is shown in Figure 35 and described in Table 12. Return to the Summary Table. Figure 35. DATA_CFG Register Table 12. DATA_CFG Register Field Descriptions 6 RESERVED R 0b Reserved. Reads return 0b. 5-4 APPEND_STATUS[1:0] R/W 0b Append 4-bit channel ID to output data. 0b = Channel ID is not appended to ADC data. 1b = Channel ID is appended to ADC data. 3-0 RESERVED R 0b Reserved. Reads return 0b.

7.6.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]

OSR_CFG is shown in Figure 36 and described in Table 13. Return to the Summary Table. Figure 36. OSR_CFG Register Table 13. OSR_CFG Register Field Descriptions 7-3 RESERVED R 0b Reserved. Reads return 0b. 2-0 OSR[2:0] R/W 0b Selects the oversampling ratio for ADC conversion result.

7.6.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]

OPMODE_CFG is shown in Figure 37 and described in Table 14. Return to the Summary Table. Figure 37. OPMODE_CFG Register Table 14. OPMODE_CFG Register Field Descriptions 7-5 RESERVED R 0b Reserved. Reads return 0b. 4 OSC_SEL R/W 0b Selects the oscillator for internal timing generation.

7.6.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]

PIN_CFG is shown in Figure 38 and described in Table 15. Return to the Summary Table. Figure 38. PIN_CFG Register Table 15. PIN_CFG Register Field Descriptions 0b = Channel is configured as analog input. 1b = Channel is configured as GPIO.

7.6.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]

GPIO_CFG is shown in Figure 39 and described in Table 16. Return to the Summary Table. Figure 39. GPIO_CFG Register Table 16. GPIO_CFG Register Field Descriptions 1b = GPIO is digital output.

7.6.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]

GPO_DRIVE_CFG is shown in Figure 40 and described in Table 17. Return to the Summary Table. Figure 40. GPO_DRIVE_CFG Register Table 17. GPO_DRIVE_CFG Register Field Descriptions 0b = Digital output is open-drain. Connect external pullup. 1b = Digital output is push-pull.

7.6.9 GPO_VALUE Register (Address = 0xB) [reset = 0x0]

GPO_VALUE is shown in Figure 41 and described in Table 18. Return to the Summary Table. Figure 41. GPO_VALUE Register Table 18. GPO_VALUE Register Field Descriptions 7-0 GPO_VALUE[7:0] R/W 0b Logic level to be set on digital outputs GPO[7:0]. 0b = Digital output set to logic 0. 1b = Digital output set to logic 1.

7.6.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]

GPI_VALUE is shown in Figure 42 and described in Table 19. Return to the Summary Table. Figure 42. GPI_VALUE Register Table 19. GPI_VALUE Register Field Descriptions 7-0 GPI_VALUE[7:0] R 0b Readback the logic level on digital input. 0b = Digital input is at logic 0. 1b = Digital input is at logic 1.

7.6.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]

SEQUENCE_CFG is shown in Figure 43 and described in Table 20. Return to the Summary Table.

Figure 43. SEQUENCE_CFG Register Table 20. SEQUENCE_CFG Register Field Descriptions 7-5 RESERVED R 0b Reserved. Reads return 0b. 4 SEQ_START R/W 0b Sequence start control when using auto sequence mode. starting from channel ID = 0 (ascending order). 3-2 RESERVED R 0b Reserved. Reads return 0b. 1-0 SEQ_MODE[1:0] R/W 0b Selects the mode of scanning analog input channels.

7.6.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]

CHANNEL_SEL is shown in Figure 44 and described in Table 21. Return to the Summary Table. Figure 44. CHANNEL_SEL Register Table 21. CHANNEL_SEL Register Field Descriptions 7-4 RESERVED R 0b Reserved. Reads return 0b. channel ID must not be configured as GPIO.

7.6.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]

AUTO_SEQ_CH_SEL is shown in Figure 45 and described in Table 22. Return to the Summary Table.

Figure 45. AUTO_SEQ_CH_SEL Register Table 22. AUTO_SEQ_CH_SEL Register Field Descriptions 0b = Analog input channel is not enabled in scanning sequence. 1b = Analog input channel is enabled in scanning sequence.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Applications

8.2.1 Mixed-Channel Configuration

Figure 46. DAQ Circuit: Single-Supply DAQ

8.2.1.1 Design Requirements

outputs, and push-pull digital outputs.

8.2.1.2 Detailed Design Procedure

GPIO_CFG registers; see Table 3.

8.2.1.2.1 Digital Input

state of the digital input can be read from the GPI_VALUE register. Figure 47. Digital Input

8.2.1.2.2 Digital Open-Drain Output

connecting the pull-up resistor to ground and bringing the node voltage at GPOx low. Figure 48. Digital Open-Drain Output maximum current supported by the device digital output (5 mA). requirement, ILOAD, of the receiving device driven by this GPIO. Select RPULL_UP such that RMIN < RPULL_UP < RMAX.

8.2.1.3 Application Curve

Figure 49. DC Input Histogram

8.2.2 Digital Push-Pull Output

opposed to an open-drain output where the line is left floating. Figure 50. Digital Push-Pull Output

9 Power Supply Recommendations

9.1 AVDD and DVDD Supply Recommendations

single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device. Connect a 1-µF decoupling capacitor between the DECAP and GND pins for the internal power supply. Figure 51. Power-Supply Decoupling

10 Layout

10.1 Layout Guidelines

and keep the analog input signals and the AVDD supply away from noise sources. connect the decoupling capacitor to the device pins with thick copper tracks.

10.2 Layout Example

Figure 52. Example Layout

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3

0.8 MAX

(DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 4 9 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD

17 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 1.55) (R0.05) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM ALL AROUND METAL SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM 5 8 1316

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLA2528IRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 TLA2528IRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 TLA2528IRTERG4 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 TLA2528IRTERG4.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 TLA2528IRTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 TLA2528IRTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 2528 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 9-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLA2528IRTER WQFN RTE 16 3000 367.0 367.0 35.0 TLA2528IRTERG4 WQFN RTE 16 3000 367.0 367.0 35.0 TLA2528IRTET WQFN RTE 16 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTE 16 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.5 mm pitch 4225944/A

www.ti.com PACKAGE OUTLINE C 16X 0.30 0.18 1.68 0.07 16X 0.5 0.3 (DIM A) TYP 0.05 0.00 12X 0.5 1.5 A 3.1 2.9 B 3.1 2.9 WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA 0.08 SEATING PLANE 4 9 5 8 16 13 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT 16X (0.24) 16X (0.6) ( 0.2) TYP VIA 12X (0.5) (2.8) (2.8) (0.58) TYP ( 1.68) (R0.05) ALL PAD CORNERS (0.58) TYP WQFN - 0.8 mm max heightRTE0016C PLASTIC QUAD FLATPACK - NO LEAD 4219117/B 04/2022 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Product Information

TLA2528IRTER.A specifications and overview.

Summary

TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs REVISED APRIL 2020

Description

TLA2528 Small, 8-Channel, 12-Bit ADC With I2C Interface and GPIOs REVISED APRIL 2020

Source title TLA2528IRTER.A Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer