TLA2021 TI | Alldatasheet
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3.3 V 3.3 V TLA2024 AIN0 AIN1 AIN3 Mux Oscillator PGA 12-Bit ADC Voltage Reference GND VDD I2C Interface SDA ADDR SCL AIN2 3.3 V I2C Bus Analog Output Temperature Sensor IC Current Sense Amplifier R SHUNT Power Supply Monitoring R BIAS Thermistor 3.3 V Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLA2021,TLA2022,TLA2024 SBAS846 – NOVEMBER 2017 TLA202xCost-Optimized,Ultra-Small,12-Bit,System-MonitoringADCs
1 Features
1• Industry’s Lowest-Cost 12-Bit Delta-Sigma ADCs
- Ultra-Small X2QFN Package: 2 mm × 1.5 mm
- Highly Integrated: – 4 Single-Ended or 2 Differential Inputs Make the TLA2024 the Industry’s Highest Channel Density ADC (0.75 mm² per Channel) – PGA (TLA2022 and TLA2024 Only) – Voltage Reference – Oscillator
- Low Current Consumption: 150 µA
- Wide Supply Range: 2 V to 5.5 V
- Programmable Data Rate: 128 SPS to 3.3 kSPS
- I2C™ Compatible Interface: – Supports Standard-Mode and Fast-Mode – Three Pin-Selectable I2C Addresses
- Operating Temperature Range: –40°C to +85°C
2 Applications
- Personal Electronics: – TVs, Tablets, Cell Phones – Wearables – Drones, Toys
- Home and Kitchen Appliances
- Building Automation: – HVACs, Smoke Detectors
- Battery Voltage and Current Monitoring
- Temperature Sensing
- Battery-Powered, Portable Instrumentation
3 Description
The TLA2021, TLA2022, and TLA2024 devices (TLA202x) are easy-to-use, low-power, 12-bit delta- sigma (ΔΣ) analog-to-digital converters (ADCs) targeted for any type of system-monitoring applications (such as supply or battery voltage supervision, current sensing, or temperature measurements). Offered in an ultra-small, leadless, 10-pin X2QFN package, the TLA2021 and TLA2022 are single-channel ADCs while the TLA2024 features a flexible input multiplexer (MUX) with two differential or four single-ended input measurement options. The TLA202x integrate a voltage reference and oscillator. Additionally, the TLA2022 and TLA2024 include a programmable gain amplifier (PGA) with selectable input ranges from ±256 mV to ±6.144 V, enabling both large- and small-signal measurements. The TLA202x communicate via an I2C-compatible interface and operate in either continuous or single- shot conversion mode. The devices automatically power down after one conversion in single-shot conversion mode, significantly reducing power consumption during idle periods. All of these features, along with a wide operating supply voltage range, make the TLA202x suitable for power- and space-constrained, system-monitoring applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLA2021 X2QFN (10) 1.50 mm × 2.00 mmTLA2022 TLA2024 (1) For all available packages, see the orderable addendum at the end of the data sheet. System-Monitoring Application Example
TLA2021,TLA2022,TLA2024 SBAS846 – NOVEMBER 2017 www.ti.com Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents
12.3 Receiving Notification of Documentation Updates 27
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES November 2017 * Initial release.
6 AIN2
7 AIN3
8 VDD
9 SDA
10 SCL
TLA2021,TLA2022,TLA2024 www.ti.com SBAS846 – NOVEMBER 2017 Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
5 Device Comparison Table
(Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS, DIFFERENTIAL (Single-Ended) PGA INTERFACE TLA2021 12 3300 1 (1) No I2C TLA2022 12 3300 1 (1) Yes I2C TLA2024 12 3300 2 (4) Yes I2C
6 Pin Configuration and Functions
TLA2021 and TLA2022 RUG Package 10-Pin X2QFN Top View 10-Pin X2QFN Top View (1) Float unused analog inputs, or tie unused analog inputs to GND. Pin Functions PIN TYPE DESCRIPTION NAME TLA2021, TLA2022 TLA2024 ADDR 1 1 Digital input I2C slave address select pin. See the I2C Address Selection section for details. AIN0 4 4 Analog input Analog input 0(1) AIN1 5 5 Analog input Analog input 1(1) AIN2 — 6 Analog input Analog input 2(1) AIN3 — 7 Analog input Analog input 3(1) GND 3 3 Supply Ground NC 2, 6, 7 2 — No connect; always leave floating SCL 10 10 Digital input Serial clock input. Connect to VDD using a pullup resistor. SDA 9 9 Digital I/O Serial data input and output. Connect to VDD using a pullup resistor. VDD 8 8 Supply Power supply. Connect a 0.1-µF, power-supply decoupling capacitor to GND.
TLA2021,TLA2022,TLA2024 SBAS846 – NOVEMBER 2017 www.ti.com Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
7 Specifications
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.1 Absolute Maximum Ratings(1)
Power-supply voltage VDD to GND –0.3 7 VAnalog input voltage AIN0, AIN1, AIN2, AIN3 GND – 0.3 VDD + 0.3 Digital input voltage SDA, SCL, ADDR GND – 0.3 7 Input current Continuous, any pin except power-supply pins –10 10 mA Temperature Junction, TJ –40 125 Storage, Tstg –60 125 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) AINP and AINN denote the selected positive and negative inputs. On the TLA2024, AINx denotes one of the four available analog inputs. (2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See the Full-Scale Range (FSR) and LSB Size section more information.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD to GND 2 5.5 V ANALOG INPUTS(1) FSR Full-scale input voltage range(2) (VIN = VAINP – VAINN) ±0.256 ±6.144 V V(AINx) Absolute input voltage GND VDD V DIGITAL INPUTS Digital input voltage GND 5.5 V TEMPERATURE TA Operating ambient temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) TLA202x UNITRUG (X2QFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 245.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.3 °C/W RθJB Junction-to-board thermal resistance 172.0 °C/W ψJT Junction-to-top characterization parameter 8.2 °C/W ψJB Junction-to-board characterization parameter 170.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
TLA2021,TLA2022,TLA2024 www.ti.com SBAS846 – NOVEMBER 2017 Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be applied to this device. See the Full-Scale Range (FSR) and LSB Size section for more information. (2) Best-fit INL; covers 99% of full-scale. (3) Includes all errors from onboard PGA and voltage reference.
7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +85°C; typical specifications are at TA = 25°C; all specifications are at VDD = 3.3 V, data rate = 128 SPS, and FSR = ±2.048 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Common-mode input impedance FSR = ±6.144 V(1) 10 MΩ FSR = ±1.024 V 3 FSR = ±0.512 V, FSR = ±0.256 V 100 Differential input impedance FSR = ±6.144 V(1) 22 MΩ FSR = ±4.096 V(1) 15 FSR = ±2.048 V 4.9 FSR = ±1.024 V 2.4 FSR = ±0.512 V, ±0.256 V 710 kΩ SYSTEM PERFORMANCE Resolution (no missing codes) 12 Bits DR Data rate 128, 250, 490, 920, 1600, 2400, 3300 SPS Data rate variation All data rates –10% 10% INL Integral nonlinearity(2) 1 LSB Offset error ±1 LSB Offset drift 0.01 LSB/°C Gain error(3) 0.05% Gain drift(3) 10 ppm/°C PSRR Power-supply rejection ratio 85 dB CMRR Common-mode rejection ratio 90 dB DIGITAL INPUT/OUTPUT VIL Logic input level, low GND 0.3 VDD V VIH Logic input level, high 0.7 VDD 5.5 V VOL Logic output level, low IOL = 3 mA GND 0.15 0.4 V Input leakage current GND < VDigital Input < VDD –10 10 µA POWER SUPPLY IVDD Supply current Power-down 0.5 µA Operating 150 PD Power dissipation VDD = 5 V 0.9 mWVDD = 3.3 V 0.5 VDD = 2 V 0.3
7.6 I2C Timing Requirements
Hold time, (repeated) START condition. Hold time, (repeated) START condition. Figure 1. I2C Timing Requirements
7.7 Typical Characteristics
Figure 2. Operating Current vs Temperature Figure 3. Power-Down Current vs Temperature Figure 4. Data Rate vs Temperature
8 Detailed Description
8.1 Overview
The TLA202x are a family of very small, low-power, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). and Figure 7 show the functional block diagrams of the TLA2024, TLA2022, and TLA2021, respectively. code proportional to the input voltage. programmed data rate. Data can be read at any time and always reflect the most recently completed conversion.
8.2 Functional Block Diagrams
Figure 5. TLA2024 Block Diagram Figure 6. TLA2022 Block Diagram Figure 7. TLA2021 Block Diagram
8.3 Feature Description
8.3.1 Multiplexer
the negative input of the ADC is internally connected to GND by a switch within the multiplexer. Figure 8. Input Multiplexer absolute voltage on any input within the range shown in Equation 1 to prevent the ESD diodes from turning on. series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).
8.3.2 Analog Inputs
stage are small, and to external circuitry, the average loading appears resistive. Figure 9 shows this structure. Figure 9. During the sampling phase, switches S1 are closed. This event charges CA1 to VAINP, CA2 to VAINN, and the effective impedance (Zeff), where Zeff = VIN / IAVERAGE. Figure 9. Simplified Analog Input Circuit Figure 10. S1 and S2 Switch Timing Figure 9, the common-mode input impedance is ZCM. scales with the full-scale range. In Figure 9, the differential input impedance is ZDIFF. applications, this input impedance drift is negligible and can be ignored.
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device.
8.3.3 Full-Scale Range (FSR) and LSB Size
Equation 2 shows how to calculate the LSB size from the selected full-scale range. Table 1. Full-Scale Range and Corresponding LSB Size The FSR of the TLA2021 is fixed at ±2.048 V.
8.3.4 Voltage Reference
The TLA202x have an integrated voltage reference. An external reference cannot be used with these devices. in the gain error and gain drift specifications in the Electrical Characteristics table.
8.3.5 Oscillator
8.3.6 Output Data Rate and Conversion Time
Conversions in the TLA202x settle within a single cycle, which means the conversion time equals 1 / DR.
TLA2021,TLA2022,TLA2024 SBAS846 – NOVEMBER 2017 www.ti.com Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
8.4 Device Functional Modes
8.4.1 Reset and Power-Up
The TLA202x reset on power-up and set all bits in the configuration register to the respective default settings. The TLA202x enter a power-down state after completion of the reset process. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the TLA202x relieves systems with tight power-supply requirements from encountering a surge during power-up. The TLA202x respond to the I2C general-call reset command. When the TLA202x receive a general-call reset command (06h), an internal reset is performed as if the device is powered up.
8.4.2 Operating Modes
The TLA202x operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the configuration register selects the respective operating mode.
8.4.2.1 Single-Shot Conversion Mode
When the MODE bit in the configuration register is set to 1, the TLA202x enter a power-down state, and operate in single-shot conversion mode. This power-down state is the default state for the TLA202x when power is first applied. Although powered down, the devices respond to commands. The TLA202x remain in this power-down state until a 1 is written to the operational status (OS) bit in the configuration register. When the OS bit is asserted, the device powers up in approximately 25 µs, resets the OS bit to 0, and starts a single conversion. When conversion data are ready for retrieval, the OS bit is set to 1 and the device powers down again. Writing a 1 to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0 to the MODE bit in the configuration register.
8.4.2.2 Continuous-Conversion Mode
In continuous-conversion mode (MODE bit set to 0), the TLA202x perform conversions continuously. When a conversion is complete, the TLA202x place the result in the conversion data register and immediately begin another conversion. When writing new configuration settings, the currently ongoing conversion completes with the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start. To switch to single-shot conversion mode, write a 1 to the MODE bit in the configuration register or reset the device.
8.5 Programming
8.5.1 I2C Interface
write under the direction of the master. The TLA202x always act as I2C slave devices. I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high. simultaneously, there is no driver contention. See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
8.5.1.1 I2C Address Selection
first falling SCL edge of the address byte, the TLA202x decode its address configuration again. Table 2. ADDR Pin Connection and Corresponding Slave Address
8.5.1.2 I2C Interface Speed
(Hs-mode) are not supported.
8.5.1.3 Serial Clock (SCL) and Serial Data (SDA)
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line. The TLA202x cannot act as a master and as a result can never drive SCL. a TLA202x, the master drives the data line. an idle state, the master should hold SCL high.
8.5.1.4 I2C Data Transfer Protocol
condition. The bus is considered to be busy after the START condition. recognize the slave address, the TLA202x holds SDA high to indicate a not acknowledge (NACK) signal. must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK. If the transaction is a write, the TLA202x issues the ACK. Figure 11. I2C Data Transfer Format
8.5.1.5 Timeout
8.5.1.6 I2C General-Call (Software Reset)
8.5.2 Reading and Writing Register Data
mapping between the register pointer value and the register that is addressed. data are transmitted most significant bit first. Table 3. Register Pointer (RP)
8.5.2.1 Reading Conversion Data or the Configuration Register
terminate the transmission after any byte by not acknowledging or issuing a START or STOP condition. because the TLA202x store the value of the register pointer until a write operation modifies the value. (1) The master can terminate the transmission after the first byte by not acknowledging. Figure 12. Reading Register Data
8.5.2.2 Writing the Configuration Register
acknowledge each received byte. Figure 13. Writing Register Data Figure 14 provides a legend for Figure 12 and Figure 13. Figure 14. Legend for the I2C Sequence Diagrams
8.5.3 Data Format
(1) Excludes the effects of noise, INL, offset, and gain errors. Table 4. Input Signal Versus Ideal Output Code Figure 15. Code Transition Diagram TLA202x can still output negative codes in case VAINP is close to 0 V.
8.6 Register Maps
TLA202x operating modes and queries the status of the device. Table 5 lists the access codes for the TLA202x. Table 5. TLA202x Access Type Codes
8.6.1 Conversion Data Register (RP = 00h) [reset = 0000h]
The 16-bit conversion data register contains the result of the last conversion in binary two's-complement format. Figure 16. Conversion Data Register Table 6. Conversion Data Register Field Descriptions
8.6.2 Configuration Register (RP = 01h) [reset = 8583h]
The 16-bit configuration register controls the operating mode, input selection, data rate, and full-scale range. Figure 17. Configuration Register
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device. Table 7. Configuration Register Field Descriptions
15 OS R/W 1h Operational Status or Single-Shot Conversion Start
when in a power-down state and has no effect when a conversion is ongoing. These bits configure the input multiplexer. These bits set the FSR of the programmable gain amplifier. These bits serve no function on the TLA2021 and are always set to 010.
8 MODE R/W 1h Operating Mode
This bit controls the operating mode. These bits control the data rate setting.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections give example circuits and suggestions for using the TLA202x in various applications.
9.1.1 Basic Interface Connections
Figure 18 shows the principle I2C connections for the TLA202x. Figure 18. Typical Interface Connections of the TLA202x provided for unless other clock-stretching devices are present on the same I2C bus. unable to pull the bus lines low.
9.1.2 Connecting Multiple Devices
presented by multiple devices and increased line length. NOTE: The TLA202x power and input connections are omitted for clarity. The ADDR pin selects the I2C address. Figure 19. Connecting Multiple TLA202x Devices
9.1.3 Single-Ended Signal Measurements
thereof in case +FS > VDD) is used in this case. Figure 20. Filter Implementation for Single-Ended and Differential Signal Measurements
9.1.4 Analog Input Filtering
- Limits the effect of aliasing during the ADC sampling process
- Attenuates unwanted noise components outside the bandwidth of interest
can be added as well, but should always be at least ten times smaller than the differential filter capacitor. Figure 20 shows an example of filtering a differential signal (AIN0, AIN1), and a single-ended signal (AIN3).
9.1.5 Duty Cycling To Reduce Power Consumption
cycling rate is arbitrary and is defined by the master controller.
9.1.6 I2C Communication Sequence Example
subsequently read the conversion result.
- Write the configuration register as shown in Figure 21 to configure the device (for example, write MUX[2:0] =
Figure 21. Write the Configuration Register
- Wait at least t = 1 / DR ± 10% for the conversion to complete.
for retrieval. This option does not work in continuous-conversion mode because the OS bit always reads 0. Figure 22. Read the Configuration Register to Check for OS = 1
- Then, as shown in Figure 23, read the conversion data register:
Figure 23. Read the Conversion Data Register
- Start a new single-shot conversion by writing a 1 to the OS bit in the configuration register.
To save time, a new conversion can also be started (step 4) before reading the conversion result (step 3). Figure 24 lists a legend for Figure 21 to Figure 23. Figure 24. Legend for the I2C Sequence Diagrams
9.2 Typical Application
system. Figure 25 shows a typical implementation for monitoring two supply voltage rails. Figure 25. Monitoring Two Supply Voltage Rails Using the TLA2024
9.2.1 Design Requirements
Table 8 lists the design requirements for this application. Table 8. Design Requirements
9.2.2 Detailed Design Procedure
measure the 1.8-V rail or the FSR can be set to FSR = ±2.048 V.
3.3 V rail monitor
1.8 V rail monitor
9.2.3 Application Curve
the complete operating ambient temperature range without any offset or gain calibration. Figure 26. Measurement Error vs Temperature
10 Power Supply Recommendations
The device requires a single unipolar supply (VDD) to power the analog and digital circuitry of the device.
10.1 Power-Supply Sequencing
10.2 Power-Supply Decoupling
multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Figure 27. TLA202x Power-Supply Decoupling
11 Layout
11.1 Layout Guidelines
designing with any analog component. Figure 28. System Component Placement performance of the ADC. A good design can be ruined with a bad circuit layout.
- Separate the analog and digital signals. To start, partition the board into analog and digital sections where the layout permits. Route digital lines away from analog lines to prevent digital noise from coupling back into analog signals.
- Fill void areas on signal layers with ground fill.
- Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground plane is cut or has other traces that block the current from flowing right next to the signal trace, the ground plane must find another path to return to the source and complete the circuit. If the ground plane is forced into a larger path, there is an increased chance of signal radiation. Sensitive signals are more susceptible to EMI interference.
- Use bypass capacitors on supplies to minimize high-frequency noise. Do not place vias between bypass capacitors and the active device. For best results, place the bypass capacitors on the same layer as close as possible to the active device.
- Consider the resistance and inductance of the routing. Input traces often have resistances that react with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source signal and the return current to minimize the inductance in the path.
- For best input combinations with differential measurements, use adjacent analog input lines such as AIN0, AIN1 and AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G (NPO) capacitors, which have stable properties and low-noise characteristics.
11.2 Layout Example
Figure 29. TLA2024 X2QFN Package
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
resources, tools and software, and quick access to order now. Table 9. Related Links
12.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments. I2C, NXP Semiconductors are trademarks of NXP Semiconductors. All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
TLA2021,TLA2022,TLA2024 SBAS846 – NOVEMBER 2017 www.ti.com Product Folder Links: TLA2021 TLA2022 TLA2024 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 17-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLA2021IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9AZ TLA2021IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9AZ TLA2021IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9AZ TLA2021IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9AZ TLA2022IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 19J TLA2022IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 19J TLA2022IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 19J TLA2022IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 19J TLA2024IRUGR Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ TLA2024IRUGR.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ TLA2024IRUGRG4 Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ TLA2024IRUGRG4.B Active Production X2QFN (RUG) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ TLA2024IRUGT Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ TLA2024IRUGT.B Active Production X2QFN (RUG) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 9IJ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1
www.ti.com 17-Jun-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLA2021IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 TLA2021IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 TLA2022IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 TLA2022IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 TLA2024IRUGR X2QFN RUG 10 3000 210.0 185.0 35.0 TLA2024IRUGRG4 X2QFN RUG 10 3000 210.0 185.0 35.0 TLA2024IRUGT X2QFN RUG 10 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE 1.6 1.4 2.1 1.9 0.40 0.34 0.05 0.00 2X 1.5 6X 0.5 10X 0.45 0.35 4X 0.25 0.15 2X 0.35 0.25 4X 0.3 0.2
0.1 MIN
(0.127) TYP X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 X 0.1) SYMM SYMM
0.1 C A B
0.05 C 0.05 C 0.05 C SCALE 7.500 50.000 OPTIONAL: SIDE WALL PIN DETAIL NOTE 3 AB C
www.ti.com EXAMPLE BOARD LAYOUT 6X (0.5) (R0.05) TYP
0.05 MAX
0.05 MIN
10X (0.6) 4X (0.25) (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 35X SEE SOLDER MASK DETAIL METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN 10X (0.6) 4X (0.25) 6X (0.5) (R0.05) TYP (1.8) (1.3) 4X (0.2) 2X (0.3) X2QFN - 0.4 mm max heightRUG0010B PLASTIC QUAD FLATPACK - NO LEAD 4220582/B 05/2025 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 35X SYMM SYMM
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