TL9879-1

F100325 NSC | Alldatasheet

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J i 8 National 8 Semiconductor ” Low Power Hex ECL-to-TTL Translator General Description Features The F100325 is a hex translator for converting F100K logic + ™ Pin/function compatible with F100125 levels to TTL logic levels. Differential inputs allow each cir- ™ Meets F100125 AC specifications cuit to be used as an inverting, non-inverting or differential _m 50% power reduction of the F100125 receiver. An internal reference voltage generator provides Differential inputs with built in offset Vpp for single-ended operation, or for use in Schmitt trigger Standard FAST® outputs applications. All inputs have S0k9 pull-down resistors. Soy ESD protection When the inputs are either unconnected or at the same y 42V to 5 7V fi potential the outputs will go low. = —4.2V to —5.7V operating range When used in single-ended operation the apparent input threshold of the true inputs is 20mV to 40mV higher (posi- tive) than the threshold of the complementary inputs. The Vee and Vrr_ power may be applied in either order. Ordering Code: see sections Logic Diagram Hy > o Do-Ds Data Inputs Do-Ds Inverting Data Inputs + > 0, Qp-Q5 Data Outputs B >- Qs oe Be >>- o TL/F/9670-4 Connection Diagrams 2 | 24-Pin DIP 28-Pin PCC 24-Pin Quad Cerpak a, - Dy 0; Dy Ves Op Dy Og 04 Ds Ds Vex Yap Oe ost 2b fae Feaapeaype yz 23} 24 23 22 21 20 19 O43 2d, 2 Ba, ie Ll 18} 5, Yn-4 21d, Vop OS Ba 0342 17-0, vm-45 201 bs ‘a Dec 5543 rr Vees Dee Veo“ 6 19,0; ac] Bec O44 15} Dp Vec7 18 Vee i522 Om as 145 Dp Qs 17 Yep o,f vm 3-46 13 FQ as 16}=D, 7-8 9 10 1112 aio 15-5, BOnRBae a tao, Dy Ds D5 Vees O5 Oy 5 Vim YmiYee Vee 2 o9-412 sha, TL/F/9879-3 TUF /9879-2 TU/F/9679-1 2-43

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3 Absolute Maximum Ratings Recommended Operating

= Above which the useful life may be impaired. (Note 1) Conditions {f Military/Aerospace specified devices are required, Case Temperature (To) please contact the National Semiconductor Sales Commercial OC to +85°C Office/Distributors for availability and specifications. Military —55°C to + 125°C Storage Temperature (Tstq) —65°C to + 150°C Supply Voltage (Vee) Maximum Junction Temperature (Ty) Commercial —5.7V to —4.2V Ceramic +175°C Military —5.7V to —4.2V Plastic + 150°C Vee Pin Potential to Ground Pin -7.0V to +0.5V Viti Pin Potential to Ground Pin +6.0V to -0.5V Input Voltage (DC) Veg to +0.5V Output Current (DC Output HIGH) —50 mA ESD (Note 2) =2000V Vee = —4.2V to —5.7V, Voc = GND, To = 0°C to + 85°C (Note 3) symbol | Parameter |_Min_ | Typ | Max__| Units | Conditions Vea __| Output Reterence Voltage = 1920 Wve = 21 mA Vin Single-Ended tnput Guaranteed HIGH Signal for All Inputs -1 —870 Vv HIGH Voltage 165 ™V | (with One Input Tied to Vag) Vit Single-Ended Input 1475 my_| Guaranteed LOW Signal for All Inputs LOW Voltage (with One Input Tied to Vgg) Vou | OutputtigHvoage | 25 | ||| to = =2.0mA_ | Vi = Vin van Vor__| Outputtowvortage | TT os |v i = 20ma | OFC Voie | inputVoltage Differential | 150° | | =| mv_| Required for Full Output Swing Vow | CommonModevotage | Veo-20| | vec-o5 | v | iT = -Ds = rm Input HIGH Current 350 wa | Yin = Vin (ax Do-Ds = Ves, Do-Ds = Vit (min) los Output Shor-Circuit Current |__-150 | | _—60 | mA | Voyr= GND" *Test one output at a time. Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to quarantee operation under “worst case” conditions. 2-44

Ceramic Dual-in-Line Package AC Electrical Characteristics 3 Vee = —4.2V to —5.7V, Voc = GND, VrT_ = +4.5V to +5.5V 8 teLH Propagation Delay CL = 15 pF tpLH Propagation Delay CL = 50 pF PCC and Cerpak AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = GND, VTL = +4.5V to +5.5V teLH Propagation Delay CL = 15 pF tpLH Propagation Delay CL = 50 pF tse.a Skew Gate to Gate ep TBD Teo PCC only (Note 1) Note 1: Gate to gate skew is defined as the difference in the propagation delays between each of the outputs. Truth Table L H L H L H L L L H H L Open Open L Vee Vee L L Ves L H Ves H VeB L H ij Vee H L H = HIGH Voltage Level L = LOW Voltage Level 2-45

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3 Military Version—Preliminary

• . . Symbol] __Parameter___[ min | Max [Unis] To | __—Conditions Notes Vas | Output Reference Voltage ere wal lves = —3 BA. Vee = —4.2V mV |~S5'C to + 125°C) ve os mA, Veg = —5.7V 1,2,3 Vin Input HIGH Voltage 1165 my | 55°C to + 125°C | SUaFanteed HIGH Signal for Allinputs | 4 4 4 (with One input Tied to Ves) Vit | Input LOW Voltage Guaranteed LOW Signal for All Inputs 183( 1476| mV 55°C to + 125°C (with One Input Tied to Vas) 1,2,3,4 Vi Output HIGH Voltage OC to + 125°C OH pu 9 mv Vin = Vin ten Vou [Outputowvottage | «| _08 | mv | ~s5°Cto + 125°C| Io, = 20mA VpirF | Input Voltage Differential —55°C to Required for Full Output Swing mV 1,2,3 +125°C Vom | Common Mode Voltage —55°C to mv +1250 1,2,3,4 hy Input HIGH Current O°C to +125°C_| Vin = Vin (Max): Do-Ds = Ves, pA aN i 1,2,3 in Input LOW Gurrent [oso |_| wa | —ss°cto +125°C| Vin = Vit avin, Do-Ds = Vow 1,2,3 los | Output Short Circuit _ ee sq| Vout = GND Current 150 MA | —55°C to + 125°C) +. One Output at a Time 12.3 lex] Output HIGH pA | —58Cto + 125°C] YOUT = 55¥ 4,2,3 Leakage Current tee | Vee Power Supply Curent | -a5 | —12 | ma | ~ss'Cto + 125°C 1.23 tm. [Vrr Power Supply Current] | 65. | mA | -55Cto +125C|Dp-Ds = Vas 1.2.3 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals —55°C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at -55°C, + 25°C, and + 125°C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table |) on each manufactured lot at — 55°C, + 25°C, and + 125°C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing Vox/VoL- Ceramic Dual-In-Line Package AC Electrical Characteristics Vee = —4.2V to —5.7V, Voc = GND, Vi7_ = +4.5V to +5.5V “nee | rvaneer | Se = Hae we = te _ [emt | conan wore tein Propagation Delay Cy = 50 pF 2-46

immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at +25°C, temperature only, Subgroup A9. Note 4: Not tested at + 25°C, + 125°C, and — 55°C temperature (design characterization data). FIGURE 1. Propagation Delay

1 Vee '

1 S/H ane 1-9 H

FIGURE 2. AC Test Circuit for 15 pF Loading

1 Veg '

7 U '

FIGURE 3. AC Test Circuit for 50 pF Loading Decoupling 0.1 4F from GND to Vcc, Veg and Vr.