TL972QPWRQ1

TL974-Q1 TI | Alldatasheet

Document overview

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Technical content

IN– IN+ TL971...D PACKAGE (TOP VIEW) VCC– VCC+ OUT2 IN2– IN2+ OUT1 IN1– IN1+ TL972...D OR PW PACKAGE (TOP VIEW) VCC+ VCC– OUT1 IN1– IN1+ IN2+ IN2– OUT2 OUT4 IN4– IN4+ IN3+ IN3– OUT3 TL974...PW PACKAGE (TOP VIEW) VCC–VCC+ NC – No internal connection TL971-Q1 TL972-Q1 TL974-Q1 www.ti.com SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 RAIL-TO-RAILOUTPUT,VERYLOW-NOISEOPERATIONALAMPLIFIERS Check forSamples: TL971-Q1,TL972-Q1,TL974-Q1 1FEATURES

• QualifiedforAutomotive Applications
• Rail-to-RailOutput VoltageSwing: ±2.4V atVCC = ±2.5V
• Very Low Noise Level:4 nV/√Hz
• Ultra-LowDistortion:0.003%
• High Dynamic Features:12 MHz, 5 V/μs
• OperatingRange: 2.7V to12 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78,Class II
• ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B) – 200-V Machine Model (A115-A) – 1500-V Charged-DeviceModel (C101)

APPLICATIONS

• PortableEquipment (CD Players,PDAs)
• PortableCommunications (CellPhones, Pagers)
• Instrumentationand Sensors
• ProfessionalAudio Circuits DESCRIPTION/ORDERING INFORMATION The TL97x familyofoperationalamplifiersoperatesatvoltagesas low as ±1.35V and featuresoutputrail-to-rail signalswing.The TL97x boastcharacteristicsthatmake them particularlywellsuitedforportableand battery- suppliedequipment.Verylownoiseand lowdistortioncharacteristicsmake them idealforaudiopreamplification. ORDERING INFORMATION (1)(2) TA ORDERABLE PART NUMBER TOP-SIDE MARKING TL971QDRQ1 TL971Q TL972QDRQ1 TL972Q –40°C to125°C TL972QPWRQ1 TL972Q TL974QPWRQ1 TL974Q (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VCC Supplyvoltagerange(2) 2.7V to15 V VID Differentialinputvoltage(3) ±1 V VIN Inputvoltagerange(4) VCC – – 0.3V toVCC+ + 0.3V D package(5) 8 pin 97°C/W θJA Package thermalimpedance,junctiontofreeair 8 pin 149°C/W PW package(5) 14 pin 113°C/W TJ Maximum junctiontemperature 150°C Tlead Maximum leadtemperature Soldering,10 seconds 260°C Tstg Storagetemperaturerange –65°C to150°C Human-Body Model (HBM) 2000 V ESD Electrostaticdischargeprotection Machine Model (MM) 200 V Charged-DeviceModel (CDM) 1500 V (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagevalues,exceptdifferentialvoltages,arewithrespecttonetworkgroundterminal. (3) Differentialvoltagesforthenoninvertinginputterminalarewithrespecttotheinvertinginputterminal. (4) The inputand outputvoltagesmust neverexceed VCC + 0.3V. (5) Package thermalimpedance iscalculatedinaccordancewithJESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VCC Supplyvoltage 2.7 12 V VICM Common-mode inputvoltage VCC – + 1.15 VCC+ – 1.15 V TA Operatingfree-airtemperature –40 125 °C

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www.ti.com SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

VCC+ = 2.5V,VCC – = –2.5V (unlessotherwisenoted) PARAMETER TEST CONDITIONS TA (1) MIN TYP MAX UNIT 25°C 1 4 VIO Inputoffsetvoltage mV Fullrange 6 αVIO Inputoffsetvoltagedrift VICM = 0 V,VO = 0 V 25°C 5 μV/°C IIO Inputoffsetcurrent VICM = 0 V,VO = 0 V 25°C 10 150 nA 25°C 200 750 IIB Inputbiascurrent VICM = 0 V,VO = 0 V nA Fullrange 1000 VICM Common-mode inputvoltage 25°C –1.35 1.35 V CMRR Common-mode rejectionratio VICM = ±1.35V 25°C 60 85 dB SVR Supply-voltagerejectionratio VCC = ±2 V to±3 V 25°C 60 70 dB AVD Large-signalvoltagegain R L = 2 kΩ 25°C 70 80 dB VOH High-leveloutputvoltage R L = 2 kΩ 25°C 2 2.4 V VOL Low-leveloutputvoltage R L = 2 kΩ 25°C –2.4 –2 V 25°C 1.2 1.4 Isource Outputsourcecurrent mA VOUT shortedto–2.5V Fullrange 1 25°C 50 80 Isink Outputsinkcurrent mA VOUT shortedto+2.5V Fullrange 25 25°C 2 2.8 ICC Supplycurrent(peramplifier) Unitygain,No load mA Fullrange 3.2 GBWP Gain bandwidthproduct f= 100 kHz,R L = 2 kΩ,C L = 100 pF 25°C 8.5 12 MHz 25°C 3.5 5 SR Slew rate AV = 1,VIN = ±1 V V/μs Fullrange 3 Φm Phase marginatunitygain R L = 2 kΩ,C L =100 pF 25°C 60 ° Gm Gain margin R L = 2 kΩ,C L =100 pF 25°C 10 dB Vn Equivalentinputnoisevoltage f= 100 kHz 25°C 4 nV/√Hz THD Totalharmonicdistortion f= 1 kHz,Av = –1,R L = 10 kΩ 25°C 0.003 % (1) FullrangeTA = –40°C to125°C Copyright© 2009–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TL971-Q1 TL972-Q1 TL974-Q1

0.0001 0.001 0.01 0.1 Frequency – Hz THD – % VCC = 5 V VIN = 1 Vrms Gain = -1 V/V R L = 2 k◊ R L = 10 k◊ kΩ kΩ 10 100 1k 10k 100k 0.001 0.01 0.1 Output Voltage – Vrms THD + Noise – % VCC = 2.7 V f = 1 kHz Gain = -1 V/V R L = 2 k R L = 10 kkΩkΩ -40 -30 -20 -10 f – Frequency – Hz Gain – dB -200 -160 -120 -80 -40 120 160 200 Phase – ° VCC = 2.7 V R L = 10 k© C L = 100 pF  M = 63.7° fO = 8.4 MHz Φ M 1k 10k 100k 1M 10M 100M kΩ -40 -30 -20 -10 f – Frequency – Hz Gain – dB -200 -160 -120 -80 -40 120 160 200 Phase – ° VCC = 5 V R L = 10 k© C L = 100 pF □ M = 64.4° fO = 17.3 MHz Φ 1k 10k 100k 1M 10M 100M kΩ TL971-Q1 TL972-Q1 TL974-Q1 SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS GAIN AND PHASE GAIN AND PHASE vs vs FREQUENCY FREQUENCY TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION + NOISE vs vs FREQUENCY OUTPUT VOLTAGE

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Output Current – mA Gain Bandwidth Product – MHz 2 4 6 8 10 12 14 Supply Voltage – V Gain Bandwidth Product – MHz C L = 30 pF C L = 130 pF C L = 250 pF 0.0001 0.001 0.01 0.1 Output Voltage – Vrms THD + Noise – % VCC = 5 V f = 1 kHz Gain = -1 V/V R L = 2 k□ R L = 10 k□ kΩ kΩ 100 f – Frequency – Hz Input Voltage Noise – nV/sqrt(Hz) VCC = 10 V R S = 100© A V = 40 dB nV/ √Hz 10 100 1k 10k 100k Ω TL971-Q1 TL972-Q1 TL974-Q1 www.ti.com SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION + NOISE INPUT VOLTAGE NOISE vs vs OUTPUT VOLTAGE FREQUENCY GAIN BANDWIDTH PRODUCT GAIN BANDWIDTH PRODUCT vs vs OUTPUT CURRENT SUPPLY VOLTAGE Copyright© 2009–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TL971-Q1 TL972-Q1 TL974-Q1

Supply Voltage – V Gain Margin – dB C L = 30 pF C L = 130 pF C L = 250 pF 1 µs /div

0.25 V/div

Output Current – mA Phase Margin – ° 100 2 4 6 8 10 12 14 Supply Voltage – V Phase Margin – ° C L = 30 pF C L = 130 pF C L = 250 pF TL971-Q1 TL972-Q1 TL974-Q1 SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) PHASE MARGIN PHASE MARGIN vs vs OUTPUT CURRENT SUPPLY VOLTAGE GAIN MARGIN vs SUPPLY VOLTAGE INPUT RESPONSE

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Supply Voltage – V Slew Rate – V/µs Rise Fall 0.01 0.1 100 Frequency – Hz Output Impedance – ℵ VCC = 5 V VCC = 2.7 V 100 1k 10k 100k 1M Ω 100 Frequency – Hz PSRR – dB 1k 10k 100k 1M 0.001 0.01 0.1 Output Current – mA Output Voltage to Supply Voltage – V VIN-= -0.2 V VIN+ = 0 V VCC = 5 VVCC = 2.7 V 0.01 0.1 1 10 TL971-Q1 TL972-Q1 TL974-Q1 www.ti.com SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) POWER-SUPPLY RIPPLE REJECTION OUTPUT VOLTAGE vs vs FREQUENCY OUTPUT CURRENT OUTPUT IMPEDANCE SLEW RATE vs vs FREQUENCY SUPPLY VOLTAGE Copyright© 2009–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TL971-Q1 TL972-Q1 TL974-Q1

SLOS632A –MARCH 2009–REVISED SEPTEMBER 2012 www.ti.com

REVISION HISTORY

Changes from Original(March 2009)toRevisionA Page

• Changed VOUT = ±2.5V toVOUT shortedto-2.5V forIsource,and changed VOUT = ±2.5V toVOUT shortedto+2.5V

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TL971QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL971Q TL971QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL971Q TL972QDRQ1 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL972Q TL972QDRQ1.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL972Q TL972QPWRQ1 Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL972Q TL972QPWRQ1.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL972Q TL974QPWRQ1 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 125 TL974Q TL974QPWRQ1.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TL974Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL971-Q1, TL972-Q1, TL974-Q1 :

• Catalog : TL971, TL972, TL974 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL972QDRQ1 SOIC D 8 2500 353.0 353.0 32.0 TL972QPWRQ1 TSSOP PW 8 2000 356.0 356.0 35.0 TL974QPWRQ1 TSSOP PW 14 2000 356.0 356.0 35.0 TL974QPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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