TL971 TI1 | Alldatasheet
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Sample & Buy T echnical Documents Tools & Software Support & Community TL971,TL972,TL974 SLOS467H –OCTOBER 2006–REVISED JANUARY 2015 TL97xOutputRail-To-RailVery-Low-NoiseOperationalAmplifiers
1 Features 3 Description
The TL97x family of single, dual, and quad 1• Rail-to-Rail Output Voltage Swing: operational amplifiers operates at voltages as low as±2.4 V at VCC = ±2.5 V ±1.35 V and features output rail-to-rail signal swing.• Very Low Noise Level: 4 nV/√Hz The TL97x boast characteristics that make them
- Ultra-Low Distortion: 0.003% particularly well suited for portable and battery- supplied equipment. Very low noise and low distortion• High Dynamic Features: 12 MHz, 5 V/μs characteristics make them ideal for audio• Operating Range: 2.7 V to 12 V preamplification.
- Latch-Up Performance Exceeds 100 mA Per The TL971 is housed in the space-saving 5-pin SOT-JESD 78, Class II 23 package, which simplifies board design because• ESD Performance Tested Per JESD 22 of the ability to be placed anywhere (outside – 2000-V Human-Body Model dimensions are 2.8 mm × 2.9 mm). – 1500-V Charged-Device Model Device Information(1) PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)2 Applications SOIC (8) 4.90 mm × 3.90 mm• Portable Equipment TL971 SOT-23 (5) 2.80 mm × 2.90 mm – Music Players MSOP (8) 3.00 mm × 3.00 mm – Tablets PDIP (8) 9.60 mm × 6.40 mm TL972– Cell Phones SOIC (8) 4.90 mm × 3.90 mm
- Instrumentation and Sensors TSSOP (8) 3.00 mm × 4.40 mm
- Professional Audio Circuits PDIP (14) 19.30 mm × 6.40 mm TL974 SOIC (14) 8.60 mm × 3.90 mm TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.
4 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL971,TL972,TL974 SLOS467H –OCTOBER 2006–REVISED JANUARY 2015 www.ti.com Table of Contents
5 Revision History
Changes from Revision G (May 2012) to Revision H Page
- Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision F (December 2009) to Revision G Page
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Product Folder Links: TL971 TL972 TL974
TL971...DBV PACKAGE (TOP VIEW) OUT VCC– IN+ IN– VCC+ 1 NC OUT NC NC IN– IN+ TL971...D PACKAGE (TOP VIEW) VCC– VC + C OUT2 IN2– IN2+ OUT1 IN1– IN1+ TL972...D, DGK, P, OR PW PACKAGE (TOP VIEW) VCC+ VCC– OUT1 81
2 OUT2
IN2–IN1+ IN1– TL972...DRG PACKAGE (TOP VIEW) VCC+ VCC– OUT1 IN1– IN1+ IN2+ IN2– OUT2 OUT4 IN4– IN4+ IN3+ IN3– OUT3 TL974...D, N, OR PW PACKAGE (TOP VIEW) VCC–VCC+ NC – No internal connection TL971,TL972,TL974 www.ti.com SLOS467H –OCTOBER 2006–REVISED JANUARY 2015
6 Pin Configuration and Functions
TL971 TL971 TL972 TL974 TYPE DESCRIPTION NAME D, DGK, P,DBV D DRG D, N, PWPW IN+ 3 3 — — — I Noninverting input IN– 4 2 — — — I Inverting input IN1+ — — 3 3 3 I Noninverting input IN1– — — 2 2 2 I Inverting input IN2+ — — 5 5 5 I Noninverting input IN2– — — 6 6 6 I Inverting input IN3+ — — — — 10 I Noninverting input IN3– — — — — 9 I Inverting input IN4+ — — — — 12 I Noninverting input IN4– — — — — 13 I Inverting input NC — 5 — — — — No Connect OUT 1 6 — — — O Output OUT1 — — 1 1 1 O Output OUT2 — — 7 7 7 O Output OUT3 — — — — 8 O Output OUT4 — — — — 14 O Output VCC+ 5 7 8 8 4 - Positive supply VCC– 2 4 4 4 11 - Negative supply Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TL971 TL972 TL974
TL971,TL972,TL974 SLOS467H –OCTOBER 2006–REVISED JANUARY 2015 www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range 2.7 15 V VID Differential input voltage(2) ±1 V V VIN Input voltage range(3) VCC– – 0.3 VCC+ + 0.3 V TJ Maximum junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Differential voltages for the noninverting input terminal are with respect to the inverting input terminal. (3) The input and output voltages must never exceed VCC + 0.3 V.
7.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification JESD22-C101, 1500all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC Supply voltage 2.7 12 V VICM Common-mode input voltage VCC– + 1.15 VCC+ – 1.15 V TA Operating free-air temperature –40 125 °C
7.4 Thermal Information
THERMAL METRIC(1) TL971 TL972 TL974 D(2) DBV(2) D(2) DGK(3) DRG(3) P(2) PW(2) D(2) N(2) PW(2) UNIT
8 PINS 5 PINS 8 PINS 14 PINS
RθJA impedance, 97 206 97 172 44 85 149 86 80 113 °C/W junction to free air (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). (2) Package thermal impedance is calculated in accordance with JESD 51-7. (3) Package thermal impedance is calculated in accordance with JESD 51-5.
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Product Folder Links: TL971 TL972 TL974
7.5 Electrical Characteristics
7.6 Typical Characteristics
Figure 2. Gain And Phase vs FrequencyFigure 1. Gain And Phase vs Frequency
Figure 3. Total Harmonic Distortion vs Frequency Figure 4. Total Harmonic Distortion + Noise vs Output Figure 6. Input Voltage Noise vs FrequencyFigure 5. Total Harmonic Distortion + Noise vs Output Figure 8. Gain Bandwidth Product vs Supply Voltage Figure 7. Gain Bandwidth Product vs Output Current
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0.25 V/div
Figure 10. Phase Margin vs Supply VoltageFigure 9. Phase Margin vs Output Current Figure 12. Input ResponseFigure 11. Gain Margin vs Supply Voltage Figure 14. Output Voltage vs Output Current Figure 13. Power-Supply Ripple Rejection vs Frequency
Figure 15. Output Impedance vs Frequency Figure 16. Slew Rate vs Supply Voltage
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1.4 mA TL971,TL972,TL974 www.ti.com SLOS467H –OCTOBER 2006–REVISED JANUARY 2015
8 Detailed Description
8.1 Overview
The TL97x family of operational amplifiers operates at voltages as low as ±1.35 V and features output rail-to-rail signal swing. The TL97x boast characteristics that make them particularly well suited for portable and battery- supplied equipment. Very low noise and low distortion characteristics make them ideal for audio preamplification. The TL97x family comes in single, dual, and quad operational amplifier packages of varying sizes. The TL971 is housed in the space-saving 5-pin SOT-23 package, which simplifies board design because of the ability to be placed anywhere (outside dimensions are 2.8 mm × 2.9 mm).
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. The TL97x devices have a 5 V/μs slew rate.
8.3.2 Unity-Gain Bandwidth
The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without greatly distorting the signal. The TL97x devices have a 12-MHz unity-gain bandwidth. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TL971 TL972 TL974
TL971,TL972,TL974 SLOS467H –OCTOBER 2006–REVISED JANUARY 2015 www.ti.com Feature Description (continued)
8.3.3 Low Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The TL97x devices have a very low THD of 0.003% meaning that they will add little harmonic distortion when used in audio signal applications.
8.3.4 Operating Voltage
The TL97x devices are fully specified and ensured for operation from 2.7 V to 12 V. In addition, many specifications apply from –40°C to 125°C.
8.4 Device Functional Modes
The TL97x devices are powered on when the supply is connected. Each of these devices can be operated as a single supply operational amplifier or dual supply amplifier depending on the application.
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Product Folder Links: TL971 TL972 TL974
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Typical Application
as necessary to the output load. Figure 17. Voltage follower schematic
9.1.1 Design Requirements
- Input at positive Terminal
- Output range of 0 V to 12 V
- Input range of 0 V to 12 V
- Short-circuit feedback to negative input for unity gain
9.1.2 Detailed Design Procedure
9.1.2.1 Output Voltage Swing
rails. For this amplifier, the output voltage must be within ±12 V.
9.1.2.2 Supply and Input Voltage
amplifier to maintain linearity for the full range of inputs.
9.1.3 Application Curves for Output Characteristics
Figure 18. Output Voltage vs Input Voltage Figure 19. Current Drawn by Input of Voltage Follower (IIO) Figure 20. Current Dawn from Supply (ICC)
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10 Power Supply Recommendations
The TL97x devices are specified for operation from 2.7 to 12 V; many specifications apply from -40 °C to 125 °C.
11 Layout
11.1 Layout Guidelines
- Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
- Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, SLOA089.
- To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
- Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Example.
- Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
- Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Figure 21. Operational Amplifier Schematic for Noninverting Configuration
Figure 22. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 1. Related Links
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 25-Jan-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL971ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 TL971IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 TL971IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z971 TL972ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL972IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TSA TL972IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL972IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL972IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TL972IP TL972IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TL972IP TL972IPW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL972IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL972IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z972 TL974ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL974I TL974IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL974I TL974IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL974I TL974IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TL974IN TL974INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TL974IN
www.ti.com 25-Jan-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL974IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z974 TL974IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 Z974 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
www.ti.com 25-Jan-2015 Addendum-Page 3 OTHER QUALIFIED VERSIONS OF TL971, TL972, TL974 :
- Automotive: TL971-Q1, TL972-Q1, TL974-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL971IDR SOIC D 8 2500 340.5 338.1 20.6 TL972IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TL972IDR SOIC D 8 2500 340.5 338.1 20.6 TL972IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL974IDR SOIC D 14 2500 333.2 345.9 28.6 TL974IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2015 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP6.6 6.2
1.2 MAX
6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8
0.1 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT (5.8)
0.05 MAX
0.05 MIN
8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X
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