TL8857F TOSHIBA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
TENTATIVE TOSHIBA CCD ANALOG PROCESSOR INTEGRATED CIRCUIT SILICON MONOLITHIC NTSC SKEW CORRECTION IC FOR VCR The TL8857F is the skew correction IC for the search playback signal of NTSC SP mode by 4 head PAL cylinder. This skew is made by the difference of 1H length on tape between NTSC (525 lines) and PAL (625 lines) PAL: 625 lines=2H NTSC : 525 li = (2/62 25 = 1.68H SN ‘| TSC 525 lines = (2/625) x 525 = 1.68! ant Difference (Skew) = 2H - 1.68H =0.32H RAS WS TL8857F corrects the skew by changing the delay time of W a CCD delay lines. SOP16-P-300-1.27 FEATURES Weight : 0.2g (Typ.) @ CCD DELAY LINES NTSC 0.32H/OH DELAY LINES (Apply to both 3.58NTSC and 4.43NTSC) @ SYNC TIP CLAMP CIRCUIT @ CCD DRIVE CIRCUIT, SAMPLE AND HOLD CIRCUIT @ 2 input SW (For the through mode) @ 2 input SW is controlled by Pin 13 Low =Through (EE) mode High = Skew (correction) mode @ When Pin 13 is Low the CCD clock driver is off and the CCD output (Pin 8) is fixed to DC 980508EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Sire products described in this document are subject to foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or ‘other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-11-20 1/13
@ The CCD delay time is 2 mode. 0H and 0.32H, controlled by Pin 14. Low =0H High =0.32H @ PLL frequency multiplier is built in. 3.58NTSC and 4.43NTSC are selected by Pin 15. Low = 4.43NTSC High =3.58NTSC @ Input signal is sampling by 4 times (3.58NTSC) or 3 times (4.43NTSC) of subcarrier frequency, generated by internal PLL multiplier. @ 5V single power supply. @ As all supporting circuit for CCD such as CCD driver, bias generators and output amplifiers are built in, minimum external parts are needed. @ The output signal at pin 8 is inverted. 1998-11-20 2/13
ap Sb & = Ey sf! g 3 s 5 « 2 Jaq fel oA 2] 3§ 5 4 ae Yura ai ea | ; G) ry 5 dooce eae PL. Ey /\\ U0ze ato g g) ]e} ]e ei 8 q : - comm Oz ° sa s4* 3 AN v4 z fs a @ |e Cy 4 ° < a z |
Vss1 M2 isfisw; aa3fase Voor 3 yafsw2 on JoszH Voo2 4 13 sw; cc ['cco(skew) Vss2 5 12 BI ccdn VeG 6 11 Bi Vin2 Vos W7 10 fl Your ccDour 8 9B Mins MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage [vp [| 6 Input Voltage -0.3~Vpp + 0.3 Storage Temperature =55~150 (Note 1) Ta=60°C (Note 2) Frost isn’t to stick to the condition.
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTIC (Ta = 25°C, Vpp =5.0V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Operating Supply Voltage Vpp 475 5.0 Vv Supply Current [op | — | [a0 [130 | 780 | ma | Output DC Level out | SKEW, 3.58NTSC mode Vin =No signal [a5 20] 25 | CLOCK = 3.579545MHz [ 25] 29] 3.3 | 300mVp- [oa [oa] 12 | Pin 13, 14, 15="Hi" [oa [oa 12 | Pin DC Level =5V DC Input [roa [15 21 | PLLFIL [os 15] 25 | CLOCK IN v [80 | 700 | 720 | as WH [3sp— | | Switch Input Select SsW2iL [| — | — |] 15] Level Pin Voltage [3ssp— | | Swit [= | — | 15 | Wath [asp T= | 1998-11-20 4/13
ELECTRICAL CHARACTERISTICS (3.58NTSC mode, CCD part) AC CHARACTERISTIC (Ta = 25°C, Vpp =5.0V, clock = 3.579545MHz, 0.3Vp-p, $2 =2, $3=2, S4=1, S6=1, Sg=1) sym-|TEST CHARACTERISTIC BOL | CIR- TEST CONDITION Typ. | MAX. | UNIT CuIT Input Level [int [i PO 2 ie $1=1, $7=2, Sg=1, Voltage Gain VIN = 15.625kHz, (Fig.2-b) $1=1, $7=2, Sg=1, Frequency Characteristic Vin = 15.625kHz/ Gre 4.5MHz, 0.6Vp-p $5 = 1(0.32H) -2 (Fig.2-b) $1=1, $7=1, Sg=1, Differential Gain Vin =5 step signal, % Y = 1401RE = 1.0Vp.p, C=40IRE Differential Phase DG = (COmax - COmin) /COmin $5 = 1 (0.32H) 7 (Fig.5) S5=2] 37 43 L 5/¥2 ot Linearity S19 =2, $41=1 (0.32H) % inearity VIN=5 step signal, S5=2] 56 1.0Vp-p (Fig.2-a, Fig.4) (OH) ly Ma Yabo (0.32H) VIN = 15.625kHz, 0.6Vp.p (ony | 10 | 25° Output Impedance (Fig.2-b) a Z9 = (V1 -V2)/V2 x 1000 S5=1 250 V1: Sg=1, Vz : Sg=2 (0.32H) S5=2 $11=2 = ™mVems. (4fsc) 14.3 Vin =No signal S5=1 Ineo sig (0.324) S5=2 $41 =2 — Vrms: (fc) 3.58 Vin =No signal S5=1 2 IN=No sig (0.32) 7998-11-20 5/13
ELECTRICAL CHARACTERISTIC (4.43NTSC mode, CCD part) AC CHARACTERISTIC (Ta =25°C, Vpp =5.0V, clock = 4.43361875MHz, 0.3Vp-p, $2 =2, $3=2, S4=2, S6=1, Sg=1) sym.] TEST CHARACTERISTIC “| CIR- TEST CONDITION Typ. | MAX. | UNIT BOL |curt Input Level Ta $1 =2, $7=2, Sg=1, Voltage Gain VIN = 15.625kHz, Gva 0.6Vp-p $5 =1(0.32H) (Fig.2-b) $1 =2, $7=2, Sg=1, Frequency Characteristic VIN = 15.625kHz/ Gra 4.5MHz, 0.6Vp-p $5 =1(0.32H) -2 (Fig.2-b) $1 =2, $7=1, Sg=1, Differential Gain Vin =5 step signal, % Y = 1401RE = 1.0Vp.p, C=40IRE Differential Phase DG = (COmax - COmin) /COmin $5 = 1 (0.32H) 7 (Fig.5) || °| 3 Linearity Vin =5 step signal, S522 % 1.0Vp. = re pow | | | Fig.2-a, Fig.4) Ly2 (Fig ig.4) v4 /Y2| S5a1 (0.32H) VIN = 15.625kHz, 0.6Vp-p (ony | 10 | 250 Output Impedance Zo2 (Fig.2-b) a Zo =(Vq - V2) /V2 x 1000 S5=1) 99 | 250 Clock input level [Vaf a] —S—SS—~*d—S | 08 | 07 | oe | S5=2 Clock Leak Lee | fet=255777 89°" S105" | ony |= [| | (3fsc) 13.3 Vi No signal S5=1 rms IN=No si9 (0.324) Clock Leak bse ‘. 5 TEA 9951 105% | OH) mv (fs) 4.43 Viv =No signal S5=1 >) o™ IN=No si9 (0.32H) 1998-11-20 6/13
ELECTRICAL CHARACTERISTIC Commonness (SW part) AC CHARACTERISTIC (Ta = 25°C, Vpp =5.0V, clock = 3.579545MHz or 4.43361875MHz, 0.3Vp-p, $1=2, $q4=1 or 2, S5=1 or 2, Sg=2, S49 =1) sym-|TEST CHARACTERISTIC CIR- TEST CONDITION TYP. | MAX. | UNIT BOL CUIT input Level 2 Vv S11=2 (Pin 11Pin 10) an Through Mode Voltage Vin = 15.625kHz, Sv6 (Fig. 6b) (Pin 9-sPin 10) 15) -0.5 Through Mode S11=2 (Pin 11Pin 10) . Frequency Characteristic Vin = 15.625kH2/ fth2 4.5MHz, 1.2Vp.p |S6= 1, S2=2, S3=1] _4 4 (Fig.6-b) (Pin 9Pin 10) S7=1,S9=1, [oo -> son1, saz 6 =2, S2=1, $3=2 pss $1153 (Pin 11Pin 10) 3 Differential Gain VIN=5 step % signal, 2.0Vp-p S6=1, S2=2, $3=1 3 Y = 1401RE = (Pin 9—>Pin 10) 1.0Vp-p, C= 40IRE DG = (COmax - (Pin 11—>Pin 10) Differential Phase COmin)/ comin S6=1, $2=2, $3=1 3 (Fig.5) (Pin 9Pin 10) a 56=2, S2=1, $3=2 j eet s/|(Pin 11 in 10) 37 “3 % Sq=1 7 4 37 43 A - (Pin 9—Pin 10) Linearity Vin =5 step Sg=2, Sp=1, Sg=2 ignal, =2, $2=1, $3= $7=2, $41=1 Vin =15.625kHz, |Sg=2, S2=1, $3=2 1.2Vp-p (Pin 11Pin 10) 100 | 250 (Fig.6-b) Output Impedance 29 =(V4-V2)/ a V2x 1000 S6=1, $2=2, $3=1 250 V1: Sg=1, (Pin 9Pin 10) V2 : Sg=2 1998-11-20 7/13
Vin 3: Ss S - 8 Ir It ly 7 102 102 192 Sy 82 $3 12 Ne ofo Ae 7OOKD $7.4 42 Yb ase oa sew weyee thse 1bss 1b56 100kQ $7.2 gs] 3] 25] tin S aa] of el B Es go a! Se +2 ve s : ca elt of oe V Tt OU FAalealed allay” lock PUL 1: ee pet £E | g a Bk x 8: ES yo S ° is BHF 100uH TA EB STS aod Tout ae & Vad b]6 192 Sg sv g 2 50002) 3° _ 89 a VECTOR wee ars Fa SCOPE # T a Fig.1 1998-11-20 8/13
(a) 5 step staircase signal (b) Sine wave input (Clamp Operation) (0.6Vp-p input) % a iooirey| S Seateeta eet oe Ee a) —2 A. (401RE) ° a eS ' 63.5 ys : Fig.2
5 STEP STAIRCASE SIGNAL
| Chroma 4.43MHz (401RE) wud----_ 3.58NHz (401RE) l (1001RE) |g (401RE) 1 ro r 63.5ps 1 Fig.3 LINEARITY TEST SIGNAL OUTPUT CHROMA DIFFERENTIAL GAIN s -p---- ‘4 8 g as a Sa Y2 7 Fig.4 Fig.5 TOO 9920S
(a) 5 step staircase signal (b) Sine wave input (Clamp operation) (1.2Vp-p input) % a iooirey| S Sees nee Daan a] —--- MR. (401RE) . a en nent n ence teenie ieieineceee Clamp DC f 63.5 ys : Fig.6 | Chroma 4.43MHz (40IRE) | (soo1re)| 9 g (a01RE) | poms ! 63.5 ps 1 Fig.7 1998-11-20 10/13
— sv Vp-p ¢ 3 a as - Fe Video in © 1a al \\ be DC=1.7V ov -----b--- ef Ts a8 Video S tl BF Fe out = I 2 a70 pF 750) ° EEJCCD (Skew) 1000 OHJ0.32H ° wl ° oe oo « “ ¥ 3 “yy ye dP ° ai hee VV a Sehets y= OU od ltl 3)|3||* BoC OA Shs a" ip S/H SIH Siete Vss(0) Vp (0) Vop‘A)_ Vss (A) OR ON ONE ON OME ONION) sq Se" — = & S : =} 3 ele LS Su a 3S ° ate Tonk [100K4 TS i sh FE = 8b ae 7s To ae g ™ 3 += 8 neq 8 gh GH S TTT 7998-11-20 11/13
This device is electrostatic sensitive device, so care must be taken in handling and storage to prevent deterioration or damage by means of shorting electrically all pins with use of aluminum foil or conductive mat. Even in assembled on board, it is necessary to protect against surge or inductive noise from input, output and power supply line. 1998-11-20 12/13
SOP16-P-300-1.27 Unit : mm 16 9 HHHHHHEHE ») | ba all = ) | g 8 | wo) oN 2 4 8 .7O5T YP. 4, 1 J) o-70s fests grasa 22 250) 10.8MAX 10.3+0.2 Nx 2,3 38 eT $7 = = 38 Ss eo # o 0.80.2 Weight : 0.2g (Typ.) 1998-11-20 13/13