TL720M05QKVURQ1M3

TL720M05-Q1_V01 TI | Alldatasheet

Document overview

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Technical content

TL720M05-Q1 Automotive, 500mA, 40V, Low-Dropout Voltage Regulator

1 Features

• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA – Junction temperature: –40°C to +150°C, TJ
• Input voltage range: – Legacy chip: 5.5V to 42V (45V absolute max) – New chip: 3.0V to 40V (42V absolute max)
• Maximum output current: 500mA (new chip)
• Output voltage accuracy: – Legacy chip: ±2.0% (across line, load, and temperature) – New chip: ±1.15% (across line, load, and temperature)
• Low dropout voltage: – Legacy chip: 500mV (max) at 300mA – New chip: 400mV (max) at 315mA
• Low quiescent current: – Legacy chip: 100µA (typ) at IOUT = 1mA – New chip: 17µA (typ) at light loads
• Excellent line transient response (new chip): – ±2% VOUT deviation during cold-crank – ±2% VOUT deviation (1V/µs VIN slew rate)
• Stable with a 2.2µF or larger capacitor (new chip)
• Reverse-polarity protection (legacy chip)
• Packages: – 3-pin TO-252 (KVU) – 3-pin DDPAK/TO-263 (KTT) – 20-pin HTSSOP (PWP) (legacy chip)

2 Applications

• Reconfigurable instrument clusters
• Body control modules (BCM)
• Always-on battery-connected applications: – Automotive gateways – Remote keyless entries (RKE) Line Transient Response (3V/µs VIN Slew Rate) (New Chip)

3 Description

The TL720M05-Q1 is a low-dropout linear regulator designed to connect to the battery in automotive applications. The device has an input voltage range extending to 40V (new chip). This range allows the device to withstand transients (such as load dumps) that are anticipated in automotive systems. With only a 17µA quiescent current at light loads, the device is designed for powering always-on components. Examples of such components are microcontrollers (MCUs) and controller area network (CAN) transceivers in standby systems. The device (new chip) has a state-of-the-art transient response that allows the output to quickly react to changes in load or line. For example, during cold- crank conditions. Additionally, the device has a novel architecture that minimizes output overshoot when recovering from dropout. During normal operation, the device has a tight DC accuracy of ±1.15% over line, load, and temperature (new chip). The device also incorporates a number of internal circuits for protection against overload and overtemperature. The legacy chip also provides protection against reverse polarity. The TL720M05-Q1 is available in thermally conductive packaging to allow the device to efficiently transfer heat to the circuit board.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TL720M05-Q1 KTT (TO-263, 3) 10.16mm × 15.24mm KVU (TO-252, 3) 6.6mm × 10.11mm PWP (HTSSOP, 20) (legacy chip) 6.5mm × 6.4mm (1) For more information, see the Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TL720M05-Q1 IN OUT GND Typical Application Schematic (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

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SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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4 Pin Configuration and Functions

Figure 4-1. KTT Package, 3-Pin TO-263 (Top View) OUT GND IN GND Figure 4-2. KVU Package, 3-Pin TO-252 (Top View) Thermal Pad NC NC NC OUT NC NC NC GND NC NC NC IN NC NC NC NC NC NC NC NC Figure 4-3. PWP Package(1), 20-Pin HTSSOP With PowerPAD (Top View) Table 4-1. Pin Functions PIN TYPE(2) DESCRIPTION NAME TO-263 TO-252 HTSSOP (Legacy Chip) GND 2 2 8 O Ground. Internally connected to heat sink. IN 1 1 19 I Input power-supply voltage pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the input of the device as possible 20 — Not connected. OUT 3 3 4 O Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground. See the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible. (1) NC = No internal connection. (2) I = input, O = output. www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TL720M05-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VIN Supply input voltage (for legacy chip) –42 45 V Supply input voltage (for new chip) –0.3 42 VOUT Regulated output voltage (for legacy chip) –1.0 40 Regulated output voltage (for new chip) –0.3 VIN + 0.3 V(2) Current Maximum output Internally limited A Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability. (2) The absolute maximum rating is VIN + 0.3V or 20V, whichever is smaller

5.2 ESD Ratings

(Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 VCharged-device model (CDM), per AEC Q100-011 All pins N/A ±500 Corner pins N/A ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VIN Supply input voltage (for legacy chip) 5.5 42 VSupply input voltage (for new chip) 3 40 VOUT Output voltage 5.0 IOUT Output current (for legacy chip) 0 400 mA Output current (for new chip) 0 500 COUT Output capacitor (for legacy chip)(2) 22 µFOutput capacitorr (for new chip)(2) 2.2 220 CIN Input capacitor(1) 1 ESR Output capacitor ESR requirements (for legacy chip) 0.001 5 Ω Output capacitor ESR requirements (for new chip) 0.001 2 TJ Operating junction temperature –40 150 °C (1) For robust EMI performance the minimum input capacitance is 500nF. (2) Effective output capacitance of 1µF minimum required for stability. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) (2) TL720M05-Q1 UNIT KVU (TO-252-3) KTT (TO-263-3) PWP (HTSS OP-20) Legacy Chip New Chip Legacy Chip New Chip Legacy Chip RθJA Junction-to-ambient thermal resistance 45.3 30 34.2 22.6 39.3 °C/W ψJT Junction-to-top characterization parameter 2.8 2.6 6 2.0 0.6 °C/W (1) The thermal data is based on the JEDEC standard high K profile,JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper. The copper pad is soldered tothe thermal land pattern. Also, correct attachment procedure must be incorporated. (2) For more information about traditional and new thermal metrics,see the Semiconductor and IC PackageThermal Metrics application report.

5.5 Electrical Characteristics

specified at TJ = –40°C to +150°C, VIN = 13.5V, IOUT = 0mA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER Test Conditions MIN TYP MAX UNIT VOUT Regulated output (for legacy chip) VIN = 6V to 28V, IOUT = 5mA to 400mA 4.9 5.0 5.1 V VIN = 6V to 40V, IOUT = 5mA to 400mA 4.9 5.0 5.1 Regulated output (for new chip) VIN = VOUT + 1V to 40V, IOUT = 100µA to 450mA, TJ = 25ºC(1) –0.85 0.85 VIN = VOUT + 1V to 40V, IOUT = 100µA to 500mA, TJ = 25ºC(1) –0.85 0.85 VIN = VOUT + 1V to 40V, IOUT = 100µA to 450mA(1) –1.15 1.15 VIN = VOUT + 1V to 40V, IOUT = 100µA to 500mA(1) –1.15 1.15 ΔVOUT(ΔIOUT) Load regulation (for legacy chip) IOUT = 5mA to 400mA 15 30 mV Load regulation (for new chip) VIN = VOUT + 1V, IOUT = 100µA to 450mA 0.425 % ΔVOUT(ΔVIN) Line regulation (for legacy chip) VIN = 8V to 32V, IOUT = 5mA –15 5 15 mV Line regulation (for new chip) VIN = VOUT + 1V to 40V, IOUT = 100µA 0.2 % ΔVOUT Load transient response settling time (for new chip)(2) tR = tF = 1µs; COUT = 10µF 100 µs ΔVOUT Load transient response overshoot, undershoot (for new chip)(2) tR = tF = 1µs; COUT = 10µF IOUT = 150mA to 350mA –2% %VOUTIOUT = 350mA to 150mA 10% IOUT = 0mA to 500mA –10% IQ Quiescent current (for legacy chip) IQ = IIN – IOUT IOUT = 1mA TJ = 25ºC 100 220 µA TJ ≤ 85ºC 100 220 IOUT = 250mA 5 10 mA IOUT = 400mA 12 22 Quiescent current (for new chip) VIN = VOUT + 1V to 40V, IOUT = 0mA, TJ = 25ºC(3) 17 21 µAVIN = VOUT + 1V to 40V, IOUT = 0mA(3) 26 IOUT = 500µA 35 VDO Dropout voltage (for legacy chip) IOUT = 300mA 250 500 mV Dropout voltage (for new chip) IOUT ≤ 1mA, VIN = VOUT(NOM) x 0.95 46 IOUT = 315mA, VIN = VOUT(NOM) 275 400 IOUT = 450mA, VIN = VOUT(NOM) 360 525 IOUT = 500mA, VIN = VOUT(NOM) 390 575 VUVLO(RISING) Rising input supply UVLO (for new chip) VIN rising 2.6 2.7 2.82 V VUVLO(FALLING) Falling input supply UVLO (for new chip) VIN falling 2.38 2.5 2.6 V www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TL720M05-Q1

5.5 Electrical Characteristics (continued)

specified at TJ = –40°C to +150°C, VIN = 13.5V, IOUT = 0mA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted); typical values are at TJ = 25°C. PARAMETER Test Conditions MIN TYP MAX UNIT VUVLO(HYST) V UVLO(IN) hysteresis (for new chip) 230 mV ICL Output current limit (for legcacy chip) VIN = VOUT + 1V, VOUT short to 90% x VOUT(NOM) 450 700 950 mA Output current limit (for new chip) VIN = VOUT + 1V, VOUT short to 90% x VOUT(NOM) 540 780 PSRR Power-supply rejection ratio (for legacy chip) VIN - VOUT = 1V, frequency = 100Hz, Vr = 0.5Vpp, IOUT = 450mA 60 dB Power-supply rejection ratio (for new chip) VIN - VOUT = 1V, frequency = 1kHz, IOUT = 450mA 70 TJ Junction temperature –40 150 °CTSD(SHUTDOWN) Junction shutdown temperature (for new chip) 175 TSD(HYST) Hysteresis of thermal shutdown (for new chip) 20 ΔVOUT/ΔT Temperature output voltage drift (for legacy chip) 0.5 mV/K (1) Power dissipation is limited to 2W for device production testing purposes. The power dissipation is potentially higher during normal operation. See the Thermal Performance section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃. (2) Specified by design. (3) For the adjustable output this is tested in unity gain and resistor current is not included. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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5.6 Typical Characteristics

specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) 4.6 4.7 4.8 4.9 5.1 5.2 -45 -25 -5 15 35 55 75 95 115 135 155 TJ – Junction Temperature – °C VO – Output Voltage – V VI = 6 V Figure 5-1. Output Voltage vs Junction Temperature (Legacy Chip) 4.6 4.7 4.8 4.9 5.1 5.2 -45 -25 -5 15 35 55 75 95 115 135 155 TJ – Junction Temperature – °C VO – Output Voltage – V VI = 28 V Figure 5-2. Output Voltage vs Junction Temperature (Legacy Chip) 0 1 2 3 4 5 6 7 8 9 10 VI – Input Voltage – V VO – Output Voltage – V Figure 5-3. Output Voltage vs Input Voltage (Legacy Chip) Temperature qC Accuracy (%) -60 -40 -20 0 20 40 60 80 100 120 140 160 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0.25 0.3 500 mA 100 PA Figure 5-4. Output Accuracy vs Temperature (New Chip) Input Voltage (V) Output Voltage (V) 5 10 15 20 25 30 35 40 4.975 4.98 4.985 4.99 4.995 5.005 5.01 5.015 -55qC -40qC 0qC 25qC 85qC 125qC 150qC VOUT = 5V, IOUT = 150mA Figure 5-5. Line Regulation vs VIN (New Chip) Input Voltage (V) Output Voltage (V) 5 10 15 20 25 30 35 40 4.975 4.98 4.985 4.99 4.995 5.005 5.01 5.015 -55qC -40qC 0qC 25qC 85qC 125qC 150qC VOUT = 5V, IOUT = 5mA Figure 5-6. Line Regulation vs VIN (New Chip) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TL720M05-Q1

5.6 Typical Characteristics (continued)

specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) Input Voltage (V) Output Voltage (V) 5 10 15 20 25 30 35 40 4.975 4.98 4.985 4.99 4.995 5.005 5.01 5.015 -55qC -40qC 0qC 25qC 85qC 125qC 150qC VOUT = 5V, IOUT = 1mA Figure 5-7. Line Regulation vs VIN (New Chip) Output Current (mA) Output Voltage (V) 0 25 50 75 100 125 150 4.975 4.98 4.985 4.99 4.995 5.005 5.01 5.015 -55qC -40qC 0qC 25qC 85qC 125qC 150qC VOUT = 5V Figure 5-8. Load Regulation vs IOUT (New Chip) Input Voltage (V) Output Voltage (V) 0 5 10 15 20 25 30 35 40 4.99 4.9925 4.995 4.9975 5.0025 5.005 5.0075 5.01 -40 qC 25 qC 85 qC COUT = 10µF, VOUT = 5V Figure 5-9. Line Regulation at 50mA (New Chip) Input Voltage (V) Output Voltage (V) 0 5 10 15 20 25 30 35 40 4.99 4.9925 4.995 4.9975 5.0025 5.005 5.0075 5.01 -40 qC 25 qC 85 qC COUT = 10µF, VOUT = 5V Figure 5-10. Line Regulation at 100mA (New Chip) 100 200 300 400 500 600 700 800 900 1000 1100 1200 -45 -25 -5 15 35 55 75 95 115 135 155 TJ – Junction Temperature – °C IO – Output Current – mA Figure 5-11. Output Current vs Junction Temperature (Legacy Chip) 0.5 1.5 2.5 3.5 0 25 50 75 100 125 150 175 200 IO – Output Current – mA Iq – Current Consumption – mA VI = 13.5 V Figure 5-12. Current Consumption vs Output Current (Legacy Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) 0 50 100 150 200 250 300 350 400 IO – Output Current – mA Iq – Current Consumption – mA VI = 13.5 V Figure 5-13. Current Consumption vs Output Current (Legacy Chip) Input Voltage (V) Iq (PA) 5 10 15 20 25 30 35 40 -55qC -40qC 0qC 25qC 85qC 125qC 150qC Figure 5-14. Quiescent Current (IQ) vs VIN (New Chip) Input Voltage (V) Iq (PA) 0 5 10 15 20 25 30 35 40 100 125 150 175 -55qC -40qC 0qC 25qC 85qC 125qC 150qC VOUT = 5V Figure 5-15. Quiescent Current (IQ) vs VIN (New Chip) Output Current (mA) Ground Current (PA) 0 50 100 150 200 250 300 350 400 450 500 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 -55 qC -40 qC 0 qC 25 qC 85 qC 125 qC 150 qC Figure 5-16. Ground Current (IGND) vs IOUT (New Chip) Temperature (qC) Ground Current (PA) -75 -50 -25 0 25 50 75 100 125 150 271 272 273 274 275 276 277 278 279 280 281 Figure 5-17. Ground Current at 100mA (New Chip) Ambient Temperature (qC) Ground Current (PA) -75 -50 -25 0 25 50 75 100 125 150 Figure 5-18. Ground Current at 500µA (New Chip) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TL720M05-Q1

specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) 100 200 300 400 500 600 700 800 0 50 100 150 200 250 300 350 400 450 500 IO – Output Current – mA Vdo – Dropout Voltage – mV TJ = 25°C Figure 5-19. Dropout Voltage vs Output Current (Legacy Chip) Output Current (mA) Dropout Voltage (mV) 0 50 100 150 200 250 300 350 400 450 500 100 150 200 250 300 350 400 450 500 550 -55 qC -40 qC 0 qC 25 qC 85 qC 125 qC 150 qC VIN = 3V Figure 5-20. Dropout Voltage (VDO) vs IOUT (New Chip) 100 Frequency – Hz Ripple Rejection – dB VIN = 13.5 V Load = 1 mA COUT = 22 µF 10 100 1k 10k 100k Figure 5-21. Power-Supply Ripple Rejection vs Frequency (Legacy Chip) 100 Frequency – Hz Ripple Rejection – dB VIN = 13.5 V Load = 200 mA COUT = 22 µF 10 100 1k 10k 100k Figure 5-22. Power-Supply Ripple Rejection vs Frequency (Legacy Chip) 100 Frequency – Hz Ripple Rejection – dB VIN = 13.5 V Load = 400 mA COUT = 22 µF 10 100 1k 10k 100k Figure 5-23. Power-Supply Ripple Rejection vs Frequency (Legacy Chip) Frequency (Hz) Power Supply Rejection Ratio (dB) 10 100 1k 10k 100k 1M 10M 1 mA 10 mA 50 mA 150 mA 350 mA 500 mA COUT = 10µF (X7R 50V), VOUT = 5V Figure 5-24. Power-Supply Ripple Rejection vs Frequency and IOUT (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) Frequency (Hz) Power Supply Rejection Ratio (dB) 10 100 1k 10k 100k 1M 10M 6 V VIN 7 V VIN 10 VIN 13.5 V VIN COUT = 10µF (X7R 50V), IOUT = 500mA, VOUT = 5V Figure 5-25. Power-Supply Ripple Rejection vs Frequency and VIN (New Chip) Frequency (Hz) Noise (PV/—Hz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 10 100 1k 10k 100k 1M 10M IOUT 10 mA, 364.8 PVRMS 150 mA, 391.4 PVRMS 500 mA, 437.2 PVRMS COUT = 10µF (X7R 50V), VOUT = 5V Figure 5-26. Noise vs Frequency (Legacy Chip) Frequency (Hz) Noise (PV/—Hz) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 10 100 1k 10k 100k 1M 10M IOUT 10 mA, 252.5 PVRMS 150 mA, 267.6 PVRMS 500 mA, 293.8 PVRMS COUT = 10µF (X7R 50V), VOUT = 3.3V Figure 5-27. Noise vs Frequency (Legacy Chip) Time (Ps) Input Voltage (V) Output Voltage (V) 0 500 1000 1500 2000 2500 3000 0 -0.2 5 -0.15 10 -0.1 15 -0.05 20 0 25 0.05 30 0.1 35 0.15 40 0.2 45 0.25 VIN VOUT VOUT = 5V, IOUT = 1mA, VIN = 13.5V to 45V, slew rate = 2.7V/µs Figure 5-28. Line Transients (New Chip) Time (Ps) Input Voltage (V) AC Coupled Output Voltage (mV) 0 50 100 150 200 250 300 350 400 450 500 -10 -300 -8 -240 -6 -180 -4 -120 -2 -60 0 0 2 60 4 120 6 180 8 240 10 300 VIN VOUT VOUT = 5V, IOUT = 100mA, VIN = 5.5V to 6.5V, rise time = 1µs Figure 5-29. Line Transients (New Chip) Time (ms) AC Coupled Output Voltage (mV) Output Current (mA) -150 -300 -100 -200 -50 -100 0 0 50 100 100 200 150 300 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 100mA, slew rate = 1A/µs, COUT = 10µF Figure 5-30. Load Transient, No Load to 100mA (New Chip) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TL720M05-Q1

specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 20 40 60 80 100 120 140 160 180 200 -150 -300 -100 -200 -50 -100 0 0 50 100 100 200 150 300 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 100mA, slew rate = 1A/µs, COUT = 10µF Figure 5-31. Load Transient, No Load to 100mA Rising Edge (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 40 80 120 160 200 240 280 -50 -300 -40 -240 -30 -180 -20 -120 -10 -60 0 0 10 60 20 120 30 180 40 240 50 300 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 45mA to 105mA, slew rate = 0.1A/µs, COUT = 10µF Figure 5-32. Load Transient, 45mA to 105mA (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 20 40 60 80 100 120 140 160 180 200 -40 -250 -30 -200 -20 -150 -10 -100 0 -50 10 0 20 50 30 100 40 150 50 200 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 45mA to 105mA, slew rate = 0.1A/µs, COUT = 10µF Figure 5-33. Load Transient, 45mA to 105mA Rising Edge (New Chip) Time (ms) AC Coupled Output Voltage (mV) Output Current (mA) -150 -300 -100 -200 -50 -100 0 0 50 100 100 200 150 300 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 150mA, slew rate = 1A/µs, COUT = 10µF Figure 5-34. Load Transient, No Load to 150mA (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 20 40 60 80 100 120 140 160 180 200 -150 -300 -100 -200 -50 -100 0 0 50 100 100 200 150 300 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 150mA, slew rate = 1A/µs, COUT = 10µF Figure 5-35. Load Transient, No Load to 150mA Rising Edge (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 25 50 75 100 125 150 175 200 225 250 -150 0 -100 100 -50 200 0 300 50 400 100 500 150 600 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 150mA to 350mA, slew rate = 0.1A/µs, COUT = 10µF Figure 5-36. Load Transient, 150mA to 350mA (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) Time (ms) AC Coupled Output Voltage (mV) Output Current (mA) -300 -600 -250 -500 -200 -400 -150 -300 -100 -200 -50 -100 0 0 50 100 100 200 150 300 200 400 250 500 300 600 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 500mA, slew rate = 1A/µs, COUT = 10µF Figure 5-37. Load Transient, No Load to 500mA (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 20 40 60 80 100 120 140 160 180 200 -250 -300 -200 -150 -150 0 -100 150 -50 300 0 450 50 600 100 750 150 900 -40qC 25qC 150qC IOUT VOUT = 5V, IOUT = 0mA to 500mA, slew rate = 1A/µs, COUT = 10µF Figure 5-38. Load Transient, No Load to 500mA Rising Edge (New Chip) Temperature (qC) IOUT (mA) -75 -45 -15 15 45 75 105 135 650 651 652 653 654 655 656 657 658 659 660 Current Limit VIN = VOUT + 1V, VOUT = 90% × VOUT(NOM) Figure 5-39. Output Current Limit vs Temperature (New Chip) Time (Ps) Voltage (V) Output Current (mA) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 -5 -100 -2.5 0 0 100 2.5 200 5 300 7.5 400 10 500 12.5 600 15 700 17.5 800 20 900 Input Voltage Output Voltage Output Current VIN = VOUT + 1V, VOUT = 90% × VOUT(NOM) Figure 5-40. Start-Up Plot Inrush Current (New Chip) Temperature (qC) UVLO Threshold (V) -60 -40 -20 0 20 40 60 80 100 120 140 160 2.4 2.45 2.5 2.55 2.6 2.65 2.7 2.75 2.8 Falling Threshold Rising Threshold Figure 5-41. Undervoltage Lockout (UVLO) Threshold vs Temperature (New Chip) Injected current (mA) Output voltage (V) Figure 5-42. Output Voltage vs Injected Current (New Chip) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TL720M05-Q1

specified for new chip at TJ = –40°C to +150°C, VIN = 13.5V , IOUT = 100μA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted) Temperature (qC) -50 -25 0 25 50 75 100 125 150 175 200 ON OFF Figure 5-43. Thermal Shutdown (New Chip) Stable Region Load Current (A) ESR (Ω) Figure 5-44. ESR Stability vs Load Current (Legacy Chip) Stable Region Unstable Region Unstable Region Load Capacitance (µF) ESR (Ω) Figure 5-45. ESR Stability vs Load Capacitance (Legacy Chip) COUT (PF) ESR (:) 1 2 3 4 5 678 10 20 30 50 70 100 200300 500 0.0001 0.0002 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 x x x x x x x x x x x x xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx xxx xxx xxx xxx xxx xxx xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xxx xx xx xx xx xx xx xx xx xx xx xxxx xxx Stable region Figure 5-46. Stability, ESR vs COUT (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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6 Parameter Measurement Information

1000 µF CI2 100 nF IN OUT COUT 22 µF IGND GND VO IO VI Figure 6-1. Test Circuit www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TL720M05-Q1

7 Detailed Description

7.1 Overview

The TL720M05-Q1 is a low-dropout linear regulator (LDO) with improved transient performance that allows for quick response to changes in line or load conditions. The device also features a novel output overshoot reduction feature (new chip) that minimizes output overshoot during cold-crank conditions. During normal operation, the device has a tight DC accuracy (new chip) of ±1.15% over line, load, and temperature. The increased accuracy allows for the powering of sensitive analog loads or sensors. The TL720M05-Q1 has overtemperature protection and overcurrent protection during a load-short or fault condition on the output.

7.2 Functional Block Diagrams

T Sensor emperature Bandgap Reference GND Figure 7-1. Functional Block Diagram (Legacy Chip) Bandgap Thermal Shutdown UVLO Current Limit IN GND OUT Figure 7-2. Functional Block Diagram (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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7.3 Feature Description

7.3.1 Undervoltage Lockout

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage. Thus, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.2 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to T SD(shutdown) (typical). Thermal shutdown hysteresis makes sure the device resets (turns on) when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short. Thus the device cycles on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start-up is high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating Conditions table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the device internal protection circuitry is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(V IN – V OUT) × I CL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. Figure 7-3 shows a diagram of the current limit. VOUT(NOM) 0 V 0 mA VOUT ICLIRATED IOUT Brickwall Figure 7-3. Current Limit www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TL720M05-Q1

7.4 Device Functional Modes

Table 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table for parameter values. Table 7-1. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO Not applicable TJ > TSD(shutdown)

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. In this mode, the transient performance of the device becomes significantly degraded. During this mode, the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout potentially result in large output voltage deviations. When the device is in a steady dropout state, the pass transistor is driven fully on. This state is defined as when the device is in dropout, directly after being in a normal regulation state, but not during start up. Dropout occurs when VIN < VOUT(NOM) + VDO. When the input voltage returns to a value ≥ VOUT(NOM) + VDO, the output voltage potentially overshoots for a short period of time. V OUT(NOM) is the nominal output voltage and V DO is the dropout voltage. During dropout exit, the device pulls the pass transistor back into the linear region.

7.4.3 Disabled

Shutdown the device output by forcing the input voltage below the UVLO falling threshold (see the Electrical Characteristics table). When disabled, the pass transistor is turned off and internal circuits are shutdown. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

Based on the end-application, different values of external components are available. In some cases, an application requires a larger output capacitor during fast load steps to prevent a reset from occurring. Use a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.

8.1.1 Input and Output Capacitor Selection

8.1.1.1 Legacy Chip Capacitor Selection

The input capacitor (C IN) compensates for line fluctuation. Using a resistor of approximately 1 Ω in series with CIN dampens the oscillation of input inductivity and input capacitance. The output capacitor (C OUT) stabilizes the regulation circuit. The output is stable at C OUT ≥ 22μF and ESR ≤ 5Ω, which is within the operating temperature range.

8.1.1.2 New Chip Output Capacitor

The new chip version of the TL720M05-Q1 requires a 2.2µF or larger output capacitor (1µF or larger capacitance) for stability. An equivalent series resistance (ESR) between 0.001 Ω and 2 Ω is also required. For best transient performance, use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and ESR over temperature. When choosing a capacitor for a specific application, be mindful of the DC bias characteristics for the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the maximum recommended output capacitance is 220µF.

8.1.1.3 New Chip Input Capacitor

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. If the input supply is high impedance over a large range of frequencies, use several input capacitors in parallel to lower the impedance over frequency. Use a higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the input power source.

8.1.2 Dropout Voltage

Dropout voltage (V DO) is defined as V IN – V OUT at the rated output current (I RATED), where the pass transistor is fully on. V IN is the input voltage, V OUT is the output voltage, and I RATED is the maximum I OUT listed in the Recommended Operating Conditions table. At this operating point, the pass transistor is driven fully on. Dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage where the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source, on-state resistance (R DS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R =DS(ON) VDO IRA TED (1) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TL720M05-Q1

8.1.3 Reverse Current

Excessive reverse current potentially damages this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current potentially occur are outlined in this section, all of which exceed the absolute maximum rating of VOUT ≤ VIN + 0.3V.

• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated.

8.1.4 Power Dissipation (PD)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the PCB, and correct sizing of the thermal plane. Make sure the printed circuit board (PCB) area around the regulator has few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT (2) Note Power dissipation is minimized, and therefore greater efficiency achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. Make sure this pad area contains an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (T A) for the device. Power dissipation and junction temperature are most often related by the R θJA of the combined PCB and device package and the ambient air temperature (T A). RθJA is the junction-to-ambient thermal resistance. Equation 3 calculates this relationship. TJ = TA + (RθJA × PD) (3) Thermal resistance (R θJA) is highly dependent on the heat-spreading capability built into the particular PCB design. Therefore, R θJA varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area. This resistance is used as a relative measure of package thermal performance.

8.1.4.1 Thermal Performance Versus Copper Area

The most used thermal resistance parameter R θJA is highly dependent on the heat-spreading capability built into the particular PCB design. Therefore, R θJA varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area. R θJA is only used as a relative measure of package thermal performance. For a well-designed thermal layout, R θJA is actually the sum of R θJCbot plus the thermal resistance contribution by the PCB copper. RθJCbot is the package junction-to-case (bottom) thermal resistance. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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Figure 8-1. JEDEC Standard 2s2p PCB Figure 8-2 and Figure 8-3 show the functions of R θJA and ψJB versus copper area and thickness. These plots are generated with a 101.6mm × 101.6mm × 1.6mm PCB of two and four layers. For the 4-layer board, inner planes use 1oz copper thickness. Outer layers are simulated with both 1oz and 2oz copper thickness. A 3×4 (KVU package) array of thermal vias with a 300µm drill diameter and 25µm copper plating is located beneath the device thermal pad. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area. Cu Area Per Layer (cm2) Thermal Resistance - RTJA (qC/W) 0 10 20 30 40 50 60 70 80 90 100 95 4 Layer PCB, 1 oz copper

4 Layer PCB, 2 oz copper

2 Layer PCB, 1 oz copper

2 Layer PCB, 2 oz copper

Figure 8-2. RθJA vs Copper Area (KVU Package) Cu Area Per Layer (cm2) Thermal Resistance - <TJB (qC/W) 0 10 20 30 40 50 60 70 80 90 100

4 Layer PCB, 1 oz copper

2 Layer PCB, 2 oz copper Figure 8-3. ψJB vs Copper Area (KVU Package) www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TL720M05-Q1

8.1.4.2 Power Dissipation Versus Ambient Temperature

Figure 8-4 is based off of a JESD51-7 4-layer, high-K board. Estimate the allowable power dissipation with the following equation. Improve thermal dissipation in the JEDEC high-K layout by adding top layer copper and increasing the number of thermal vias. See the An empirical analysis of the impact of board layout on LDO thermal performance application note . If a good thermal layout is used, the allowable thermal dissipation is improved by up to 50%. (4) Ambient Temerature (qC) Maximum Power Dissipation (W) -40 -20 0 20 40 60 80 100 120 140 0.5 1.5 2.5 3.5 4.5 5.5 6.5 Figure 8-4. TL720M05-Q1 Allowable Power Dissipation

8.1.5 Estimating Junction Temperature

The JEDEC standard recommends using psi ( Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter ( ψJT) and junction-to-board characterization parameter ( ψJB). These parameters provide two methods for calculating the junction temperature (T J), as described in the following equations. Use the junction-to-top characterization parameter ( ψJT) with the temperature at the center-top of device package (T T) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD (5) where:

• PD is the dissipated power
• TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD (6) where:
• TB is the PCB surface temperature measured 1mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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8.2 Typical Application

Figure 8-5 shows a typical application circuit for the TL720M05-Q1. TL720M05-Q1 IN OUT GND Figure 8-5. Typical Application Diagram (New Chip)

8.2.1 Design Requirements

Use the parameters listed in Table 8-1 for this design example. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range 4V to 40V Output voltage 5V Output current rating 400mA Output capacitor range 10μF to 200μF

8.2.2 Detailed Design Procedure

8.2.2.1 Input Capacitor

The device requires an input decoupling capacitor, the value of which depends on the application. The typical recommended value for the decoupling capacitor is 1µF. Make sure the voltage rating is greater than the maximum input voltage.

8.2.2.2 Output Capacitor

The device (new chip) requires an output capacitor to stabilize the output voltage. Make sure the capacitor value is between 2.2µF and 200µF and the ESR range is between 1m Ω and 2Ω. For this design, use a low ESR, 10µF ceramic capacitor to improve transient performance. www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TL720M05-Q1

8.2.3 Application Curves

Channel 1: VIN, channel 2: VOUT Figure 8-6. Power-Up Waveform (Load = 50mA) (Legacy Chip) Channel 1: VIN, channel 2: VOUT Figure 8-7. Power-Down Waveform (Load = 50mA) (Legacy Chip) Frequency (Hz) Power Supply Rejection Ratio (dB) 10 100 1k 10k 100k 1M 10M 1 mA 10 mA 50 mA 150 mA 350 mA 500 mA Figure 8-8. Power-Supply Ripple Rejection vs Frequency and IOUT (New Chip) Time (Ps) Voltage (V) Output Current (mA) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 -5 -100 -2.5 0 0 100 2.5 200 5 300 7.5 400 10 500 12.5 600 15 700 17.5 800 20 900 Input Voltage Output Voltage Output Current VIN = VOUT + 1V, VOUT = 90% × VOUT(NOM) Figure 8-9. Start-Up Plot Inrush Current (New Chip) Time (Ps) AC Coupled Output Voltage (mV) Output Current (mA) 0 25 50 75 100 125 150 175 200 225 250 -150 0 -100 100 -50 200 0 300 50 400 100 500 150 600 -40qC 25qC 150qC IOUT Figure 8-10. Transient Response (New Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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8.3 Power Supply Recommendations

This device is designed for operation from a 4V to 40V input voltage supply. Make sure this input supply is well regulated. Do not place the input supply more than a few inches from the TL720M05-Q1. If this location is unavoidable, add a 22µF electrolytic capacitor and a ceramic bypass capacitor at the input.

8.4 Layout

8.4.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board. Place these components as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close as possible to each other. Use wide, component-side, copper surface for these connections. Using vias and long traces to the input and output capacitors is strongly discouraged and negatively affects system performance. Place a ground reference plane embedded in the PCB or located on the bottom side of the PCB opposite the components. This reference plane provides output voltage accuracy and shields noise. This plane also behaves similar to a thermal plane to spread (or sink) heat from the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements. www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TL720M05-Q1

8.4.2 Layout Examples

Figure 8-11. Layout Example Diagram for KVU, KTT Packages Vin OUT Vin 180 NC NC NC OUT NC NC NC GND NC IN NC NC NC NC NC NC TL720M05 HTSSOP NC NC NC NC Output filter capacitor Input bypass capacitor Figure 8-12. Layout Example Diagram for PWP Package (Legacy Chip) TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV709. Request the MLTLDO2EVM evaluation module (and related user's guide) at the TI website through the product folders.

9.1.2 Device Nomenclature

Table 9-1. Device Nomenclature PRODUCT(1) VOUT TL720M05Q xxxRQ1 xxx is the package designation (for example, KVU = TO-252; KTT = DDPAK/TO-263; PWP = HTSSOP). Q indicates that this device is a grade-1 device in accordance with the AEC-Q100 standard. Q1 indicates that this device is an automotive grade (AEC-Q100) device. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com.

9.1.3 Development Support

For the PSpice model, see the TPS7B88-Q1 (5-V Output) PSpice Transient Model.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, LDO Noise Demystified application note
• Texas Instruments, LDO PSRR Measurement Simplified application note
• Texas Instruments, MLTLDO2EVM-037 EVM user guide

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TL720M05-Q1

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (November 2014) to Revision I (May 2024) Page Changes from Revision G (June 2013) to Revision H (July 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TL720M05-Q1 SGLS380I – SEPTEMBER 2008 – REVISED MAY 2024 www.ti.com

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www.ti.com 23-May-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL720M05GQKVURQ1 ACTIVE TO-252 KVU 3 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 720M05Q Samples TL720M05GQKVURQ1M3 ACTIVE TO-252 KVU 3 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 720M05Q Samples TL720M05QKTTRQ1 ACTIVE DDPAK/ TO-263 KTT 3 500 RoHS & Green SN Level-3-245C-168 HR -40 to 125 T720M05Q Samples TL720M05QKVURQ1 ACTIVE TO-252 KVU 3 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 720M05Q Samples TL720M05QKVURQ1M3 ACTIVE TO-252 KVU 3 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 720M05Q Samples TL720M05QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 720M05Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 23-May-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL720M05GQKVURQ1 TO-252 KVU 3 2500 340.0 340.0 38.0 TL720M05GQKVURQ1M3 TO-252 KVU 3 2500 340.0 340.0 38.0 TL720M05QKVURQ1 TO-252 KVU 3 2500 340.0 340.0 38.0 TL720M05QKVURQ1M3 TO-252 KVU 3 2500 340.0 340.0 38.0 TL720M05QPWPRQ1 HTSSOP PWP 20 2000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 5.460 4.953 10.41 9.40 2.29 4.58 3X 0.890 0.635 1.02 0.61 1.27 0.89

2.52 MAX

0.61 0.46 4.32 MIN

5.21 MIN

-80 0.13 0.00 1.78 1.40 0.61 0.46 A 6.70 6.35 B 6.22 5.97 0.51 GAGE PLANE TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Shape may vary per different assembly sites. 4. Reference JEDEC registration TO-252.

0.25 C A B

SCALE 1.500 SEE DETAIL A EXPOSED THERMAL PAD NOTE 3 A 7.000 DETAIL A TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN ALL AROUND (6.15) (5.55)(4.58) 2X (1) 2X (2.75) TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X PKG SYMM NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers 6. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK DETAILS NOT TO SCALE NON SOLDER MASK DEFINED METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) 2X (2.75) 2X (1) (4.58) (1.33) TYP (1.18) TYP (0.14) (4.2) TO-252 - 2.52 mm max heightKVU0003A TO-252 4218915/A 02/2017 PKG NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 65% PRINTED SOLDER COVERAGE BY AREA SCALE:8X SYMM

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